rename_impl.hh (13652:45d94ac03a27) rename_impl.hh (13831:4fba790d88be)
1/*
2 * Copyright (c) 2010-2012, 2014-2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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369 assert(instsInProgress[tid] == 0);
370 }
371}
372
373template <class Impl>
374void
375DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, ThreadID tid)
376{
1/*
2 * Copyright (c) 2010-2012, 2014-2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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369 assert(instsInProgress[tid] == 0);
370 }
371}
372
373template <class Impl>
374void
375DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, ThreadID tid)
376{
377 DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid);
377 DPRINTF(Rename, "[tid:%i] [squash sn:%llu] Squashing instructions.\n",
378 tid,squash_seq_num);
378
379 // Clear the stall signal if rename was blocked or unblocking before.
380 // If it still needs to block, the blocking should happen the next
381 // cycle and there should be space to hold everything due to the squash.
382 if (renameStatus[tid] == Blocked ||
383 renameStatus[tid] == Unblocking) {
384 toDecode->renameUnblock[tid] = 1;
385
386 resumeSerialize = false;
387 serializeInst[tid] = NULL;
388 } else if (renameStatus[tid] == SerializeStall) {
389 if (serializeInst[tid]->seqNum <= squash_seq_num) {
379
380 // Clear the stall signal if rename was blocked or unblocking before.
381 // If it still needs to block, the blocking should happen the next
382 // cycle and there should be space to hold everything due to the squash.
383 if (renameStatus[tid] == Blocked ||
384 renameStatus[tid] == Unblocking) {
385 toDecode->renameUnblock[tid] = 1;
386
387 resumeSerialize = false;
388 serializeInst[tid] = NULL;
389 } else if (renameStatus[tid] == SerializeStall) {
390 if (serializeInst[tid]->seqNum <= squash_seq_num) {
390 DPRINTF(Rename, "Rename will resume serializing after squash\n");
391 DPRINTF(Rename, "[tid:%i] [squash sn:%llu] "
392 "Rename will resume serializing after squash\n",
393 tid,squash_seq_num);
391 resumeSerialize = true;
392 assert(serializeInst[tid]);
393 } else {
394 resumeSerialize = false;
395 toDecode->renameUnblock[tid] = 1;
396
397 serializeInst[tid] = NULL;
398 }

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515 block(tid);
516 resumeUnblocking = false;
517 toDecode->renameUnblock[tid] = false;
518 }
519 }
520
521 if (renameStatus[tid] == Running ||
522 renameStatus[tid] == Idle) {
394 resumeSerialize = true;
395 assert(serializeInst[tid]);
396 } else {
397 resumeSerialize = false;
398 toDecode->renameUnblock[tid] = 1;
399
400 serializeInst[tid] = NULL;
401 }

--- 116 unchanged lines hidden (view full) ---

518 block(tid);
519 resumeUnblocking = false;
520 toDecode->renameUnblock[tid] = false;
521 }
522 }
523
524 if (renameStatus[tid] == Running ||
525 renameStatus[tid] == Idle) {
523 DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run "
524 "stage.\n", tid);
526 DPRINTF(Rename,
527 "[tid:%i] "
528 "Not blocked, so attempting to run stage.\n",
529 tid);
525
526 renameInsts(tid);
527 } else if (renameStatus[tid] == Unblocking) {
528 renameInsts(tid);
529
530 if (validInsts()) {
531 // Add the current inputs to the skid buffer so they can be
532 // reprocessed when this stage unblocks.

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546 // Instructions can be either in the skid buffer or the queue of
547 // instructions coming from decode, depending on the status.
548 int insts_available = renameStatus[tid] == Unblocking ?
549 skidBuffer[tid].size() : insts[tid].size();
550
551 // Check the decode queue to see if instructions are available.
552 // If there are no available instructions to rename, then do nothing.
553 if (insts_available == 0) {
530
531 renameInsts(tid);
532 } else if (renameStatus[tid] == Unblocking) {
533 renameInsts(tid);
534
535 if (validInsts()) {
536 // Add the current inputs to the skid buffer so they can be
537 // reprocessed when this stage unblocks.

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551 // Instructions can be either in the skid buffer or the queue of
552 // instructions coming from decode, depending on the status.
553 int insts_available = renameStatus[tid] == Unblocking ?
554 skidBuffer[tid].size() : insts[tid].size();
555
556 // Check the decode queue to see if instructions are available.
557 // If there are no available instructions to rename, then do nothing.
558 if (insts_available == 0) {
554 DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n",
559 DPRINTF(Rename, "[tid:%i] Nothing to do, breaking out early.\n",
555 tid);
556 // Should I change status to idle?
557 ++renameIdleCycles;
558 return;
559 } else if (renameStatus[tid] == Unblocking) {
560 ++renameUnblockCycles;
561 } else if (renameStatus[tid] == Running) {
562 ++renameRunCycles;

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572
573 if (free_iq_entries < min_free_entries) {
574 min_free_entries = free_iq_entries;
575 source = IQ;
576 }
577
578 // Check if there's any space left.
579 if (min_free_entries <= 0) {
560 tid);
561 // Should I change status to idle?
562 ++renameIdleCycles;
563 return;
564 } else if (renameStatus[tid] == Unblocking) {
565 ++renameUnblockCycles;
566 } else if (renameStatus[tid] == Running) {
567 ++renameRunCycles;

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577
578 if (free_iq_entries < min_free_entries) {
579 min_free_entries = free_iq_entries;
580 source = IQ;
581 }
582
583 // Check if there's any space left.
584 if (min_free_entries <= 0) {
580 DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/ "
581 "entries.\n"
585 DPRINTF(Rename,
586 "[tid:%i] Blocking due to no free ROB/IQ/ entries.\n"
582 "ROB has %i free entries.\n"
583 "IQ has %i free entries.\n",
587 "ROB has %i free entries.\n"
588 "IQ has %i free entries.\n",
584 tid,
585 free_rob_entries,
586 free_iq_entries);
589 tid, free_rob_entries, free_iq_entries);
587
588 blockThisCycle = true;
589
590 block(tid);
591
592 incrFullStat(source);
593
594 return;
595 } else if (min_free_entries < insts_available) {
590
591 blockThisCycle = true;
592
593 block(tid);
594
595 incrFullStat(source);
596
597 return;
598 } else if (min_free_entries < insts_available) {
596 DPRINTF(Rename, "[tid:%u]: Will have to block this cycle."
597 "%i insts available, but only %i insts can be "
598 "renamed due to ROB/IQ/LSQ limits.\n",
599 DPRINTF(Rename,
600 "[tid:%i] "
601 "Will have to block this cycle. "
602 "%i insts available, "
603 "but only %i insts can be renamed due to ROB/IQ/LSQ limits.\n",
599 tid, insts_available, min_free_entries);
600
601 insts_available = min_free_entries;
602
603 blockThisCycle = true;
604
605 incrFullStat(source);
606 }
607
608 InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ?
609 skidBuffer[tid] : insts[tid];
610
604 tid, insts_available, min_free_entries);
605
606 insts_available = min_free_entries;
607
608 blockThisCycle = true;
609
610 incrFullStat(source);
611 }
612
613 InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ?
614 skidBuffer[tid] : insts[tid];
615
611 DPRINTF(Rename, "[tid:%u]: %i available instructions to "
612 "send iew.\n", tid, insts_available);
616 DPRINTF(Rename,
617 "[tid:%i] "
618 "%i available instructions to send iew.\n",
619 tid, insts_available);
613
620
614 DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts "
615 "dispatched to IQ last cycle.\n",
621 DPRINTF(Rename,
622 "[tid:%i] "
623 "%i insts pipelining from Rename | "
624 "%i insts dispatched to IQ last cycle.\n",
616 tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched);
617
618 // Handle serializing the next instruction if necessary.
619 if (serializeOnNextInst[tid]) {
620 if (emptyROB[tid] && instsInProgress[tid] == 0) {
621 // ROB already empty; no need to serialize.
622 serializeOnNextInst[tid] = false;
623 } else if (!insts_to_rename.empty()) {
624 insts_to_rename.front()->setSerializeBefore();
625 }
626 }
627
628 int renamed_insts = 0;
629
630 while (insts_available > 0 && toIEWIndex < renameWidth) {
625 tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched);
626
627 // Handle serializing the next instruction if necessary.
628 if (serializeOnNextInst[tid]) {
629 if (emptyROB[tid] && instsInProgress[tid] == 0) {
630 // ROB already empty; no need to serialize.
631 serializeOnNextInst[tid] = false;
632 } else if (!insts_to_rename.empty()) {
633 insts_to_rename.front()->setSerializeBefore();
634 }
635 }
636
637 int renamed_insts = 0;
638
639 while (insts_available > 0 && toIEWIndex < renameWidth) {
631 DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid);
640 DPRINTF(Rename, "[tid:%i] Sending instructions to IEW.\n", tid);
632
633 assert(!insts_to_rename.empty());
634
635 DynInstPtr inst = insts_to_rename.front();
636
637 //For all kind of instructions, check ROB and IQ first
638 //For load instruction, check LQ size and take into account the inflight loads
639 //For store instruction, check SQ size and take into account the inflight stores
640
641 if (inst->isLoad()) {
642 if (calcFreeLQEntries(tid) <= 0) {
641
642 assert(!insts_to_rename.empty());
643
644 DynInstPtr inst = insts_to_rename.front();
645
646 //For all kind of instructions, check ROB and IQ first
647 //For load instruction, check LQ size and take into account the inflight loads
648 //For store instruction, check SQ size and take into account the inflight stores
649
650 if (inst->isLoad()) {
651 if (calcFreeLQEntries(tid) <= 0) {
643 DPRINTF(Rename, "[tid:%u]: Cannot rename due to no free LQ\n");
652 DPRINTF(Rename, "[tid:%i] Cannot rename due to no free LQ\n");
644 source = LQ;
645 incrFullStat(source);
646 break;
647 }
648 }
649
650 if (inst->isStore() || inst->isAtomic()) {
651 if (calcFreeSQEntries(tid) <= 0) {
653 source = LQ;
654 incrFullStat(source);
655 break;
656 }
657 }
658
659 if (inst->isStore() || inst->isAtomic()) {
660 if (calcFreeSQEntries(tid) <= 0) {
652 DPRINTF(Rename, "[tid:%u]: Cannot rename due to no free SQ\n");
661 DPRINTF(Rename, "[tid:%i] Cannot rename due to no free SQ\n");
653 source = SQ;
654 incrFullStat(source);
655 break;
656 }
657 }
658
659 insts_to_rename.pop_front();
660
661 if (renameStatus[tid] == Unblocking) {
662 source = SQ;
663 incrFullStat(source);
664 break;
665 }
666 }
667
668 insts_to_rename.pop_front();
669
670 if (renameStatus[tid] == Unblocking) {
662 DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%s from rename "
663 "skidBuffer\n", tid, inst->seqNum, inst->pcState());
671 DPRINTF(Rename,
672 "[tid:%i] "
673 "Removing [sn:%llu] PC:%s from rename skidBuffer\n",
674 tid, inst->seqNum, inst->pcState());
664 }
665
666 if (inst->isSquashed()) {
675 }
676
677 if (inst->isSquashed()) {
667 DPRINTF(Rename, "[tid:%u]: instruction %i with PC %s is "
668 "squashed, skipping.\n", tid, inst->seqNum,
669 inst->pcState());
678 DPRINTF(Rename,
679 "[tid:%i] "
680 "instruction %i with PC %s is squashed, skipping.\n",
681 tid, inst->seqNum, inst->pcState());
670
671 ++renameSquashedInsts;
672
673 // Decrement how many instructions are available.
674 --insts_available;
675
676 continue;
677 }
678
682
683 ++renameSquashedInsts;
684
685 // Decrement how many instructions are available.
686 --insts_available;
687
688 continue;
689 }
690
679 DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with "
680 "PC %s.\n", tid, inst->seqNum, inst->pcState());
691 DPRINTF(Rename,
692 "[tid:%i] "
693 "Processing instruction [sn:%llu] with PC %s.\n",
694 tid, inst->seqNum, inst->pcState());
681
682 // Check here to make sure there are enough destination registers
683 // to rename to. Otherwise block.
684 if (!renameMap[tid]->canRename(inst->numIntDestRegs(),
685 inst->numFPDestRegs(),
686 inst->numVecDestRegs(),
687 inst->numVecElemDestRegs(),
688 inst->numVecPredDestRegs(),
689 inst->numCCDestRegs())) {
695
696 // Check here to make sure there are enough destination registers
697 // to rename to. Otherwise block.
698 if (!renameMap[tid]->canRename(inst->numIntDestRegs(),
699 inst->numFPDestRegs(),
700 inst->numVecDestRegs(),
701 inst->numVecElemDestRegs(),
702 inst->numVecPredDestRegs(),
703 inst->numCCDestRegs())) {
690 DPRINTF(Rename, "Blocking due to lack of free "
691 "physical registers to rename to.\n");
704 DPRINTF(Rename,
705 "Blocking due to "
706 " lack of free physical registers to rename to.\n");
692 blockThisCycle = true;
693 insts_to_rename.push_front(inst);
694 ++renameFullRegistersEvents;
695
696 break;
697 }
698
699 // Handle serializeAfter/serializeBefore instructions.

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791
792 while (!insts[tid].empty()) {
793 inst = insts[tid].front();
794
795 insts[tid].pop_front();
796
797 assert(tid == inst->threadNumber);
798
707 blockThisCycle = true;
708 insts_to_rename.push_front(inst);
709 ++renameFullRegistersEvents;
710
711 break;
712 }
713
714 // Handle serializeAfter/serializeBefore instructions.

--- 91 unchanged lines hidden (view full) ---

806
807 while (!insts[tid].empty()) {
808 inst = insts[tid].front();
809
810 insts[tid].pop_front();
811
812 assert(tid == inst->threadNumber);
813
799 DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC: %s into Rename "
814 DPRINTF(Rename, "[tid:%i] Inserting [sn:%llu] PC: %s into Rename "
800 "skidBuffer\n", tid, inst->seqNum, inst->pcState());
801
802 ++renameSkidInsts;
803
804 skidBuffer[tid].push_back(inst);
805 }
806
807 if (skidBuffer[tid].size() > skidBufferMax)
808 {
809 typename InstQueue::iterator it;
810 warn("Skidbuffer contents:\n");
811 for (it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++)
812 {
815 "skidBuffer\n", tid, inst->seqNum, inst->pcState());
816
817 ++renameSkidInsts;
818
819 skidBuffer[tid].push_back(inst);
820 }
821
822 if (skidBuffer[tid].size() > skidBufferMax)
823 {
824 typename InstQueue::iterator it;
825 warn("Skidbuffer contents:\n");
826 for (it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++)
827 {
813 warn("[tid:%u]: %s [sn:%i].\n", tid,
828 warn("[tid:%i] %s [sn:%llu].\n", tid,
814 (*it)->staticInst->disassemble(inst->instAddr()),
815 (*it)->seqNum);
816 }
817 panic("Skidbuffer Exceeded Max Size");
818 }
819}
820
821template <class Impl>

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889 }
890 }
891}
892
893template <class Impl>
894bool
895DefaultRename<Impl>::block(ThreadID tid)
896{
829 (*it)->staticInst->disassemble(inst->instAddr()),
830 (*it)->seqNum);
831 }
832 panic("Skidbuffer Exceeded Max Size");
833 }
834}
835
836template <class Impl>

--- 67 unchanged lines hidden (view full) ---

904 }
905 }
906}
907
908template <class Impl>
909bool
910DefaultRename<Impl>::block(ThreadID tid)
911{
897 DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid);
912 DPRINTF(Rename, "[tid:%i] Blocking.\n", tid);
898
899 // Add the current inputs onto the skid buffer, so they can be
900 // reprocessed when this stage unblocks.
901 skidInsert(tid);
902
903 // Only signal backwards to block if the previous stages do not think
904 // rename is already blocked.
905 if (renameStatus[tid] != Blocked) {

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923
924 return false;
925}
926
927template <class Impl>
928bool
929DefaultRename<Impl>::unblock(ThreadID tid)
930{
913
914 // Add the current inputs onto the skid buffer, so they can be
915 // reprocessed when this stage unblocks.
916 skidInsert(tid);
917
918 // Only signal backwards to block if the previous stages do not think
919 // rename is already blocked.
920 if (renameStatus[tid] != Blocked) {

--- 17 unchanged lines hidden (view full) ---

938
939 return false;
940}
941
942template <class Impl>
943bool
944DefaultRename<Impl>::unblock(ThreadID tid)
945{
931 DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid);
946 DPRINTF(Rename, "[tid:%i] Trying to unblock.\n", tid);
932
933 // Rename is done unblocking if the skid buffer is empty.
934 if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) {
935
947
948 // Rename is done unblocking if the skid buffer is empty.
949 if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) {
950
936 DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid);
951 DPRINTF(Rename, "[tid:%i] Done unblocking.\n", tid);
937
938 toDecode->renameUnblock[tid] = true;
939 wroteToTimeBuffer = true;
940
941 renameStatus[tid] = Running;
942 return true;
943 }
944

--- 10 unchanged lines hidden (view full) ---

955 // After a syscall squashes everything, the history buffer may be empty
956 // but the ROB may still be squashing instructions.
957 // Go through the most recent instructions, undoing the mappings
958 // they did and freeing up the registers.
959 while (!historyBuffer[tid].empty() &&
960 hb_it->instSeqNum > squashed_seq_num) {
961 assert(hb_it != historyBuffer[tid].end());
962
952
953 toDecode->renameUnblock[tid] = true;
954 wroteToTimeBuffer = true;
955
956 renameStatus[tid] = Running;
957 return true;
958 }
959

--- 10 unchanged lines hidden (view full) ---

970 // After a syscall squashes everything, the history buffer may be empty
971 // but the ROB may still be squashing instructions.
972 // Go through the most recent instructions, undoing the mappings
973 // they did and freeing up the registers.
974 while (!historyBuffer[tid].empty() &&
975 hb_it->instSeqNum > squashed_seq_num) {
976 assert(hb_it != historyBuffer[tid].end());
977
963 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
978 DPRINTF(Rename, "[tid:%i] Removing history entry with sequence "
964 "number %i.\n", tid, hb_it->instSeqNum);
965
966 // Undo the rename mapping only if it was really a change.
967 // Special regs that are not really renamed (like misc regs
968 // and the zero reg) can be recognized because the new mapping
969 // is the same as the old one. While it would be merely a
970 // waste of time to update the rename table, we definitely
971 // don't want to put these on the free list.

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992 // Check if we need to change vector renaming mode after squashing
993 cpu->switchRenameMode(tid, freeList);
994}
995
996template<class Impl>
997void
998DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid)
999{
979 "number %i.\n", tid, hb_it->instSeqNum);
980
981 // Undo the rename mapping only if it was really a change.
982 // Special regs that are not really renamed (like misc regs
983 // and the zero reg) can be recognized because the new mapping
984 // is the same as the old one. While it would be merely a
985 // waste of time to update the rename table, we definitely
986 // don't want to put these on the free list.

--- 20 unchanged lines hidden (view full) ---

1007 // Check if we need to change vector renaming mode after squashing
1008 cpu->switchRenameMode(tid, freeList);
1009}
1010
1011template<class Impl>
1012void
1013DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid)
1014{
1000 DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the "
1001 "history buffer %u (size=%i), until [sn:%lli].\n",
1015 DPRINTF(Rename, "[tid:%i] Removing a committed instruction from the "
1016 "history buffer %u (size=%i), until [sn:%llu].\n",
1002 tid, tid, historyBuffer[tid].size(), inst_seq_num);
1003
1004 typename std::list<RenameHistory>::iterator hb_it =
1005 historyBuffer[tid].end();
1006
1007 --hb_it;
1008
1009 if (historyBuffer[tid].empty()) {
1017 tid, tid, historyBuffer[tid].size(), inst_seq_num);
1018
1019 typename std::list<RenameHistory>::iterator hb_it =
1020 historyBuffer[tid].end();
1021
1022 --hb_it;
1023
1024 if (historyBuffer[tid].empty()) {
1010 DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid);
1025 DPRINTF(Rename, "[tid:%i] History buffer is empty.\n", tid);
1011 return;
1012 } else if (hb_it->instSeqNum > inst_seq_num) {
1026 return;
1027 } else if (hb_it->instSeqNum > inst_seq_num) {
1013 DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure "
1014 "that a syscall happened recently.\n", tid);
1028 DPRINTF(Rename, "[tid:%i] [sn:%llu] "
1029 "Old sequence number encountered. "
1030 "Ensure that a syscall happened recently.\n",
1031 tid,inst_seq_num);
1015 return;
1016 }
1017
1018 // Commit all the renames up until (and including) the committed sequence
1019 // number. Some or even all of the committed instructions may not have
1020 // rename histories if they did not have destination registers that were
1021 // renamed.
1022 while (!historyBuffer[tid].empty() &&
1023 hb_it != historyBuffer[tid].end() &&
1024 hb_it->instSeqNum <= inst_seq_num) {
1025
1032 return;
1033 }
1034
1035 // Commit all the renames up until (and including) the committed sequence
1036 // number. Some or even all of the committed instructions may not have
1037 // rename histories if they did not have destination registers that were
1038 // renamed.
1039 while (!historyBuffer[tid].empty() &&
1040 hb_it != historyBuffer[tid].end() &&
1041 hb_it->instSeqNum <= inst_seq_num) {
1042
1026 DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i (%s), "
1027 "[sn:%lli].\n",
1043 DPRINTF(Rename, "[tid:%i] Freeing up older rename of reg %i (%s), "
1044 "[sn:%llu].\n",
1028 tid, hb_it->prevPhysReg->index(),
1029 hb_it->prevPhysReg->className(),
1030 hb_it->instSeqNum);
1031
1032 // Don't free special phys regs like misc and zero regs, which
1033 // can be recognized because the new mapping is the same as
1034 // the old one.
1035 if (hb_it->newPhysReg != hb_it->prevPhysReg) {

--- 38 unchanged lines hidden (view full) ---

1074 case CCRegClass:
1075 case MiscRegClass:
1076 break;
1077
1078 default:
1079 panic("Invalid register class: %d.", src_reg.classValue());
1080 }
1081
1045 tid, hb_it->prevPhysReg->index(),
1046 hb_it->prevPhysReg->className(),
1047 hb_it->instSeqNum);
1048
1049 // Don't free special phys regs like misc and zero regs, which
1050 // can be recognized because the new mapping is the same as
1051 // the old one.
1052 if (hb_it->newPhysReg != hb_it->prevPhysReg) {

--- 38 unchanged lines hidden (view full) ---

1091 case CCRegClass:
1092 case MiscRegClass:
1093 break;
1094
1095 default:
1096 panic("Invalid register class: %d.", src_reg.classValue());
1097 }
1098
1082 DPRINTF(Rename, "[tid:%u]: Looking up %s arch reg %i"
1083 ", got phys reg %i (%s)\n", tid,
1084 src_reg.className(), src_reg.index(),
1085 renamed_reg->index(),
1099 DPRINTF(Rename,
1100 "[tid:%i] "
1101 "Looking up %s arch reg %i, got phys reg %i (%s)\n",
1102 tid, src_reg.className(),
1103 src_reg.index(), renamed_reg->index(),
1086 renamed_reg->className());
1087
1088 inst->renameSrcReg(src_idx, renamed_reg);
1089
1090 // See if the register is ready or not.
1091 if (scoreboard->getReg(renamed_reg)) {
1104 renamed_reg->className());
1105
1106 inst->renameSrcReg(src_idx, renamed_reg);
1107
1108 // See if the register is ready or not.
1109 if (scoreboard->getReg(renamed_reg)) {
1092 DPRINTF(Rename, "[tid:%u]: Register %d (flat: %d) (%s)"
1093 " is ready.\n", tid, renamed_reg->index(),
1094 renamed_reg->flatIndex(),
1110 DPRINTF(Rename,
1111 "[tid:%i] "
1112 "Register %d (flat: %d) (%s) is ready.\n",
1113 tid, renamed_reg->index(), renamed_reg->flatIndex(),
1095 renamed_reg->className());
1096
1097 inst->markSrcRegReady(src_idx);
1098 } else {
1114 renamed_reg->className());
1115
1116 inst->markSrcRegReady(src_idx);
1117 } else {
1099 DPRINTF(Rename, "[tid:%u]: Register %d (flat: %d) (%s)"
1100 " is not ready.\n", tid, renamed_reg->index(),
1101 renamed_reg->flatIndex(),
1118 DPRINTF(Rename,
1119 "[tid:%i] "
1120 "Register %d (flat: %d) (%s) is not ready.\n",
1121 tid, renamed_reg->index(), renamed_reg->flatIndex(),
1102 renamed_reg->className());
1103 }
1104
1105 ++renameRenameLookups;
1106 }
1107}
1108
1109template <class Impl>

--- 13 unchanged lines hidden (view full) ---

1123
1124 rename_result = map->rename(flat_dest_regid);
1125
1126 inst->flattenDestReg(dest_idx, flat_dest_regid);
1127
1128 // Mark Scoreboard entry as not ready
1129 scoreboard->unsetReg(rename_result.first);
1130
1122 renamed_reg->className());
1123 }
1124
1125 ++renameRenameLookups;
1126 }
1127}
1128
1129template <class Impl>

--- 13 unchanged lines hidden (view full) ---

1143
1144 rename_result = map->rename(flat_dest_regid);
1145
1146 inst->flattenDestReg(dest_idx, flat_dest_regid);
1147
1148 // Mark Scoreboard entry as not ready
1149 scoreboard->unsetReg(rename_result.first);
1150
1131 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i (%s) to physical "
1132 "reg %i (%i).\n", tid, dest_reg.index(),
1133 dest_reg.className(),
1151 DPRINTF(Rename,
1152 "[tid:%i] "
1153 "Renaming arch reg %i (%s) to physical reg %i (%i).\n",
1154 tid, dest_reg.index(), dest_reg.className(),
1134 rename_result.first->index(),
1135 rename_result.first->flatIndex());
1136
1137 // Record the rename information so that a history can be kept.
1138 RenameHistory hb_entry(inst->seqNum, flat_dest_regid,
1139 rename_result.first,
1140 rename_result.second);
1141
1142 historyBuffer[tid].push_front(hb_entry);
1143
1155 rename_result.first->index(),
1156 rename_result.first->flatIndex());
1157
1158 // Record the rename information so that a history can be kept.
1159 RenameHistory hb_entry(inst->seqNum, flat_dest_regid,
1160 rename_result.first,
1161 rename_result.second);
1162
1163 historyBuffer[tid].push_front(hb_entry);
1164
1144 DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer "
1145 "(size=%i), [sn:%lli].\n",tid,
1146 historyBuffer[tid].size(),
1147 (*historyBuffer[tid].begin()).instSeqNum);
1165 DPRINTF(Rename, "[tid:%i] [sn:%llu] "
1166 "Adding instruction to history buffer (size=%i).\n",
1167 tid,(*historyBuffer[tid].begin()).instSeqNum,
1168 historyBuffer[tid].size());
1148
1149 // Tell the instruction to rename the appropriate destination
1150 // register (dest_idx) to the new physical register
1151 // (rename_result.first), and record the previous physical
1152 // register that the same logical register was renamed to
1153 // (rename_result.second).
1154 inst->renameDestReg(dest_idx,
1155 rename_result.first,

--- 5 unchanged lines hidden (view full) ---

1161
1162template <class Impl>
1163inline int
1164DefaultRename<Impl>::calcFreeROBEntries(ThreadID tid)
1165{
1166 int num_free = freeEntries[tid].robEntries -
1167 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1168
1169
1170 // Tell the instruction to rename the appropriate destination
1171 // register (dest_idx) to the new physical register
1172 // (rename_result.first), and record the previous physical
1173 // register that the same logical register was renamed to
1174 // (rename_result.second).
1175 inst->renameDestReg(dest_idx,
1176 rename_result.first,

--- 5 unchanged lines hidden (view full) ---

1182
1183template <class Impl>
1184inline int
1185DefaultRename<Impl>::calcFreeROBEntries(ThreadID tid)
1186{
1187 int num_free = freeEntries[tid].robEntries -
1188 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1189
1169 //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free);
1190 //DPRINTF(Rename,"[tid:%i] %i rob free\n",tid,num_free);
1170
1171 return num_free;
1172}
1173
1174template <class Impl>
1175inline int
1176DefaultRename<Impl>::calcFreeIQEntries(ThreadID tid)
1177{
1178 int num_free = freeEntries[tid].iqEntries -
1179 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1180
1191
1192 return num_free;
1193}
1194
1195template <class Impl>
1196inline int
1197DefaultRename<Impl>::calcFreeIQEntries(ThreadID tid)
1198{
1199 int num_free = freeEntries[tid].iqEntries -
1200 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1201
1181 //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free);
1202 //DPRINTF(Rename,"[tid:%i] %i iq free\n",tid,num_free);
1182
1183 return num_free;
1184}
1185
1186template <class Impl>
1187inline int
1188DefaultRename<Impl>::calcFreeLQEntries(ThreadID tid)
1189{
1190 int num_free = freeEntries[tid].lqEntries -
1191 (loadsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLQ);
1203
1204 return num_free;
1205}
1206
1207template <class Impl>
1208inline int
1209DefaultRename<Impl>::calcFreeLQEntries(ThreadID tid)
1210{
1211 int num_free = freeEntries[tid].lqEntries -
1212 (loadsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLQ);
1192 DPRINTF(Rename, "calcFreeLQEntries: free lqEntries: %d, loadsInProgress: %d, "
1193 "loads dispatchedToLQ: %d\n", freeEntries[tid].lqEntries,
1194 loadsInProgress[tid], fromIEW->iewInfo[tid].dispatchedToLQ);
1213 DPRINTF(Rename,
1214 "calcFreeLQEntries: free lqEntries: %d, loadsInProgress: %d, "
1215 "loads dispatchedToLQ: %d\n",
1216 freeEntries[tid].lqEntries, loadsInProgress[tid],
1217 fromIEW->iewInfo[tid].dispatchedToLQ);
1195 return num_free;
1196}
1197
1198template <class Impl>
1199inline int
1200DefaultRename<Impl>::calcFreeSQEntries(ThreadID tid)
1201{
1202 int num_free = freeEntries[tid].sqEntries -

--- 34 unchanged lines hidden (view full) ---

1237
1238template <class Impl>
1239bool
1240DefaultRename<Impl>::checkStall(ThreadID tid)
1241{
1242 bool ret_val = false;
1243
1244 if (stalls[tid].iew) {
1218 return num_free;
1219}
1220
1221template <class Impl>
1222inline int
1223DefaultRename<Impl>::calcFreeSQEntries(ThreadID tid)
1224{
1225 int num_free = freeEntries[tid].sqEntries -

--- 34 unchanged lines hidden (view full) ---

1260
1261template <class Impl>
1262bool
1263DefaultRename<Impl>::checkStall(ThreadID tid)
1264{
1265 bool ret_val = false;
1266
1267 if (stalls[tid].iew) {
1245 DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid);
1268 DPRINTF(Rename,"[tid:%i] Stall from IEW stage detected.\n", tid);
1246 ret_val = true;
1247 } else if (calcFreeROBEntries(tid) <= 0) {
1269 ret_val = true;
1270 } else if (calcFreeROBEntries(tid) <= 0) {
1248 DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid);
1271 DPRINTF(Rename,"[tid:%i] Stall: ROB has 0 free entries.\n", tid);
1249 ret_val = true;
1250 } else if (calcFreeIQEntries(tid) <= 0) {
1272 ret_val = true;
1273 } else if (calcFreeIQEntries(tid) <= 0) {
1251 DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid);
1274 DPRINTF(Rename,"[tid:%i] Stall: IQ has 0 free entries.\n", tid);
1252 ret_val = true;
1253 } else if (calcFreeLQEntries(tid) <= 0 && calcFreeSQEntries(tid) <= 0) {
1275 ret_val = true;
1276 } else if (calcFreeLQEntries(tid) <= 0 && calcFreeSQEntries(tid) <= 0) {
1254 DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid);
1277 DPRINTF(Rename,"[tid:%i] Stall: LSQ has 0 free entries.\n", tid);
1255 ret_val = true;
1256 } else if (renameMap[tid]->numFreeEntries() <= 0) {
1278 ret_val = true;
1279 } else if (renameMap[tid]->numFreeEntries() <= 0) {
1257 DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid);
1280 DPRINTF(Rename,"[tid:%i] Stall: RenameMap has 0 free entries.\n", tid);
1258 ret_val = true;
1259 } else if (renameStatus[tid] == SerializeStall &&
1260 (!emptyROB[tid] || instsInProgress[tid])) {
1281 ret_val = true;
1282 } else if (renameStatus[tid] == SerializeStall &&
1283 (!emptyROB[tid] || instsInProgress[tid])) {
1261 DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not "
1284 DPRINTF(Rename,"[tid:%i] Stall: Serialize stall and ROB is not "
1262 "empty.\n",
1263 tid);
1264 ret_val = true;
1265 }
1266
1267 return ret_val;
1268}
1269

--- 10 unchanged lines hidden (view full) ---

1280 }
1281
1282 if (fromCommit->commitInfo[tid].usedROB) {
1283 freeEntries[tid].robEntries =
1284 fromCommit->commitInfo[tid].freeROBEntries;
1285 emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB;
1286 }
1287
1285 "empty.\n",
1286 tid);
1287 ret_val = true;
1288 }
1289
1290 return ret_val;
1291}
1292

--- 10 unchanged lines hidden (view full) ---

1303 }
1304
1305 if (fromCommit->commitInfo[tid].usedROB) {
1306 freeEntries[tid].robEntries =
1307 fromCommit->commitInfo[tid].freeROBEntries;
1308 emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB;
1309 }
1310
1288 DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, "
1311 DPRINTF(Rename, "[tid:%i] Free IQ: %i, Free ROB: %i, "
1289 "Free LQ: %i, Free SQ: %i, FreeRM %i(%i %i %i %i %i)\n",
1290 tid,
1291 freeEntries[tid].iqEntries,
1292 freeEntries[tid].robEntries,
1293 freeEntries[tid].lqEntries,
1294 freeEntries[tid].sqEntries,
1295 renameMap[tid]->numFreeEntries(),
1296 renameMap[tid]->numFreeIntEntries(),
1297 renameMap[tid]->numFreeFloatEntries(),
1298 renameMap[tid]->numFreeVecEntries(),
1299 renameMap[tid]->numFreePredEntries(),
1300 renameMap[tid]->numFreeCCEntries());
1301
1312 "Free LQ: %i, Free SQ: %i, FreeRM %i(%i %i %i %i %i)\n",
1313 tid,
1314 freeEntries[tid].iqEntries,
1315 freeEntries[tid].robEntries,
1316 freeEntries[tid].lqEntries,
1317 freeEntries[tid].sqEntries,
1318 renameMap[tid]->numFreeEntries(),
1319 renameMap[tid]->numFreeIntEntries(),
1320 renameMap[tid]->numFreeFloatEntries(),
1321 renameMap[tid]->numFreeVecEntries(),
1322 renameMap[tid]->numFreePredEntries(),
1323 renameMap[tid]->numFreeCCEntries());
1324
1302 DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n",
1325 DPRINTF(Rename, "[tid:%i] %i instructions not yet in ROB\n",
1303 tid, instsInProgress[tid]);
1304}
1305
1306template <class Impl>
1307bool
1308DefaultRename<Impl>::checkSignalsAndUpdate(ThreadID tid)
1309{
1310 // Check if there's a squash signal, squash if there is

--- 5 unchanged lines hidden (view full) ---

1316 // check if squashing is not high. Switch to running this cycle.
1317 // If status was serialize stall
1318 // check if ROB is empty and no insts are in flight to the ROB
1319
1320 readFreeEntries(tid);
1321 readStallSignals(tid);
1322
1323 if (fromCommit->commitInfo[tid].squash) {
1326 tid, instsInProgress[tid]);
1327}
1328
1329template <class Impl>
1330bool
1331DefaultRename<Impl>::checkSignalsAndUpdate(ThreadID tid)
1332{
1333 // Check if there's a squash signal, squash if there is

--- 5 unchanged lines hidden (view full) ---

1339 // check if squashing is not high. Switch to running this cycle.
1340 // If status was serialize stall
1341 // check if ROB is empty and no insts are in flight to the ROB
1342
1343 readFreeEntries(tid);
1344 readStallSignals(tid);
1345
1346 if (fromCommit->commitInfo[tid].squash) {
1324 DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from "
1347 DPRINTF(Rename, "[tid:%i] Squashing instructions due to squash from "
1325 "commit.\n", tid);
1326
1327 squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
1328
1329 return true;
1330 }
1331
1332 if (checkStall(tid)) {
1333 return block(tid);
1334 }
1335
1336 if (renameStatus[tid] == Blocked) {
1348 "commit.\n", tid);
1349
1350 squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
1351
1352 return true;
1353 }
1354
1355 if (checkStall(tid)) {
1356 return block(tid);
1357 }
1358
1359 if (renameStatus[tid] == Blocked) {
1337 DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n",
1360 DPRINTF(Rename, "[tid:%i] Done blocking, switching to unblocking.\n",
1338 tid);
1339
1340 renameStatus[tid] = Unblocking;
1341
1342 unblock(tid);
1343
1344 return true;
1345 }
1346
1347 if (renameStatus[tid] == Squashing) {
1348 // Switch status to running if rename isn't being told to block or
1349 // squash this cycle.
1350 if (resumeSerialize) {
1361 tid);
1362
1363 renameStatus[tid] = Unblocking;
1364
1365 unblock(tid);
1366
1367 return true;
1368 }
1369
1370 if (renameStatus[tid] == Squashing) {
1371 // Switch status to running if rename isn't being told to block or
1372 // squash this cycle.
1373 if (resumeSerialize) {
1351 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n",
1352 tid);
1374 DPRINTF(Rename,
1375 "[tid:%i] Done squashing, switching to serialize.\n", tid);
1353
1354 renameStatus[tid] = SerializeStall;
1355 return true;
1356 } else if (resumeUnblocking) {
1376
1377 renameStatus[tid] = SerializeStall;
1378 return true;
1379 } else if (resumeUnblocking) {
1357 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n",
1380 DPRINTF(Rename,
1381 "[tid:%i] Done squashing, switching to unblocking.\n",
1358 tid);
1359 renameStatus[tid] = Unblocking;
1360 return true;
1361 } else {
1382 tid);
1383 renameStatus[tid] = Unblocking;
1384 return true;
1385 } else {
1362 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n",
1386 DPRINTF(Rename, "[tid:%i] Done squashing, switching to running.\n",
1363 tid);
1387 tid);
1364
1365 renameStatus[tid] = Running;
1366 return false;
1367 }
1368 }
1369
1370 if (renameStatus[tid] == SerializeStall) {
1371 // Stall ends once the ROB is free.
1388 renameStatus[tid] = Running;
1389 return false;
1390 }
1391 }
1392
1393 if (renameStatus[tid] == SerializeStall) {
1394 // Stall ends once the ROB is free.
1372 DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to "
1395 DPRINTF(Rename, "[tid:%i] Done with serialize stall, switching to "
1373 "unblocking.\n", tid);
1374
1375 DynInstPtr serial_inst = serializeInst[tid];
1376
1377 renameStatus[tid] = Unblocking;
1378
1379 unblock(tid);
1380
1396 "unblocking.\n", tid);
1397
1398 DynInstPtr serial_inst = serializeInst[tid];
1399
1400 renameStatus[tid] = Unblocking;
1401
1402 unblock(tid);
1403
1381 DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with "
1404 DPRINTF(Rename, "[tid:%i] Processing instruction [%lli] with "
1382 "PC %s.\n", tid, serial_inst->seqNum, serial_inst->pcState());
1383
1384 // Put instruction into queue here.
1385 serial_inst->clearSerializeBefore();
1386
1387 if (!skidBuffer[tid].empty()) {
1388 skidBuffer[tid].push_front(serial_inst);
1389 } else {
1390 insts[tid].push_front(serial_inst);
1391 }
1392
1405 "PC %s.\n", tid, serial_inst->seqNum, serial_inst->pcState());
1406
1407 // Put instruction into queue here.
1408 serial_inst->clearSerializeBefore();
1409
1410 if (!skidBuffer[tid].empty()) {
1411 skidBuffer[tid].push_front(serial_inst);
1412 } else {
1413 insts[tid].push_front(serial_inst);
1414 }
1415
1393 DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename."
1416 DPRINTF(Rename, "[tid:%i] Instruction must be processed by rename."
1394 " Adding to front of list.\n", tid);
1395
1396 serializeInst[tid] = NULL;
1397
1398 return true;
1399 }
1400
1401 // If we've reached this point, we have not gotten any signals that

--- 68 unchanged lines hidden --- 		1417 " Adding to front of list.\n", tid);
1418
1419 serializeInst[tid] = NULL;
1420
1421 return true;
1422 }
1423
1424 // If we've reached this point, we have not gotten any signals that

--- 68 unchanged lines hidden ---