rename_impl.hh (13601:f5c84915eb7f) rename_impl.hh (13610:5d5404ac6288)
1/*
2 * Copyright (c) 2010-2012, 2014-2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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191 fpRenameLookups
192 .name(name() + ".fp_rename_lookups")
193 .desc("Number of floating rename lookups")
194 .prereq(fpRenameLookups);
195 vecRenameLookups
196 .name(name() + ".vec_rename_lookups")
197 .desc("Number of vector rename lookups")
198 .prereq(vecRenameLookups);
1/*
2 * Copyright (c) 2010-2012, 2014-2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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191 fpRenameLookups
192 .name(name() + ".fp_rename_lookups")
193 .desc("Number of floating rename lookups")
194 .prereq(fpRenameLookups);
195 vecRenameLookups
196 .name(name() + ".vec_rename_lookups")
197 .desc("Number of vector rename lookups")
198 .prereq(vecRenameLookups);
199 vecPredRenameLookups
200 .name(name() + ".vec_pred_rename_lookups")
201 .desc("Number of vector predicate rename lookups")
202 .prereq(vecPredRenameLookups);
199}
200
201template <class Impl>
202void
203DefaultRename<Impl>::regProbePoints()
204{
205 ppRename = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Rename");
206 ppSquashInRename = new ProbePointArg<SeqNumRegPair>(cpu->getProbeManager(),

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654 "PC %s.\n", tid, inst->seqNum, inst->pcState());
655
656 // Check here to make sure there are enough destination registers
657 // to rename to. Otherwise block.
658 if (!renameMap[tid]->canRename(inst->numIntDestRegs(),
659 inst->numFPDestRegs(),
660 inst->numVecDestRegs(),
661 inst->numVecElemDestRegs(),
203}
204
205template <class Impl>
206void
207DefaultRename<Impl>::regProbePoints()
208{
209 ppRename = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Rename");
210 ppSquashInRename = new ProbePointArg<SeqNumRegPair>(cpu->getProbeManager(),

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658 "PC %s.\n", tid, inst->seqNum, inst->pcState());
659
660 // Check here to make sure there are enough destination registers
661 // to rename to. Otherwise block.
662 if (!renameMap[tid]->canRename(inst->numIntDestRegs(),
663 inst->numFPDestRegs(),
664 inst->numVecDestRegs(),
665 inst->numVecElemDestRegs(),
666 inst->numVecPredDestRegs(),
662 inst->numCCDestRegs())) {
663 DPRINTF(Rename, "Blocking due to lack of free "
664 "physical registers to rename to.\n");
665 blockThisCycle = true;
666 insts_to_rename.push_front(inst);
667 ++renameFullRegistersEvents;
668
669 break;

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1036 break;
1037 case FloatRegClass:
1038 fpRenameLookups++;
1039 break;
1040 case VecRegClass:
1041 case VecElemClass:
1042 vecRenameLookups++;
1043 break;
667 inst->numCCDestRegs())) {
668 DPRINTF(Rename, "Blocking due to lack of free "
669 "physical registers to rename to.\n");
670 blockThisCycle = true;
671 insts_to_rename.push_front(inst);
672 ++renameFullRegistersEvents;
673
674 break;

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1041 break;
1042 case FloatRegClass:
1043 fpRenameLookups++;
1044 break;
1045 case VecRegClass:
1046 case VecElemClass:
1047 vecRenameLookups++;
1048 break;
1049 case VecPredRegClass:
1050 vecPredRenameLookups++;
1051 break;
1044 case CCRegClass:
1045 case MiscRegClass:
1046 break;
1047
1048 default:
1049 panic("Invalid register class: %d.", src_reg.classValue());
1050 }
1051

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1251
1252 if (fromCommit->commitInfo[tid].usedROB) {
1253 freeEntries[tid].robEntries =
1254 fromCommit->commitInfo[tid].freeROBEntries;
1255 emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB;
1256 }
1257
1258 DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, "
1052 case CCRegClass:
1053 case MiscRegClass:
1054 break;
1055
1056 default:
1057 panic("Invalid register class: %d.", src_reg.classValue());
1058 }
1059

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1259
1260 if (fromCommit->commitInfo[tid].usedROB) {
1261 freeEntries[tid].robEntries =
1262 fromCommit->commitInfo[tid].freeROBEntries;
1263 emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB;
1264 }
1265
1266 DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, "
1259 "Free LQ: %i, Free SQ: %i, FreeRM %i(%i %i %i %i)\n",
1267 "Free LQ: %i, Free SQ: %i, FreeRM %i(%i %i %i %i %i)\n",
1260 tid,
1261 freeEntries[tid].iqEntries,
1262 freeEntries[tid].robEntries,
1263 freeEntries[tid].lqEntries,
1264 freeEntries[tid].sqEntries,
1265 renameMap[tid]->numFreeEntries(),
1266 renameMap[tid]->numFreeIntEntries(),
1267 renameMap[tid]->numFreeFloatEntries(),
1268 renameMap[tid]->numFreeVecEntries(),
1268 tid,
1269 freeEntries[tid].iqEntries,
1270 freeEntries[tid].robEntries,
1271 freeEntries[tid].lqEntries,
1272 freeEntries[tid].sqEntries,
1273 renameMap[tid]->numFreeEntries(),
1274 renameMap[tid]->numFreeIntEntries(),
1275 renameMap[tid]->numFreeFloatEntries(),
1276 renameMap[tid]->numFreeVecEntries(),
1277 renameMap[tid]->numFreePredEntries(),
1269 renameMap[tid]->numFreeCCEntries());
1270
1271 DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n",
1272 tid, instsInProgress[tid]);
1273}
1274
1275template <class Impl>
1276bool

--- 162 unchanged lines hidden --- 		1278 renameMap[tid]->numFreeCCEntries());
1279
1280 DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n",
1281 tid, instsInProgress[tid]);
1282}
1283
1284template <class Impl>
1285bool

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