rename_impl.hh (12105:742d80361989) rename_impl.hh (12106:7784fac1b159)
1/*
1/*
2 * Copyright (c) 2010-2012, 2014-2015 ARM Limited
2 * Copyright (c) 2010-2012, 2014-2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license

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980 // rename histories if they did not have destination registers that were
981 // renamed.
982 while (!historyBuffer[tid].empty() &&
983 hb_it != historyBuffer[tid].end() &&
984 hb_it->instSeqNum <= inst_seq_num) {
985
986 DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i (%s), "
987 "[sn:%lli].\n",
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license

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980 // rename histories if they did not have destination registers that were
981 // renamed.
982 while (!historyBuffer[tid].empty() &&
983 hb_it != historyBuffer[tid].end() &&
984 hb_it->instSeqNum <= inst_seq_num) {
985
986 DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i (%s), "
987 "[sn:%lli].\n",
988 tid, hb_it->prevPhysReg->regIdx,
989 RegClassStrings[hb_it->prevPhysReg->regClass],
988 tid, hb_it->prevPhysReg->index(),
989 hb_it->prevPhysReg->className(),
990 hb_it->instSeqNum);
991
992 // Don't free special phys regs like misc and zero regs, which
993 // can be recognized because the new mapping is the same as
994 // the old one.
995 if (hb_it->newPhysReg != hb_it->prevPhysReg) {
996 freeList->addReg(hb_it->prevPhysReg);
997 }

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1008{
1009 ThreadContext *tc = inst->tcBase();
1010 RenameMap *map = renameMap[tid];
1011 unsigned num_src_regs = inst->numSrcRegs();
1012
1013 // Get the architectual register numbers from the source and
1014 // operands, and redirect them to the right physical register.
1015 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) {
990 hb_it->instSeqNum);
991
992 // Don't free special phys regs like misc and zero regs, which
993 // can be recognized because the new mapping is the same as
994 // the old one.
995 if (hb_it->newPhysReg != hb_it->prevPhysReg) {
996 freeList->addReg(hb_it->prevPhysReg);
997 }

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1008{
1009 ThreadContext *tc = inst->tcBase();
1010 RenameMap *map = renameMap[tid];
1011 unsigned num_src_regs = inst->numSrcRegs();
1012
1013 // Get the architectual register numbers from the source and
1014 // operands, and redirect them to the right physical register.
1015 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) {
1016 RegId src_reg = inst->srcRegIdx(src_idx);
1017 RegIndex flat_src_reg;
1016 const RegId& src_reg = inst->srcRegIdx(src_idx);
1018 PhysRegIdPtr renamed_reg;
1019
1017 PhysRegIdPtr renamed_reg;
1018
1020 switch (src_reg.regClass) {
1019 renamed_reg = map->lookup(tc->flattenRegId(src_reg));
1020 switch (src_reg.classValue()) {
1021 case IntRegClass:
1021 case IntRegClass:
1022 flat_src_reg = tc->flattenIntIndex(src_reg.regIdx);
1023 renamed_reg = map->lookupInt(flat_src_reg);
1024 intRenameLookups++;
1025 break;
1022 intRenameLookups++;
1023 break;
1026
1027 case FloatRegClass:
1024 case FloatRegClass:
1028 flat_src_reg = tc->flattenFloatIndex(src_reg.regIdx);
1029 renamed_reg = map->lookupFloat(flat_src_reg);
1030 fpRenameLookups++;
1031 break;
1025 fpRenameLookups++;
1026 break;
1032
1033 case CCRegClass:
1027 case CCRegClass:
1034 flat_src_reg = tc->flattenCCIndex(src_reg.regIdx);
1035 renamed_reg = map->lookupCC(flat_src_reg);
1036 break;
1037
1038 case MiscRegClass:
1028 case MiscRegClass:
1039 // misc regs don't get flattened
1040 flat_src_reg = src_reg.regIdx;
1041 renamed_reg = map->lookupMisc(flat_src_reg);
1042 break;
1043
1044 default:
1029 break;
1030
1031 default:
1045 panic("Invalid register class: %d.", src_reg.regClass);
1032 panic("Invalid register class: %d.", src_reg.classValue());
1046 }
1047
1048 DPRINTF(Rename, "[tid:%u]: Looking up %s arch reg %i"
1033 }
1034
1035 DPRINTF(Rename, "[tid:%u]: Looking up %s arch reg %i"
1049 " (flattened %i), got phys reg %i (%s)\n", tid,
1050 RegClassStrings[src_reg.regClass], src_reg.regIdx,
1051 flat_src_reg, renamed_reg->regIdx,
1052 RegClassStrings[renamed_reg->regClass]);
1036 ", got phys reg %i (%s)\n", tid,
1037 src_reg.className(), src_reg.index(),
1038 renamed_reg->index(),
1039 renamed_reg->className());
1053
1054 inst->renameSrcReg(src_idx, renamed_reg);
1055
1056 // See if the register is ready or not.
1057 if (scoreboard->getReg(renamed_reg)) {
1058 DPRINTF(Rename, "[tid:%u]: Register %d (flat: %d) (%s)"
1040
1041 inst->renameSrcReg(src_idx, renamed_reg);
1042
1043 // See if the register is ready or not.
1044 if (scoreboard->getReg(renamed_reg)) {
1045 DPRINTF(Rename, "[tid:%u]: Register %d (flat: %d) (%s)"
1059 " is ready.\n", tid, renamed_reg->regIdx,
1060 renamed_reg->flatIdx,
1061 RegClassStrings[renamed_reg->regClass]);
1046 " is ready.\n", tid, renamed_reg->index(),
1047 renamed_reg->flatIndex(),
1048 renamed_reg->className());
1062
1063 inst->markSrcRegReady(src_idx);
1064 } else {
1065 DPRINTF(Rename, "[tid:%u]: Register %d (flat: %d) (%s)"
1049
1050 inst->markSrcRegReady(src_idx);
1051 } else {
1052 DPRINTF(Rename, "[tid:%u]: Register %d (flat: %d) (%s)"
1066 " is not ready.\n", tid, renamed_reg->regIdx,
1067 renamed_reg->flatIdx,
1068 RegClassStrings[renamed_reg->regClass]);
1053 " is not ready.\n", tid, renamed_reg->index(),
1054 renamed_reg->flatIndex(),
1055 renamed_reg->className());
1069 }
1070
1071 ++renameRenameLookups;
1072 }
1073}
1074
1075template <class Impl>
1076inline void
1077DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid)
1078{
1079 ThreadContext *tc = inst->tcBase();
1080 RenameMap *map = renameMap[tid];
1081 unsigned num_dest_regs = inst->numDestRegs();
1082
1083 // Rename the destination registers.
1084 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) {
1056 }
1057
1058 ++renameRenameLookups;
1059 }
1060}
1061
1062template <class Impl>
1063inline void
1064DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid)
1065{
1066 ThreadContext *tc = inst->tcBase();
1067 RenameMap *map = renameMap[tid];
1068 unsigned num_dest_regs = inst->numDestRegs();
1069
1070 // Rename the destination registers.
1071 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) {
1085 RegId dest_reg = inst->destRegIdx(dest_idx);
1086 RegIndex flat_dest_reg;
1072 const RegId& dest_reg = inst->destRegIdx(dest_idx);
1087 typename RenameMap::RenameInfo rename_result;
1088
1073 typename RenameMap::RenameInfo rename_result;
1074
1089 switch (dest_reg.regClass) {
1090 case IntRegClass:
1091 flat_dest_reg = tc->flattenIntIndex(dest_reg.regIdx);
1092 rename_result = map->renameInt(flat_dest_reg);
1093 break;
1075 RegId flat_dest_regid = tc->flattenRegId(dest_reg);
1094
1076
1095 case FloatRegClass:
1096 flat_dest_reg = tc->flattenFloatIndex(dest_reg.regIdx);
1097 rename_result = map->renameFloat(flat_dest_reg);
1098 break;
1077 rename_result = map->rename(flat_dest_regid);
1099
1078
1100 case CCRegClass:
1101 flat_dest_reg = tc->flattenCCIndex(dest_reg.regIdx);
1102 rename_result = map->renameCC(flat_dest_reg);
1103 break;
1079 inst->flattenDestReg(dest_idx, flat_dest_regid);
1104
1080
1105 case MiscRegClass:
1106 // misc regs don't get flattened
1107 flat_dest_reg = dest_reg.regIdx;
1108 rename_result = map->renameMisc(dest_reg.regIdx);
1109 break;
1110
1111 default:
1112 panic("Invalid register class: %d.", dest_reg.regClass);
1113 }
1114
1115 RegId flat_uni_dest_reg(dest_reg.regClass, flat_dest_reg);
1116
1117 inst->flattenDestReg(dest_idx, flat_uni_dest_reg);
1118
1119 // Mark Scoreboard entry as not ready
1120 scoreboard->unsetReg(rename_result.first);
1121
1122 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i (%s) to physical "
1081 // Mark Scoreboard entry as not ready
1082 scoreboard->unsetReg(rename_result.first);
1083
1084 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i (%s) to physical "
1123 "reg %i (%i).\n", tid, dest_reg.regIdx,
1124 RegClassStrings[dest_reg.regClass],
1125 rename_result.first->regIdx,
1126 rename_result.first->flatIdx);
1085 "reg %i (%i).\n", tid, dest_reg.index(),
1086 dest_reg.className(),
1087 rename_result.first->index(),
1088 rename_result.first->flatIndex());
1127
1128 // Record the rename information so that a history can be kept.
1089
1090 // Record the rename information so that a history can be kept.
1129 RenameHistory hb_entry(inst->seqNum, flat_uni_dest_reg,
1091 RenameHistory hb_entry(inst->seqNum, flat_dest_regid,
1130 rename_result.first,
1131 rename_result.second);
1132
1133 historyBuffer[tid].push_front(hb_entry);
1134
1135 DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer "
1136 "(size=%i), [sn:%lli].\n",tid,
1137 historyBuffer[tid].size(),

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1434 for (ThreadID tid = 0; tid < numThreads; tid++) {
1435
1436 buf_it = historyBuffer[tid].begin();
1437
1438 while (buf_it != historyBuffer[tid].end()) {
1439 cprintf("Seq num: %i\nArch reg[%s]: %i New phys reg:"
1440 " %i[%s] Old phys reg: %i[%s]\n",
1441 (*buf_it).instSeqNum,
1092 rename_result.first,
1093 rename_result.second);
1094
1095 historyBuffer[tid].push_front(hb_entry);
1096
1097 DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer "
1098 "(size=%i), [sn:%lli].\n",tid,
1099 historyBuffer[tid].size(),

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1396 for (ThreadID tid = 0; tid < numThreads; tid++) {
1397
1398 buf_it = historyBuffer[tid].begin();
1399
1400 while (buf_it != historyBuffer[tid].end()) {
1401 cprintf("Seq num: %i\nArch reg[%s]: %i New phys reg:"
1402 " %i[%s] Old phys reg: %i[%s]\n",
1403 (*buf_it).instSeqNum,
1442 RegClassStrings[(*buf_it).archReg.regClass],
1443 (*buf_it).archReg.regIdx,
1444 (*buf_it).newPhysReg->regIdx,
1445 RegClassStrings[(*buf_it).newPhysReg->regClass],
1446 (*buf_it).prevPhysReg->regIdx,
1447 RegClassStrings[(*buf_it).prevPhysReg->regClass]);
1404 (*buf_it).archReg.className(),
1405 (*buf_it).archReg.index(),
1406 (*buf_it).newPhysReg->index(),
1407 (*buf_it).newPhysReg->className(),
1408 (*buf_it).prevPhysReg->index(),
1409 (*buf_it).prevPhysReg->className());
1448
1449 buf_it++;
1450 }
1451 }
1452}
1453
1454#endif//__CPU_O3_RENAME_IMPL_HH__
1410
1411 buf_it++;
1412 }
1413 }
1414}
1415
1416#endif//__CPU_O3_RENAME_IMPL_HH__