rename_impl.hh (11650:fe601d7bd955) | rename_impl.hh (12104:edd63f9c6184) |
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1/* 2 * Copyright (c) 2010-2012, 2014-2015 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 997 unchanged lines hidden (view full) --- 1006{ 1007 ThreadContext *tc = inst->tcBase(); 1008 RenameMap *map = renameMap[tid]; 1009 unsigned num_src_regs = inst->numSrcRegs(); 1010 1011 // Get the architectual register numbers from the source and 1012 // operands, and redirect them to the right physical register. 1013 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) { | 1/* 2 * Copyright (c) 2010-2012, 2014-2015 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 997 unchanged lines hidden (view full) --- 1006{ 1007 ThreadContext *tc = inst->tcBase(); 1008 RenameMap *map = renameMap[tid]; 1009 unsigned num_src_regs = inst->numSrcRegs(); 1010 1011 // Get the architectual register numbers from the source and 1012 // operands, and redirect them to the right physical register. 1013 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) { |
1014 RegIndex src_reg = inst->srcRegIdx(src_idx); 1015 RegIndex rel_src_reg; 1016 RegIndex flat_rel_src_reg; | 1014 RegId src_reg = inst->srcRegIdx(src_idx); 1015 RegIndex flat_src_reg; |
1017 PhysRegIndex renamed_reg; 1018 | 1016 PhysRegIndex renamed_reg; 1017 |
1019 switch (regIdxToClass(src_reg, &rel_src_reg)) { | 1018 switch (src_reg.regClass) { |
1020 case IntRegClass: | 1019 case IntRegClass: |
1021 flat_rel_src_reg = tc->flattenIntIndex(rel_src_reg); 1022 renamed_reg = map->lookupInt(flat_rel_src_reg); | 1020 flat_src_reg = tc->flattenIntIndex(src_reg.regIdx); 1021 renamed_reg = map->lookupInt(flat_src_reg); |
1023 intRenameLookups++; 1024 break; 1025 1026 case FloatRegClass: | 1022 intRenameLookups++; 1023 break; 1024 1025 case FloatRegClass: |
1027 flat_rel_src_reg = tc->flattenFloatIndex(rel_src_reg); 1028 renamed_reg = map->lookupFloat(flat_rel_src_reg); | 1026 flat_src_reg = tc->flattenFloatIndex(src_reg.regIdx); 1027 renamed_reg = map->lookupFloat(flat_src_reg); |
1029 fpRenameLookups++; 1030 break; 1031 1032 case CCRegClass: | 1028 fpRenameLookups++; 1029 break; 1030 1031 case CCRegClass: |
1033 flat_rel_src_reg = tc->flattenCCIndex(rel_src_reg); 1034 renamed_reg = map->lookupCC(flat_rel_src_reg); | 1032 flat_src_reg = tc->flattenCCIndex(src_reg.regIdx); 1033 renamed_reg = map->lookupCC(flat_src_reg); |
1035 break; 1036 1037 case MiscRegClass: 1038 // misc regs don't get flattened | 1034 break; 1035 1036 case MiscRegClass: 1037 // misc regs don't get flattened |
1039 flat_rel_src_reg = rel_src_reg; 1040 renamed_reg = map->lookupMisc(flat_rel_src_reg); | 1038 flat_src_reg = src_reg.regIdx; 1039 renamed_reg = map->lookupMisc(flat_src_reg); |
1041 break; 1042 1043 default: | 1040 break; 1041 1042 default: |
1044 panic("Reg index is out of bound: %d.", src_reg); | 1043 panic("Invalid register class: %d.", src_reg.regClass); |
1045 } 1046 1047 DPRINTF(Rename, "[tid:%u]: Looking up %s arch reg %i (flattened %i), " | 1044 } 1045 1046 DPRINTF(Rename, "[tid:%u]: Looking up %s arch reg %i (flattened %i), " |
1048 "got phys reg %i\n", tid, RegClassStrings[regIdxToClass(src_reg)], 1049 (int)src_reg, (int)flat_rel_src_reg, (int)renamed_reg); | 1047 "got phys reg %i\n", tid, RegClassStrings[src_reg.regClass], 1048 (int)src_reg.regIdx, (int)flat_src_reg, (int)renamed_reg); |
1050 1051 inst->renameSrcReg(src_idx, renamed_reg); 1052 1053 // See if the register is ready or not. 1054 if (scoreboard->getReg(renamed_reg)) { 1055 DPRINTF(Rename, "[tid:%u]: Register %d is ready.\n", 1056 tid, renamed_reg); 1057 --- 12 unchanged lines hidden (view full) --- 1070DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid) 1071{ 1072 ThreadContext *tc = inst->tcBase(); 1073 RenameMap *map = renameMap[tid]; 1074 unsigned num_dest_regs = inst->numDestRegs(); 1075 1076 // Rename the destination registers. 1077 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) { | 1049 1050 inst->renameSrcReg(src_idx, renamed_reg); 1051 1052 // See if the register is ready or not. 1053 if (scoreboard->getReg(renamed_reg)) { 1054 DPRINTF(Rename, "[tid:%u]: Register %d is ready.\n", 1055 tid, renamed_reg); 1056 --- 12 unchanged lines hidden (view full) --- 1069DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid) 1070{ 1071 ThreadContext *tc = inst->tcBase(); 1072 RenameMap *map = renameMap[tid]; 1073 unsigned num_dest_regs = inst->numDestRegs(); 1074 1075 // Rename the destination registers. 1076 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) { |
1078 RegIndex dest_reg = inst->destRegIdx(dest_idx); 1079 RegIndex rel_dest_reg; 1080 RegIndex flat_rel_dest_reg; 1081 RegIndex flat_uni_dest_reg; | 1077 RegId dest_reg = inst->destRegIdx(dest_idx); 1078 RegIndex flat_dest_reg; |
1082 typename RenameMap::RenameInfo rename_result; 1083 | 1079 typename RenameMap::RenameInfo rename_result; 1080 |
1084 switch (regIdxToClass(dest_reg, &rel_dest_reg)) { | 1081 switch (dest_reg.regClass) { |
1085 case IntRegClass: | 1082 case IntRegClass: |
1086 flat_rel_dest_reg = tc->flattenIntIndex(rel_dest_reg); 1087 rename_result = map->renameInt(flat_rel_dest_reg); 1088 flat_uni_dest_reg = flat_rel_dest_reg; // 1:1 mapping | 1083 flat_dest_reg = tc->flattenIntIndex(dest_reg.regIdx); 1084 rename_result = map->renameInt(flat_dest_reg); |
1089 break; 1090 1091 case FloatRegClass: | 1085 break; 1086 1087 case FloatRegClass: |
1092 flat_rel_dest_reg = tc->flattenFloatIndex(rel_dest_reg); 1093 rename_result = map->renameFloat(flat_rel_dest_reg); 1094 flat_uni_dest_reg = flat_rel_dest_reg + TheISA::FP_Reg_Base; | 1088 flat_dest_reg = tc->flattenFloatIndex(dest_reg.regIdx); 1089 rename_result = map->renameFloat(flat_dest_reg); |
1095 break; 1096 1097 case CCRegClass: | 1090 break; 1091 1092 case CCRegClass: |
1098 flat_rel_dest_reg = tc->flattenCCIndex(rel_dest_reg); 1099 rename_result = map->renameCC(flat_rel_dest_reg); 1100 flat_uni_dest_reg = flat_rel_dest_reg + TheISA::CC_Reg_Base; | 1093 flat_dest_reg = tc->flattenCCIndex(dest_reg.regIdx); 1094 rename_result = map->renameCC(flat_dest_reg); |
1101 break; 1102 1103 case MiscRegClass: 1104 // misc regs don't get flattened | 1095 break; 1096 1097 case MiscRegClass: 1098 // misc regs don't get flattened |
1105 flat_rel_dest_reg = rel_dest_reg; 1106 rename_result = map->renameMisc(flat_rel_dest_reg); 1107 flat_uni_dest_reg = flat_rel_dest_reg + TheISA::Misc_Reg_Base; | 1099 flat_dest_reg = dest_reg.regIdx; 1100 rename_result = map->renameMisc(dest_reg.regIdx); |
1108 break; 1109 1110 default: | 1101 break; 1102 1103 default: |
1111 panic("Reg index is out of bound: %d.", dest_reg); | 1104 panic("Invalid register class: %d.", dest_reg.regClass); |
1112 } 1113 | 1105 } 1106 |
1107 RegId flat_uni_dest_reg(dest_reg.regClass, flat_dest_reg); 1108 |
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1114 inst->flattenDestReg(dest_idx, flat_uni_dest_reg); 1115 1116 // Mark Scoreboard entry as not ready 1117 scoreboard->unsetReg(rename_result.first); 1118 1119 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical " | 1109 inst->flattenDestReg(dest_idx, flat_uni_dest_reg); 1110 1111 // Mark Scoreboard entry as not ready 1112 scoreboard->unsetReg(rename_result.first); 1113 1114 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical " |
1120 "reg %i.\n", tid, (int)flat_rel_dest_reg, | 1115 "reg %i.\n", tid, (int)flat_dest_reg, |
1121 (int)rename_result.first); 1122 1123 // Record the rename information so that a history can be kept. 1124 RenameHistory hb_entry(inst->seqNum, flat_uni_dest_reg, 1125 rename_result.first, 1126 rename_result.second); 1127 1128 historyBuffer[tid].push_front(hb_entry); --- 297 unchanged lines hidden (view full) --- 1426{ 1427 typename std::list<RenameHistory>::iterator buf_it; 1428 1429 for (ThreadID tid = 0; tid < numThreads; tid++) { 1430 1431 buf_it = historyBuffer[tid].begin(); 1432 1433 while (buf_it != historyBuffer[tid].end()) { | 1116 (int)rename_result.first); 1117 1118 // Record the rename information so that a history can be kept. 1119 RenameHistory hb_entry(inst->seqNum, flat_uni_dest_reg, 1120 rename_result.first, 1121 rename_result.second); 1122 1123 historyBuffer[tid].push_front(hb_entry); --- 297 unchanged lines hidden (view full) --- 1421{ 1422 typename std::list<RenameHistory>::iterator buf_it; 1423 1424 for (ThreadID tid = 0; tid < numThreads; tid++) { 1425 1426 buf_it = historyBuffer[tid].begin(); 1427 1428 while (buf_it != historyBuffer[tid].end()) { |
1434 cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys " 1435 "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg, | 1429 cprintf("Seq num: %i\nArch reg[%s]: %i New phys reg: %i Old phys " 1430 "reg: %i\n", (*buf_it).instSeqNum, 1431 RegClassStrings[(*buf_it).archReg.regClass], 1432 (*buf_it).archReg.regIdx, |
1436 (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg); 1437 1438 buf_it++; 1439 } 1440 } 1441} 1442 1443#endif//__CPU_O3_RENAME_IMPL_HH__ | 1433 (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg); 1434 1435 buf_it++; 1436 } 1437 } 1438} 1439 1440#endif//__CPU_O3_RENAME_IMPL_HH__ |