rename_impl.hh (10934:5af8f40d8f2c) rename_impl.hh (10935:acd48ddd725f)
1/*
2 * Copyright (c) 2010-2012, 2014-2015 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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64 : cpu(_cpu),
65 iewToRenameDelay(params->iewToRenameDelay),
66 decodeToRenameDelay(params->decodeToRenameDelay),
67 commitToRenameDelay(params->commitToRenameDelay),
68 renameWidth(params->renameWidth),
69 commitWidth(params->commitWidth),
70 numThreads(params->numThreads),
71 maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs
1/*
2 * Copyright (c) 2010-2012, 2014-2015 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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64 : cpu(_cpu),
65 iewToRenameDelay(params->iewToRenameDelay),
66 decodeToRenameDelay(params->decodeToRenameDelay),
67 commitToRenameDelay(params->commitToRenameDelay),
68 renameWidth(params->renameWidth),
69 commitWidth(params->commitWidth),
70 numThreads(params->numThreads),
71 maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs
72 + params->numPhysCCRegs + params->numPhysVectorRegs)
72 + params->numPhysCCRegs)
73{
74 if (renameWidth > Impl::MaxWidth)
75 fatal("renameWidth (%d) is larger than compiled limit (%d),\n"
76 "\tincrease MaxWidth in src/cpu/o3/impl.hh\n",
77 renameWidth, static_cast<int>(Impl::MaxWidth));
78
79 // @todo: Make into a parameter.
80 skidBufferMax = (decodeToRenameDelay + 1) * params->decodeWidth;

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630
631 DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with "
632 "PC %s.\n", tid, inst->seqNum, inst->pcState());
633
634 // Check here to make sure there are enough destination registers
635 // to rename to. Otherwise block.
636 if (!renameMap[tid]->canRename(inst->numIntDestRegs(),
637 inst->numFPDestRegs(),
73{
74 if (renameWidth > Impl::MaxWidth)
75 fatal("renameWidth (%d) is larger than compiled limit (%d),\n"
76 "\tincrease MaxWidth in src/cpu/o3/impl.hh\n",
77 renameWidth, static_cast<int>(Impl::MaxWidth));
78
79 // @todo: Make into a parameter.
80 skidBufferMax = (decodeToRenameDelay + 1) * params->decodeWidth;

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630
631 DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with "
632 "PC %s.\n", tid, inst->seqNum, inst->pcState());
633
634 // Check here to make sure there are enough destination registers
635 // to rename to. Otherwise block.
636 if (!renameMap[tid]->canRename(inst->numIntDestRegs(),
637 inst->numFPDestRegs(),
638 inst->numCCDestRegs(),
639 inst->numVectorDestRegs())) {
638 inst->numCCDestRegs())) {
640 DPRINTF(Rename, "Blocking due to lack of free "
641 "physical registers to rename to.\n");
642 blockThisCycle = true;
643 insts_to_rename.push_front(inst);
644 ++renameFullRegistersEvents;
645
646 break;
647 }

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1012 fpRenameLookups++;
1013 break;
1014
1015 case CCRegClass:
1016 flat_rel_src_reg = tc->flattenCCIndex(rel_src_reg);
1017 renamed_reg = map->lookupCC(flat_rel_src_reg);
1018 break;
1019
639 DPRINTF(Rename, "Blocking due to lack of free "
640 "physical registers to rename to.\n");
641 blockThisCycle = true;
642 insts_to_rename.push_front(inst);
643 ++renameFullRegistersEvents;
644
645 break;
646 }

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1011 fpRenameLookups++;
1012 break;
1013
1014 case CCRegClass:
1015 flat_rel_src_reg = tc->flattenCCIndex(rel_src_reg);
1016 renamed_reg = map->lookupCC(flat_rel_src_reg);
1017 break;
1018
1020 case VectorRegClass:
1021 flat_rel_src_reg = tc->flattenVectorIndex(rel_src_reg);
1022 renamed_reg = map->lookupVector(flat_rel_src_reg);
1023 break;
1024
1025 case MiscRegClass:
1026 // misc regs don't get flattened
1027 flat_rel_src_reg = rel_src_reg;
1028 renamed_reg = map->lookupMisc(flat_rel_src_reg);
1029 break;
1030
1031 default:
1032 panic("Reg index is out of bound: %d.", src_reg);

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1083 break;
1084
1085 case CCRegClass:
1086 flat_rel_dest_reg = tc->flattenCCIndex(rel_dest_reg);
1087 rename_result = map->renameCC(flat_rel_dest_reg);
1088 flat_uni_dest_reg = flat_rel_dest_reg + TheISA::CC_Reg_Base;
1089 break;
1090
1019 case MiscRegClass:
1020 // misc regs don't get flattened
1021 flat_rel_src_reg = rel_src_reg;
1022 renamed_reg = map->lookupMisc(flat_rel_src_reg);
1023 break;
1024
1025 default:
1026 panic("Reg index is out of bound: %d.", src_reg);

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1077 break;
1078
1079 case CCRegClass:
1080 flat_rel_dest_reg = tc->flattenCCIndex(rel_dest_reg);
1081 rename_result = map->renameCC(flat_rel_dest_reg);
1082 flat_uni_dest_reg = flat_rel_dest_reg + TheISA::CC_Reg_Base;
1083 break;
1084
1091 case VectorRegClass:
1092 flat_rel_dest_reg = tc->flattenVectorIndex(rel_dest_reg);
1093 rename_result = map->renameVector(flat_rel_dest_reg);
1094 flat_uni_dest_reg = flat_rel_dest_reg + TheISA::Vector_Reg_Base;
1095 break;
1096
1097 case MiscRegClass:
1098 // misc regs don't get flattened
1099 flat_rel_dest_reg = rel_dest_reg;
1100 rename_result = map->renameMisc(flat_rel_dest_reg);
1101 flat_uni_dest_reg = flat_rel_dest_reg + TheISA::Misc_Reg_Base;
1102 break;
1103
1104 default:

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1163 return num_free;
1164}
1165
1166template <class Impl>
1167inline int
1168DefaultRename<Impl>::calcFreeLQEntries(ThreadID tid)
1169{
1170 int num_free = freeEntries[tid].lqEntries -
1085 case MiscRegClass:
1086 // misc regs don't get flattened
1087 flat_rel_dest_reg = rel_dest_reg;
1088 rename_result = map->renameMisc(flat_rel_dest_reg);
1089 flat_uni_dest_reg = flat_rel_dest_reg + TheISA::Misc_Reg_Base;
1090 break;
1091
1092 default:

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1151 return num_free;
1152}
1153
1154template <class Impl>
1155inline int
1156DefaultRename<Impl>::calcFreeLQEntries(ThreadID tid)
1157{
1158 int num_free = freeEntries[tid].lqEntries -
1171 (loadsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLQ);
1159 (loadsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLQ);
1172 DPRINTF(Rename, "calcFreeLQEntries: free lqEntries: %d, loadsInProgress: %d, "
1173 "loads dispatchedToLQ: %d\n", freeEntries[tid].lqEntries,
1174 loadsInProgress[tid], fromIEW->iewInfo[tid].dispatchedToLQ);
1175 return num_free;
1176}
1177
1178template <class Impl>
1179inline int
1180DefaultRename<Impl>::calcFreeSQEntries(ThreadID tid)
1181{
1182 int num_free = freeEntries[tid].sqEntries -
1160 DPRINTF(Rename, "calcFreeLQEntries: free lqEntries: %d, loadsInProgress: %d, "
1161 "loads dispatchedToLQ: %d\n", freeEntries[tid].lqEntries,
1162 loadsInProgress[tid], fromIEW->iewInfo[tid].dispatchedToLQ);
1163 return num_free;
1164}
1165
1166template <class Impl>
1167inline int
1168DefaultRename<Impl>::calcFreeSQEntries(ThreadID tid)
1169{
1170 int num_free = freeEntries[tid].sqEntries -
1183 (storesInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToSQ);
1171 (storesInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToSQ);
1184 DPRINTF(Rename, "calcFreeSQEntries: free sqEntries: %d, storesInProgress: %d, "
1185 "stores dispatchedToSQ: %d\n", freeEntries[tid].sqEntries,
1186 storesInProgress[tid], fromIEW->iewInfo[tid].dispatchedToSQ);
1187 return num_free;
1188}
1189
1190template <class Impl>
1191unsigned

--- 246 unchanged lines hidden --- 		1172 DPRINTF(Rename, "calcFreeSQEntries: free sqEntries: %d, storesInProgress: %d, "
1173 "stores dispatchedToSQ: %d\n", freeEntries[tid].sqEntries,
1174 storesInProgress[tid], fromIEW->iewInfo[tid].dispatchedToSQ);
1175 return num_free;
1176}
1177
1178template <class Impl>
1179unsigned

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