1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 * Korey Sewell
43 */
44
45#ifndef __CPU_O3_RENAME_IMPL_HH__
46#define __CPU_O3_RENAME_IMPL_HH__
47
48#include <list>
49
50#include "arch/isa_traits.hh"
51#include "arch/registers.hh"
52#include "config/the_isa.hh"
53#include "cpu/o3/rename.hh"
54#include "cpu/reg_class.hh"
55#include "debug/Activity.hh"
56#include "debug/Rename.hh"
57#include "debug/O3PipeView.hh"
58#include "params/DerivO3CPU.hh"
59
60using namespace std;
61
62template <class Impl>
63DefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params)
64 : cpu(_cpu),
65 iewToRenameDelay(params->iewToRenameDelay),
66 decodeToRenameDelay(params->decodeToRenameDelay),
67 commitToRenameDelay(params->commitToRenameDelay),
68 renameWidth(params->renameWidth),
69 commitWidth(params->commitWidth),
70 numThreads(params->numThreads),
71 maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs
72 + params->numPhysCCRegs)
73{
74 if (renameWidth > Impl::MaxWidth)
75 fatal("renameWidth (%d) is larger than compiled limit (%d),\n"
76 "\tincrease MaxWidth in src/cpu/o3/impl.hh\n",
77 renameWidth, static_cast<int>(Impl::MaxWidth));
78
79 // @todo: Make into a parameter.
80 skidBufferMax = (2 * (decodeToRenameDelay * params->decodeWidth)) + renameWidth;
81}
82
83template <class Impl>
84std::string
85DefaultRename<Impl>::name() const
86{
87 return cpu->name() + ".rename";
88}
89
90template <class Impl>
91void
92DefaultRename<Impl>::regStats()
93{
94 renameSquashCycles
95 .name(name() + ".SquashCycles")
96 .desc("Number of cycles rename is squashing")
97 .prereq(renameSquashCycles);
98 renameIdleCycles
99 .name(name() + ".IdleCycles")
100 .desc("Number of cycles rename is idle")
101 .prereq(renameIdleCycles);
102 renameBlockCycles
103 .name(name() + ".BlockCycles")
104 .desc("Number of cycles rename is blocking")
105 .prereq(renameBlockCycles);
106 renameSerializeStallCycles
107 .name(name() + ".serializeStallCycles")
108 .desc("count of cycles rename stalled for serializing inst")
109 .flags(Stats::total);
110 renameRunCycles
111 .name(name() + ".RunCycles")
112 .desc("Number of cycles rename is running")
113 .prereq(renameIdleCycles);
114 renameUnblockCycles
115 .name(name() + ".UnblockCycles")
116 .desc("Number of cycles rename is unblocking")
117 .prereq(renameUnblockCycles);
118 renameRenamedInsts
119 .name(name() + ".RenamedInsts")
120 .desc("Number of instructions processed by rename")
121 .prereq(renameRenamedInsts);
122 renameSquashedInsts
123 .name(name() + ".SquashedInsts")
124 .desc("Number of squashed instructions processed by rename")
125 .prereq(renameSquashedInsts);
126 renameROBFullEvents
127 .name(name() + ".ROBFullEvents")
128 .desc("Number of times rename has blocked due to ROB full")
129 .prereq(renameROBFullEvents);
130 renameIQFullEvents
131 .name(name() + ".IQFullEvents")
132 .desc("Number of times rename has blocked due to IQ full")
133 .prereq(renameIQFullEvents);
|
134 renameLSQFullEvents
135 .name(name() + ".LSQFullEvents")
136 .desc("Number of times rename has blocked due to LSQ full")
137 .prereq(renameLSQFullEvents);
|
134 renameLQFullEvents
135 .name(name() + ".LQFullEvents")
136 .desc("Number of times rename has blocked due to LQ full")
137 .prereq(renameLQFullEvents);
138 renameSQFullEvents
139 .name(name() + ".SQFullEvents")
140 .desc("Number of times rename has blocked due to SQ full")
141 .prereq(renameSQFullEvents); |
142 renameFullRegistersEvents
143 .name(name() + ".FullRegisterEvents")
144 .desc("Number of times there has been no free registers")
145 .prereq(renameFullRegistersEvents);
146 renameRenamedOperands
147 .name(name() + ".RenamedOperands")
148 .desc("Number of destination operands rename has renamed")
149 .prereq(renameRenamedOperands);
150 renameRenameLookups
151 .name(name() + ".RenameLookups")
152 .desc("Number of register rename lookups that rename has made")
153 .prereq(renameRenameLookups);
154 renameCommittedMaps
155 .name(name() + ".CommittedMaps")
156 .desc("Number of HB maps that are committed")
157 .prereq(renameCommittedMaps);
158 renameUndoneMaps
159 .name(name() + ".UndoneMaps")
160 .desc("Number of HB maps that are undone due to squashing")
161 .prereq(renameUndoneMaps);
162 renamedSerializing
163 .name(name() + ".serializingInsts")
164 .desc("count of serializing insts renamed")
165 .flags(Stats::total)
166 ;
167 renamedTempSerializing
168 .name(name() + ".tempSerializingInsts")
169 .desc("count of temporary serializing insts renamed")
170 .flags(Stats::total)
171 ;
172 renameSkidInsts
173 .name(name() + ".skidInsts")
174 .desc("count of insts added to the skid buffer")
175 .flags(Stats::total)
176 ;
177 intRenameLookups
178 .name(name() + ".int_rename_lookups")
179 .desc("Number of integer rename lookups")
180 .prereq(intRenameLookups);
181 fpRenameLookups
182 .name(name() + ".fp_rename_lookups")
183 .desc("Number of floating rename lookups")
184 .prereq(fpRenameLookups);
185}
186
187template <class Impl>
188void
189DefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
190{
191 timeBuffer = tb_ptr;
192
193 // Setup wire to read information from time buffer, from IEW stage.
194 fromIEW = timeBuffer->getWire(-iewToRenameDelay);
195
196 // Setup wire to read infromation from time buffer, from commit stage.
197 fromCommit = timeBuffer->getWire(-commitToRenameDelay);
198
199 // Setup wire to write information to previous stages.
200 toDecode = timeBuffer->getWire(0);
201}
202
203template <class Impl>
204void
205DefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
206{
207 renameQueue = rq_ptr;
208
209 // Setup wire to write information to future stages.
210 toIEW = renameQueue->getWire(0);
211}
212
213template <class Impl>
214void
215DefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
216{
217 decodeQueue = dq_ptr;
218
219 // Setup wire to get information from decode.
220 fromDecode = decodeQueue->getWire(-decodeToRenameDelay);
221}
222
223template <class Impl>
224void
225DefaultRename<Impl>::startupStage()
226{
227 resetStage();
228}
229
230template <class Impl>
231void
232DefaultRename<Impl>::resetStage()
233{
234 _status = Inactive;
235
236 resumeSerialize = false;
237 resumeUnblocking = false;
238
239 // Grab the number of free entries directly from the stages.
240 for (ThreadID tid = 0; tid < numThreads; tid++) {
241 renameStatus[tid] = Idle;
242
243 freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid);
|
240 freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid);
|
244 freeEntries[tid].lqEntries = iew_ptr->ldstQueue.numFreeLoadEntries(tid);
245 freeEntries[tid].sqEntries = iew_ptr->ldstQueue.numFreeStoreEntries(tid); |
246 freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid);
247 emptyROB[tid] = true;
248
249 stalls[tid].iew = false;
250 stalls[tid].commit = false;
251 serializeInst[tid] = NULL;
252
253 instsInProgress[tid] = 0;
|
254 loadsInProgress[tid] = 0;
255 storesInProgress[tid] = 0; |
256
257 serializeOnNextInst[tid] = false;
258 }
259}
260
261template<class Impl>
262void
263DefaultRename<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
264{
265 activeThreads = at_ptr;
266}
267
268
269template <class Impl>
270void
271DefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[])
272{
273 for (ThreadID tid = 0; tid < numThreads; tid++)
274 renameMap[tid] = &rm_ptr[tid];
275}
276
277template <class Impl>
278void
279DefaultRename<Impl>::setFreeList(FreeList *fl_ptr)
280{
281 freeList = fl_ptr;
282}
283
284template<class Impl>
285void
286DefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard)
287{
288 scoreboard = _scoreboard;
289}
290
291template <class Impl>
292bool
293DefaultRename<Impl>::isDrained() const
294{
295 for (ThreadID tid = 0; tid < numThreads; tid++) {
296 if (instsInProgress[tid] != 0 ||
297 !historyBuffer[tid].empty() ||
298 !skidBuffer[tid].empty() ||
299 !insts[tid].empty())
300 return false;
301 }
302 return true;
303}
304
305template <class Impl>
306void
307DefaultRename<Impl>::takeOverFrom()
308{
309 resetStage();
310}
311
312template <class Impl>
313void
314DefaultRename<Impl>::drainSanityCheck() const
315{
316 for (ThreadID tid = 0; tid < numThreads; tid++) {
317 assert(historyBuffer[tid].empty());
318 assert(insts[tid].empty());
319 assert(skidBuffer[tid].empty());
320 assert(instsInProgress[tid] == 0);
321 }
322}
323
324template <class Impl>
325void
326DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, ThreadID tid)
327{
328 DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid);
329
330 // Clear the stall signal if rename was blocked or unblocking before.
331 // If it still needs to block, the blocking should happen the next
332 // cycle and there should be space to hold everything due to the squash.
333 if (renameStatus[tid] == Blocked ||
334 renameStatus[tid] == Unblocking) {
335 toDecode->renameUnblock[tid] = 1;
336
337 resumeSerialize = false;
338 serializeInst[tid] = NULL;
339 } else if (renameStatus[tid] == SerializeStall) {
340 if (serializeInst[tid]->seqNum <= squash_seq_num) {
341 DPRINTF(Rename, "Rename will resume serializing after squash\n");
342 resumeSerialize = true;
343 assert(serializeInst[tid]);
344 } else {
345 resumeSerialize = false;
346 toDecode->renameUnblock[tid] = 1;
347
348 serializeInst[tid] = NULL;
349 }
350 }
351
352 // Set the status to Squashing.
353 renameStatus[tid] = Squashing;
354
355 // Squash any instructions from decode.
356 for (int i=0; i<fromDecode->size; i++) {
357 if (fromDecode->insts[i]->threadNumber == tid &&
358 fromDecode->insts[i]->seqNum > squash_seq_num) {
359 fromDecode->insts[i]->setSquashed();
360 wroteToTimeBuffer = true;
361 }
362
363 }
364
365 // Clear the instruction list and skid buffer in case they have any
366 // insts in them.
367 insts[tid].clear();
368
369 // Clear the skid buffer in case it has any data in it.
370 skidBuffer[tid].clear();
371
372 doSquash(squash_seq_num, tid);
373}
374
375template <class Impl>
376void
377DefaultRename<Impl>::tick()
378{
379 wroteToTimeBuffer = false;
380
381 blockThisCycle = false;
382
383 bool status_change = false;
384
385 toIEWIndex = 0;
386
387 sortInsts();
388
389 list<ThreadID>::iterator threads = activeThreads->begin();
390 list<ThreadID>::iterator end = activeThreads->end();
391
392 // Check stall and squash signals.
393 while (threads != end) {
394 ThreadID tid = *threads++;
395
396 DPRINTF(Rename, "Processing [tid:%i]\n", tid);
397
398 status_change = checkSignalsAndUpdate(tid) || status_change;
399
400 rename(status_change, tid);
401 }
402
403 if (status_change) {
404 updateStatus();
405 }
406
407 if (wroteToTimeBuffer) {
408 DPRINTF(Activity, "Activity this cycle.\n");
409 cpu->activityThisCycle();
410 }
411
412 threads = activeThreads->begin();
413
414 while (threads != end) {
415 ThreadID tid = *threads++;
416
417 // If we committed this cycle then doneSeqNum will be > 0
418 if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
419 !fromCommit->commitInfo[tid].squash &&
420 renameStatus[tid] != Squashing) {
421
422 removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum,
423 tid);
424 }
425 }
426
427 // @todo: make into updateProgress function
428 for (ThreadID tid = 0; tid < numThreads; tid++) {
429 instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched;
|
423
|
430 loadsInProgress[tid] -= fromIEW->iewInfo[tid].dispatchedToLQ;
431 storesInProgress[tid] -= fromIEW->iewInfo[tid].dispatchedToSQ;
432 assert(loadsInProgress[tid] >= 0);
433 assert(storesInProgress[tid] >= 0); |
434 assert(instsInProgress[tid] >=0);
435 }
436
437}
438
439template<class Impl>
440void
441DefaultRename<Impl>::rename(bool &status_change, ThreadID tid)
442{
443 // If status is Running or idle,
444 // call renameInsts()
445 // If status is Unblocking,
446 // buffer any instructions coming from decode
447 // continue trying to empty skid buffer
448 // check if stall conditions have passed
449
450 if (renameStatus[tid] == Blocked) {
451 ++renameBlockCycles;
452 } else if (renameStatus[tid] == Squashing) {
453 ++renameSquashCycles;
454 } else if (renameStatus[tid] == SerializeStall) {
455 ++renameSerializeStallCycles;
456 // If we are currently in SerializeStall and resumeSerialize
457 // was set, then that means that we are resuming serializing
458 // this cycle. Tell the previous stages to block.
459 if (resumeSerialize) {
460 resumeSerialize = false;
461 block(tid);
462 toDecode->renameUnblock[tid] = false;
463 }
464 } else if (renameStatus[tid] == Unblocking) {
465 if (resumeUnblocking) {
466 block(tid);
467 resumeUnblocking = false;
468 toDecode->renameUnblock[tid] = false;
469 }
470 }
471
472 if (renameStatus[tid] == Running ||
473 renameStatus[tid] == Idle) {
474 DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run "
475 "stage.\n", tid);
476
477 renameInsts(tid);
478 } else if (renameStatus[tid] == Unblocking) {
479 renameInsts(tid);
480
481 if (validInsts()) {
482 // Add the current inputs to the skid buffer so they can be
483 // reprocessed when this stage unblocks.
484 skidInsert(tid);
485 }
486
487 // If we switched over to blocking, then there's a potential for
488 // an overall status change.
489 status_change = unblock(tid) || status_change || blockThisCycle;
490 }
491}
492
493template <class Impl>
494void
495DefaultRename<Impl>::renameInsts(ThreadID tid)
496{
497 // Instructions can be either in the skid buffer or the queue of
498 // instructions coming from decode, depending on the status.
499 int insts_available = renameStatus[tid] == Unblocking ?
500 skidBuffer[tid].size() : insts[tid].size();
501
502 // Check the decode queue to see if instructions are available.
503 // If there are no available instructions to rename, then do nothing.
504 if (insts_available == 0) {
505 DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n",
506 tid);
507 // Should I change status to idle?
508 ++renameIdleCycles;
509 return;
510 } else if (renameStatus[tid] == Unblocking) {
511 ++renameUnblockCycles;
512 } else if (renameStatus[tid] == Running) {
513 ++renameRunCycles;
514 }
515
516 DynInstPtr inst;
517
518 // Will have to do a different calculation for the number of free
519 // entries.
520 int free_rob_entries = calcFreeROBEntries(tid);
521 int free_iq_entries = calcFreeIQEntries(tid);
|
512 int free_lsq_entries = calcFreeLSQEntries(tid);
|
522 int min_free_entries = free_rob_entries;
523
524 FullSource source = ROB;
525
526 if (free_iq_entries < min_free_entries) {
527 min_free_entries = free_iq_entries;
528 source = IQ;
529 }
530
|
522 if (free_lsq_entries < min_free_entries) {
523 min_free_entries = free_lsq_entries;
524 source = LSQ;
525 }
526
|
531 // Check if there's any space left.
532 if (min_free_entries <= 0) {
|
529 DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ "
|
| 533 DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/ " |
534 "entries.\n"
535 "ROB has %i free entries.\n"
|
532 "IQ has %i free entries.\n"
533 "LSQ has %i free entries.\n",
|
| 536 "IQ has %i free entries.\n", |
537 tid,
538 free_rob_entries,
|
536 free_iq_entries,
537 free_lsq_entries);
|
| 539 free_iq_entries); |
540
541 blockThisCycle = true;
542
543 block(tid);
544
545 incrFullStat(source);
546
547 return;
548 } else if (min_free_entries < insts_available) {
549 DPRINTF(Rename, "[tid:%u]: Will have to block this cycle."
550 "%i insts available, but only %i insts can be "
551 "renamed due to ROB/IQ/LSQ limits.\n",
552 tid, insts_available, min_free_entries);
553
554 insts_available = min_free_entries;
555
556 blockThisCycle = true;
557
558 incrFullStat(source);
559 }
560
561 InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ?
562 skidBuffer[tid] : insts[tid];
563
564 DPRINTF(Rename, "[tid:%u]: %i available instructions to "
565 "send iew.\n", tid, insts_available);
566
567 DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts "
568 "dispatched to IQ last cycle.\n",
569 tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched);
570
571 // Handle serializing the next instruction if necessary.
572 if (serializeOnNextInst[tid]) {
573 if (emptyROB[tid] && instsInProgress[tid] == 0) {
574 // ROB already empty; no need to serialize.
575 serializeOnNextInst[tid] = false;
576 } else if (!insts_to_rename.empty()) {
577 insts_to_rename.front()->setSerializeBefore();
578 }
579 }
580
581 int renamed_insts = 0;
582
583 while (insts_available > 0 && toIEWIndex < renameWidth) {
584 DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid);
585
586 assert(!insts_to_rename.empty());
587
588 inst = insts_to_rename.front();
589
|
590 //For all kind of instructions, check ROB and IQ first
591 //For load instruction, check LQ size and take into account the inflight loads
592 //For store instruction, check SQ size and take into account the inflight stores
593
594 if (inst->isLoad()) {
595 if(calcFreeLQEntries(tid) <= 0) {
596 DPRINTF(Rename, "[tid:%u]: Cannot rename due to no free LQ\n");
597 source = LQ;
598 incrFullStat(source);
599 break;
600 }
601 }
602
603 if (inst->isStore()) {
604 if(calcFreeSQEntries(tid) <= 0) {
605 DPRINTF(Rename, "[tid:%u]: Cannot rename due to no free SQ\n");
606 source = SQ;
607 incrFullStat(source);
608 break;
609 }
610 }
611 |
612 insts_to_rename.pop_front();
613
614 if (renameStatus[tid] == Unblocking) {
615 DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%s from rename "
616 "skidBuffer\n", tid, inst->seqNum, inst->pcState());
617 }
618
619 if (inst->isSquashed()) {
620 DPRINTF(Rename, "[tid:%u]: instruction %i with PC %s is "
621 "squashed, skipping.\n", tid, inst->seqNum,
622 inst->pcState());
623
624 ++renameSquashedInsts;
625
626 // Decrement how many instructions are available.
627 --insts_available;
628
629 continue;
630 }
631
632 DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with "
633 "PC %s.\n", tid, inst->seqNum, inst->pcState());
634
635 // Check here to make sure there are enough destination registers
636 // to rename to. Otherwise block.
637 if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) {
638 DPRINTF(Rename, "Blocking due to lack of free "
639 "physical registers to rename to.\n");
640 blockThisCycle = true;
641 insts_to_rename.push_front(inst);
642 ++renameFullRegistersEvents;
643
644 break;
645 }
646
647 // Handle serializeAfter/serializeBefore instructions.
648 // serializeAfter marks the next instruction as serializeBefore.
649 // serializeBefore makes the instruction wait in rename until the ROB
650 // is empty.
651
652 // In this model, IPR accesses are serialize before
653 // instructions, and store conditionals are serialize after
654 // instructions. This is mainly due to lack of support for
655 // out-of-order operations of either of those classes of
656 // instructions.
657 if ((inst->isIprAccess() || inst->isSerializeBefore()) &&
658 !inst->isSerializeHandled()) {
659 DPRINTF(Rename, "Serialize before instruction encountered.\n");
660
661 if (!inst->isTempSerializeBefore()) {
662 renamedSerializing++;
663 inst->setSerializeHandled();
664 } else {
665 renamedTempSerializing++;
666 }
667
668 // Change status over to SerializeStall so that other stages know
669 // what this is blocked on.
670 renameStatus[tid] = SerializeStall;
671
672 serializeInst[tid] = inst;
673
674 blockThisCycle = true;
675
676 break;
677 } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) &&
678 !inst->isSerializeHandled()) {
679 DPRINTF(Rename, "Serialize after instruction encountered.\n");
680
681 renamedSerializing++;
682
683 inst->setSerializeHandled();
684
685 serializeAfter(insts_to_rename, tid);
686 }
687
688 renameSrcRegs(inst, inst->threadNumber);
689
690 renameDestRegs(inst, inst->threadNumber);
691
|
692 if (inst->isLoad()) {
693 loadsInProgress[tid]++;
694 }
695 if (inst->isStore()) {
696 storesInProgress[tid]++;
697 } |
698 ++renamed_insts;
699
700
701 // Put instruction in rename queue.
702 toIEW->insts[toIEWIndex] = inst;
703 ++(toIEW->size);
704
705 // Increment which instruction we're on.
706 ++toIEWIndex;
707
708 // Decrement how many instructions are available.
709 --insts_available;
710 }
711
712 instsInProgress[tid] += renamed_insts;
713 renameRenamedInsts += renamed_insts;
714
715 // If we wrote to the time buffer, record this.
716 if (toIEWIndex) {
717 wroteToTimeBuffer = true;
718 }
719
720 // Check if there's any instructions left that haven't yet been renamed.
721 // If so then block.
722 if (insts_available) {
723 blockThisCycle = true;
724 }
725
726 if (blockThisCycle) {
727 block(tid);
728 toDecode->renameUnblock[tid] = false;
729 }
730}
731
732template<class Impl>
733void
734DefaultRename<Impl>::skidInsert(ThreadID tid)
735{
736 DynInstPtr inst = NULL;
737
738 while (!insts[tid].empty()) {
739 inst = insts[tid].front();
740
741 insts[tid].pop_front();
742
743 assert(tid == inst->threadNumber);
744
745 DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC: %s into Rename "
746 "skidBuffer\n", tid, inst->seqNum, inst->pcState());
747
748 ++renameSkidInsts;
749
750 skidBuffer[tid].push_back(inst);
751 }
752
753 if (skidBuffer[tid].size() > skidBufferMax)
754 {
755 typename InstQueue::iterator it;
756 warn("Skidbuffer contents:\n");
757 for(it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++)
758 {
759 warn("[tid:%u]: %s [sn:%i].\n", tid,
760 (*it)->staticInst->disassemble(inst->instAddr()),
761 (*it)->seqNum);
762 }
763 panic("Skidbuffer Exceeded Max Size");
764 }
765}
766
767template <class Impl>
768void
769DefaultRename<Impl>::sortInsts()
770{
771 int insts_from_decode = fromDecode->size;
772 for (int i = 0; i < insts_from_decode; ++i) {
773 DynInstPtr inst = fromDecode->insts[i];
774 insts[inst->threadNumber].push_back(inst);
775#if TRACING_ON
776 if (DTRACE(O3PipeView)) {
777 inst->renameTick = curTick() - inst->fetchTick;
778 }
779#endif
780 }
781}
782
783template<class Impl>
784bool
785DefaultRename<Impl>::skidsEmpty()
786{
787 list<ThreadID>::iterator threads = activeThreads->begin();
788 list<ThreadID>::iterator end = activeThreads->end();
789
790 while (threads != end) {
791 ThreadID tid = *threads++;
792
793 if (!skidBuffer[tid].empty())
794 return false;
795 }
796
797 return true;
798}
799
800template<class Impl>
801void
802DefaultRename<Impl>::updateStatus()
803{
804 bool any_unblocking = false;
805
806 list<ThreadID>::iterator threads = activeThreads->begin();
807 list<ThreadID>::iterator end = activeThreads->end();
808
809 while (threads != end) {
810 ThreadID tid = *threads++;
811
812 if (renameStatus[tid] == Unblocking) {
813 any_unblocking = true;
814 break;
815 }
816 }
817
818 // Rename will have activity if it's unblocking.
819 if (any_unblocking) {
820 if (_status == Inactive) {
821 _status = Active;
822
823 DPRINTF(Activity, "Activating stage.\n");
824
825 cpu->activateStage(O3CPU::RenameIdx);
826 }
827 } else {
828 // If it's not unblocking, then rename will not have any internal
829 // activity. Switch it to inactive.
830 if (_status == Active) {
831 _status = Inactive;
832 DPRINTF(Activity, "Deactivating stage.\n");
833
834 cpu->deactivateStage(O3CPU::RenameIdx);
835 }
836 }
837}
838
839template <class Impl>
840bool
841DefaultRename<Impl>::block(ThreadID tid)
842{
843 DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid);
844
845 // Add the current inputs onto the skid buffer, so they can be
846 // reprocessed when this stage unblocks.
847 skidInsert(tid);
848
849 // Only signal backwards to block if the previous stages do not think
850 // rename is already blocked.
851 if (renameStatus[tid] != Blocked) {
852 // If resumeUnblocking is set, we unblocked during the squash,
853 // but now we're have unblocking status. We need to tell earlier
854 // stages to block.
855 if (resumeUnblocking || renameStatus[tid] != Unblocking) {
856 toDecode->renameBlock[tid] = true;
857 toDecode->renameUnblock[tid] = false;
858 wroteToTimeBuffer = true;
859 }
860
861 // Rename can not go from SerializeStall to Blocked, otherwise
862 // it would not know to complete the serialize stall.
863 if (renameStatus[tid] != SerializeStall) {
864 // Set status to Blocked.
865 renameStatus[tid] = Blocked;
866 return true;
867 }
868 }
869
870 return false;
871}
872
873template <class Impl>
874bool
875DefaultRename<Impl>::unblock(ThreadID tid)
876{
877 DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid);
878
879 // Rename is done unblocking if the skid buffer is empty.
880 if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) {
881
882 DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid);
883
884 toDecode->renameUnblock[tid] = true;
885 wroteToTimeBuffer = true;
886
887 renameStatus[tid] = Running;
888 return true;
889 }
890
891 return false;
892}
893
894template <class Impl>
895void
896DefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, ThreadID tid)
897{
898 typename std::list<RenameHistory>::iterator hb_it =
899 historyBuffer[tid].begin();
900
901 // After a syscall squashes everything, the history buffer may be empty
902 // but the ROB may still be squashing instructions.
903 if (historyBuffer[tid].empty()) {
904 return;
905 }
906
907 // Go through the most recent instructions, undoing the mappings
908 // they did and freeing up the registers.
909 while (!historyBuffer[tid].empty() &&
910 hb_it->instSeqNum > squashed_seq_num) {
911 assert(hb_it != historyBuffer[tid].end());
912
913 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
914 "number %i.\n", tid, hb_it->instSeqNum);
915
916 // Undo the rename mapping only if it was really a change.
917 // Special regs that are not really renamed (like misc regs
918 // and the zero reg) can be recognized because the new mapping
919 // is the same as the old one. While it would be merely a
920 // waste of time to update the rename table, we definitely
921 // don't want to put these on the free list.
922 if (hb_it->newPhysReg != hb_it->prevPhysReg) {
923 // Tell the rename map to set the architected register to the
924 // previous physical register that it was renamed to.
925 renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
926
927 // Put the renamed physical register back on the free list.
928 freeList->addReg(hb_it->newPhysReg);
929 }
930
931 historyBuffer[tid].erase(hb_it++);
932
933 ++renameUndoneMaps;
934 }
935}
936
937template<class Impl>
938void
939DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid)
940{
941 DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the "
942 "history buffer %u (size=%i), until [sn:%lli].\n",
943 tid, tid, historyBuffer[tid].size(), inst_seq_num);
944
945 typename std::list<RenameHistory>::iterator hb_it =
946 historyBuffer[tid].end();
947
948 --hb_it;
949
950 if (historyBuffer[tid].empty()) {
951 DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid);
952 return;
953 } else if (hb_it->instSeqNum > inst_seq_num) {
954 DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure "
955 "that a syscall happened recently.\n", tid);
956 return;
957 }
958
959 // Commit all the renames up until (and including) the committed sequence
960 // number. Some or even all of the committed instructions may not have
961 // rename histories if they did not have destination registers that were
962 // renamed.
963 while (!historyBuffer[tid].empty() &&
964 hb_it != historyBuffer[tid].end() &&
965 hb_it->instSeqNum <= inst_seq_num) {
966
967 DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, "
968 "[sn:%lli].\n",
969 tid, hb_it->prevPhysReg, hb_it->instSeqNum);
970
971 // Don't free special phys regs like misc and zero regs, which
972 // can be recognized because the new mapping is the same as
973 // the old one.
974 if (hb_it->newPhysReg != hb_it->prevPhysReg) {
975 freeList->addReg(hb_it->prevPhysReg);
976 }
977
978 ++renameCommittedMaps;
979
980 historyBuffer[tid].erase(hb_it--);
981 }
982}
983
984template <class Impl>
985inline void
986DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid)
987{
988 ThreadContext *tc = inst->tcBase();
989 RenameMap *map = renameMap[tid];
990 unsigned num_src_regs = inst->numSrcRegs();
991
992 // Get the architectual register numbers from the source and
993 // operands, and redirect them to the right physical register.
994 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) {
995 RegIndex src_reg = inst->srcRegIdx(src_idx);
996 RegIndex rel_src_reg;
997 RegIndex flat_rel_src_reg;
998 PhysRegIndex renamed_reg;
999
1000 switch (regIdxToClass(src_reg, &rel_src_reg)) {
1001 case IntRegClass:
1002 flat_rel_src_reg = tc->flattenIntIndex(rel_src_reg);
1003 renamed_reg = map->lookupInt(flat_rel_src_reg);
1004 intRenameLookups++;
1005 break;
1006
1007 case FloatRegClass:
1008 flat_rel_src_reg = tc->flattenFloatIndex(rel_src_reg);
1009 renamed_reg = map->lookupFloat(flat_rel_src_reg);
1010 fpRenameLookups++;
1011 break;
1012
1013 case CCRegClass:
1014 flat_rel_src_reg = tc->flattenCCIndex(rel_src_reg);
1015 renamed_reg = map->lookupCC(flat_rel_src_reg);
1016 break;
1017
1018 case MiscRegClass:
1019 // misc regs don't get flattened
1020 flat_rel_src_reg = rel_src_reg;
1021 renamed_reg = map->lookupMisc(flat_rel_src_reg);
1022 break;
1023
1024 default:
1025 panic("Reg index is out of bound: %d.", src_reg);
1026 }
1027
1028 DPRINTF(Rename, "[tid:%u]: Looking up %s arch reg %i (flattened %i), "
1029 "got phys reg %i\n", tid, RegClassStrings[regIdxToClass(src_reg)],
1030 (int)src_reg, (int)flat_rel_src_reg, (int)renamed_reg);
1031
1032 inst->renameSrcReg(src_idx, renamed_reg);
1033
1034 // See if the register is ready or not.
1035 if (scoreboard->getReg(renamed_reg)) {
1036 DPRINTF(Rename, "[tid:%u]: Register %d is ready.\n",
1037 tid, renamed_reg);
1038
1039 inst->markSrcRegReady(src_idx);
1040 } else {
1041 DPRINTF(Rename, "[tid:%u]: Register %d is not ready.\n",
1042 tid, renamed_reg);
1043 }
1044
1045 ++renameRenameLookups;
1046 }
1047}
1048
1049template <class Impl>
1050inline void
1051DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid)
1052{
1053 ThreadContext *tc = inst->tcBase();
1054 RenameMap *map = renameMap[tid];
1055 unsigned num_dest_regs = inst->numDestRegs();
1056
1057 // Rename the destination registers.
1058 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) {
1059 RegIndex dest_reg = inst->destRegIdx(dest_idx);
1060 RegIndex rel_dest_reg;
1061 RegIndex flat_rel_dest_reg;
1062 RegIndex flat_uni_dest_reg;
1063 typename RenameMap::RenameInfo rename_result;
1064
1065 switch (regIdxToClass(dest_reg, &rel_dest_reg)) {
1066 case IntRegClass:
1067 flat_rel_dest_reg = tc->flattenIntIndex(rel_dest_reg);
1068 rename_result = map->renameInt(flat_rel_dest_reg);
1069 flat_uni_dest_reg = flat_rel_dest_reg; // 1:1 mapping
1070 break;
1071
1072 case FloatRegClass:
1073 flat_rel_dest_reg = tc->flattenFloatIndex(rel_dest_reg);
1074 rename_result = map->renameFloat(flat_rel_dest_reg);
1075 flat_uni_dest_reg = flat_rel_dest_reg + TheISA::FP_Reg_Base;
1076 break;
1077
1078 case CCRegClass:
1079 flat_rel_dest_reg = tc->flattenCCIndex(rel_dest_reg);
1080 rename_result = map->renameCC(flat_rel_dest_reg);
1081 flat_uni_dest_reg = flat_rel_dest_reg + TheISA::CC_Reg_Base;
1082 break;
1083
1084 case MiscRegClass:
1085 // misc regs don't get flattened
1086 flat_rel_dest_reg = rel_dest_reg;
1087 rename_result = map->renameMisc(flat_rel_dest_reg);
1088 flat_uni_dest_reg = flat_rel_dest_reg + TheISA::Misc_Reg_Base;
1089 break;
1090
1091 default:
1092 panic("Reg index is out of bound: %d.", dest_reg);
1093 }
1094
1095 inst->flattenDestReg(dest_idx, flat_uni_dest_reg);
1096
1097 // Mark Scoreboard entry as not ready
1098 scoreboard->unsetReg(rename_result.first);
1099
1100 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical "
1101 "reg %i.\n", tid, (int)flat_rel_dest_reg,
1102 (int)rename_result.first);
1103
1104 // Record the rename information so that a history can be kept.
1105 RenameHistory hb_entry(inst->seqNum, flat_uni_dest_reg,
1106 rename_result.first,
1107 rename_result.second);
1108
1109 historyBuffer[tid].push_front(hb_entry);
1110
1111 DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer "
1112 "(size=%i), [sn:%lli].\n",tid,
1113 historyBuffer[tid].size(),
1114 (*historyBuffer[tid].begin()).instSeqNum);
1115
1116 // Tell the instruction to rename the appropriate destination
1117 // register (dest_idx) to the new physical register
1118 // (rename_result.first), and record the previous physical
1119 // register that the same logical register was renamed to
1120 // (rename_result.second).
1121 inst->renameDestReg(dest_idx,
1122 rename_result.first,
1123 rename_result.second);
1124
1125 ++renameRenamedOperands;
1126 }
1127}
1128
1129template <class Impl>
1130inline int
1131DefaultRename<Impl>::calcFreeROBEntries(ThreadID tid)
1132{
1133 int num_free = freeEntries[tid].robEntries -
1134 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1135
1136 //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free);
1137
1138 return num_free;
1139}
1140
1141template <class Impl>
1142inline int
1143DefaultRename<Impl>::calcFreeIQEntries(ThreadID tid)
1144{
1145 int num_free = freeEntries[tid].iqEntries -
1146 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1147
1148 //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free);
1149
1150 return num_free;
1151}
1152
1153template <class Impl>
1154inline int
|
1125DefaultRename<Impl>::calcFreeLSQEntries(ThreadID tid)
|
| 1155DefaultRename::calcFreeLQEntries(ThreadID tid) |
1156{
|
1127 int num_free = freeEntries[tid].lsqEntries -
1128 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ);
|
1157 int num_free = freeEntries[tid].lqEntries -
1158 (loadsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLQ);
1159 DPRINTF(Rename, "calcFreeLQEntries: free lqEntries: %d, loadsInProgress: %d, "
1160 "loads dispatchedToLQ: %d\n", freeEntries[tid].lqEntries,
1161 loadsInProgress[tid], fromIEW->iewInfo[tid].dispatchedToLQ);
1162 return num_free;
1163} |
1164
|
1130 //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free);
1131
1132 return num_free;
|
1165template <class Impl>
1166inline int
1167DefaultRename<Impl>::calcFreeSQEntries(ThreadID tid)
1168{
1169 int num_free = freeEntries[tid].sqEntries -
1170 (storesInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToSQ);
1171 DPRINTF(Rename, "calcFreeSQEntries: free sqEntries: %d, storesInProgress: %d, "
1172 "stores dispatchedToSQ: %d\n", freeEntries[tid].sqEntries,
1173 storesInProgress[tid], fromIEW->iewInfo[tid].dispatchedToSQ);
1174 return num_free; |
1175}
1176
1177template <class Impl>
1178unsigned
1179DefaultRename<Impl>::validInsts()
1180{
1181 unsigned inst_count = 0;
1182
1183 for (int i=0; i<fromDecode->size; i++) {
1184 if (!fromDecode->insts[i]->isSquashed())
1185 inst_count++;
1186 }
1187
1188 return inst_count;
1189}
1190
1191template <class Impl>
1192void
1193DefaultRename<Impl>::readStallSignals(ThreadID tid)
1194{
1195 if (fromIEW->iewBlock[tid]) {
1196 stalls[tid].iew = true;
1197 }
1198
1199 if (fromIEW->iewUnblock[tid]) {
1200 assert(stalls[tid].iew);
1201 stalls[tid].iew = false;
1202 }
1203
1204 if (fromCommit->commitBlock[tid]) {
1205 stalls[tid].commit = true;
1206 }
1207
1208 if (fromCommit->commitUnblock[tid]) {
1209 assert(stalls[tid].commit);
1210 stalls[tid].commit = false;
1211 }
1212}
1213
1214template <class Impl>
1215bool
1216DefaultRename<Impl>::checkStall(ThreadID tid)
1217{
1218 bool ret_val = false;
1219
1220 if (stalls[tid].iew) {
1221 DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid);
1222 ret_val = true;
1223 } else if (stalls[tid].commit) {
1224 DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid);
1225 ret_val = true;
1226 } else if (calcFreeROBEntries(tid) <= 0) {
1227 DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid);
1228 ret_val = true;
1229 } else if (calcFreeIQEntries(tid) <= 0) {
1230 DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid);
1231 ret_val = true;
|
1190 } else if (calcFreeLSQEntries(tid) <= 0) {
|
| 1232 } else if (calcFreeLQEntries(tid) <= 0 && calcFreeSQEntries(tid) <= 0) { |
1233 DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid);
1234 ret_val = true;
1235 } else if (renameMap[tid]->numFreeEntries() <= 0) {
1236 DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid);
1237 ret_val = true;
1238 } else if (renameStatus[tid] == SerializeStall &&
1239 (!emptyROB[tid] || instsInProgress[tid])) {
1240 DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not "
1241 "empty.\n",
1242 tid);
1243 ret_val = true;
1244 }
1245
1246 return ret_val;
1247}
1248
1249template <class Impl>
1250void
1251DefaultRename<Impl>::readFreeEntries(ThreadID tid)
1252{
1253 if (fromIEW->iewInfo[tid].usedIQ)
1254 freeEntries[tid].iqEntries = fromIEW->iewInfo[tid].freeIQEntries;
1255
|
1214 if (fromIEW->iewInfo[tid].usedLSQ)
1215 freeEntries[tid].lsqEntries = fromIEW->iewInfo[tid].freeLSQEntries;
|
1256 if (fromIEW->iewInfo[tid].usedLSQ) {
1257 freeEntries[tid].lqEntries = fromIEW->iewInfo[tid].freeLQEntries;
1258 freeEntries[tid].sqEntries = fromIEW->iewInfo[tid].freeSQEntries;
1259 } |
1260
1261 if (fromCommit->commitInfo[tid].usedROB) {
1262 freeEntries[tid].robEntries =
1263 fromCommit->commitInfo[tid].freeROBEntries;
1264 emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB;
1265 }
1266
|
1223 DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n",
|
1267 DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, "
1268 "Free LQ: %i, Free SQ: %i\n", |
1269 tid,
1270 freeEntries[tid].iqEntries,
1271 freeEntries[tid].robEntries,
|
1227 freeEntries[tid].lsqEntries);
|
1272 freeEntries[tid].lqEntries,
1273 freeEntries[tid].sqEntries); |
1274
1275 DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n",
1276 tid, instsInProgress[tid]);
1277}
1278
1279template <class Impl>
1280bool
1281DefaultRename<Impl>::checkSignalsAndUpdate(ThreadID tid)
1282{
1283 // Check if there's a squash signal, squash if there is
1284 // Check stall signals, block if necessary.
1285 // If status was blocked
1286 // check if stall conditions have passed
1287 // if so then go to unblocking
1288 // If status was Squashing
1289 // check if squashing is not high. Switch to running this cycle.
1290 // If status was serialize stall
1291 // check if ROB is empty and no insts are in flight to the ROB
1292
1293 readFreeEntries(tid);
1294 readStallSignals(tid);
1295
1296 if (fromCommit->commitInfo[tid].squash) {
1297 DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from "
1298 "commit.\n", tid);
1299
1300 squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
1301
1302 return true;
1303 }
1304
1305 if (fromCommit->commitInfo[tid].robSquashing) {
1306 DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid);
1307
1308 renameStatus[tid] = Squashing;
1309
1310 return true;
1311 }
1312
1313 if (checkStall(tid)) {
1314 return block(tid);
1315 }
1316
1317 if (renameStatus[tid] == Blocked) {
1318 DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n",
1319 tid);
1320
1321 renameStatus[tid] = Unblocking;
1322
1323 unblock(tid);
1324
1325 return true;
1326 }
1327
1328 if (renameStatus[tid] == Squashing) {
1329 // Switch status to running if rename isn't being told to block or
1330 // squash this cycle.
1331 if (resumeSerialize) {
1332 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n",
1333 tid);
1334
1335 renameStatus[tid] = SerializeStall;
1336 return true;
1337 } else if (resumeUnblocking) {
1338 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n",
1339 tid);
1340 renameStatus[tid] = Unblocking;
1341 return true;
1342 } else {
1343 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n",
1344 tid);
1345
1346 renameStatus[tid] = Running;
1347 return false;
1348 }
1349 }
1350
1351 if (renameStatus[tid] == SerializeStall) {
1352 // Stall ends once the ROB is free.
1353 DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to "
1354 "unblocking.\n", tid);
1355
1356 DynInstPtr serial_inst = serializeInst[tid];
1357
1358 renameStatus[tid] = Unblocking;
1359
1360 unblock(tid);
1361
1362 DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with "
1363 "PC %s.\n", tid, serial_inst->seqNum, serial_inst->pcState());
1364
1365 // Put instruction into queue here.
1366 serial_inst->clearSerializeBefore();
1367
1368 if (!skidBuffer[tid].empty()) {
1369 skidBuffer[tid].push_front(serial_inst);
1370 } else {
1371 insts[tid].push_front(serial_inst);
1372 }
1373
1374 DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename."
1375 " Adding to front of list.\n", tid);
1376
1377 serializeInst[tid] = NULL;
1378
1379 return true;
1380 }
1381
1382 // If we've reached this point, we have not gotten any signals that
1383 // cause rename to change its status. Rename remains the same as before.
1384 return false;
1385}
1386
1387template<class Impl>
1388void
1389DefaultRename<Impl>::serializeAfter(InstQueue &inst_list, ThreadID tid)
1390{
1391 if (inst_list.empty()) {
1392 // Mark a bit to say that I must serialize on the next instruction.
1393 serializeOnNextInst[tid] = true;
1394 return;
1395 }
1396
1397 // Set the next instruction as serializing.
1398 inst_list.front()->setSerializeBefore();
1399}
1400
1401template <class Impl>
1402inline void
1403DefaultRename<Impl>::incrFullStat(const FullSource &source)
1404{
1405 switch (source) {
1406 case ROB:
1407 ++renameROBFullEvents;
1408 break;
1409 case IQ:
1410 ++renameIQFullEvents;
1411 break;
|
1366 case LSQ:
1367 ++renameLSQFullEvents;
|
1412 case LQ:
1413 ++renameLQFullEvents; |
1414 break;
|
1415 case SQ:
1416 ++renameSQFullEvents;
1417 break; |
1418 default:
1419 panic("Rename full stall stat should be incremented for a reason!");
1420 break;
1421 }
1422}
1423
1424template <class Impl>
1425void
1426DefaultRename<Impl>::dumpHistory()
1427{
1428 typename std::list<RenameHistory>::iterator buf_it;
1429
1430 for (ThreadID tid = 0; tid < numThreads; tid++) {
1431
1432 buf_it = historyBuffer[tid].begin();
1433
1434 while (buf_it != historyBuffer[tid].end()) {
1435 cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys "
1436 "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg,
1437 (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg);
1438
1439 buf_it++;
1440 }
1441 }
1442}
1443
1444#endif//__CPU_O3_RENAME_IMPL_HH__
|