1/* 2 * Copyright (c) 2010-2012 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 857 unchanged lines hidden (view full) --- 866 // but the ROB may still be squashing instructions. 867 if (historyBuffer[tid].empty()) { 868 return; 869 } 870 871 // Go through the most recent instructions, undoing the mappings 872 // they did and freeing up the registers. 873 while (!historyBuffer[tid].empty() && |
874 hb_it->instSeqNum > squashed_seq_num) { |
875 assert(hb_it != historyBuffer[tid].end()); 876 877 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " |
878 "number %i.\n", tid, hb_it->instSeqNum); |
879 |
880 // Undo the rename mapping only if it was really a change. 881 // Special regs that are not really renamed (like misc regs 882 // and the zero reg) can be recognized because the new mapping 883 // is the same as the old one. While it would be merely a 884 // waste of time to update the rename table, we definitely 885 // don't want to put these on the free list. 886 if (hb_it->newPhysReg != hb_it->prevPhysReg) { 887 // Tell the rename map to set the architected register to the 888 // previous physical register that it was renamed to. 889 renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg); |
890 |
891 // Put the renamed physical register back on the free list. 892 freeList->addReg(hb_it->newPhysReg); 893 } |
894 895 historyBuffer[tid].erase(hb_it++); 896 897 ++renameUndoneMaps; 898 } 899} 900 901template<class Impl> --- 19 unchanged lines hidden (view full) --- 921 } 922 923 // Commit all the renames up until (and including) the committed sequence 924 // number. Some or even all of the committed instructions may not have 925 // rename histories if they did not have destination registers that were 926 // renamed. 927 while (!historyBuffer[tid].empty() && 928 hb_it != historyBuffer[tid].end() && |
929 hb_it->instSeqNum <= inst_seq_num) { |
930 931 DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, " 932 "[sn:%lli].\n", |
933 tid, hb_it->prevPhysReg, hb_it->instSeqNum); |
934 |
935 // Don't free special phys regs like misc and zero regs, which 936 // can be recognized because the new mapping is the same as 937 // the old one. 938 if (hb_it->newPhysReg != hb_it->prevPhysReg) { 939 freeList->addReg(hb_it->prevPhysReg); 940 } 941 |
942 ++renameCommittedMaps; 943 944 historyBuffer[tid].erase(hb_it--); 945 } 946} 947 948template <class Impl> 949inline void 950DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid) 951{ |
952 ThreadContext *tc = inst->tcBase(); 953 RenameMap *map = renameMap[tid]; |
954 unsigned num_src_regs = inst->numSrcRegs(); 955 956 // Get the architectual register numbers from the source and |
957 // operands, and redirect them to the right physical register. |
958 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) { 959 RegIndex src_reg = inst->srcRegIdx(src_idx); |
960 RegIndex rel_src_reg; 961 RegIndex flat_rel_src_reg; 962 PhysRegIndex renamed_reg; 963 964 switch (regIdxToClass(src_reg, &rel_src_reg)) { |
965 case IntRegClass: |
966 flat_rel_src_reg = tc->flattenIntIndex(rel_src_reg); 967 renamed_reg = map->lookupInt(flat_rel_src_reg); 968 intRenameLookups++; |
969 break; 970 971 case FloatRegClass: |
972 flat_rel_src_reg = tc->flattenFloatIndex(rel_src_reg); 973 renamed_reg = map->lookupFloat(flat_rel_src_reg); 974 fpRenameLookups++; |
975 break; 976 977 case MiscRegClass: |
978 // misc regs don't get flattened 979 flat_rel_src_reg = rel_src_reg; 980 renamed_reg = map->lookupMisc(flat_rel_src_reg); |
981 break; 982 983 default: 984 panic("Reg index is out of bound: %d.", src_reg); 985 } 986 |
987 DPRINTF(Rename, "[tid:%u]: Looking up %s arch reg %i (flattened %i), " 988 "got phys reg %i\n", tid, RegClassStrings[regIdxToClass(src_reg)], 989 (int)src_reg, (int)flat_rel_src_reg, (int)renamed_reg); |
990 |
991 inst->renameSrcReg(src_idx, renamed_reg); 992 993 // See if the register is ready or not. |
994 if (scoreboard->getReg(renamed_reg)) { |
995 DPRINTF(Rename, "[tid:%u]: Register %d is ready.\n", 996 tid, renamed_reg); 997 998 inst->markSrcRegReady(src_idx); 999 } else { 1000 DPRINTF(Rename, "[tid:%u]: Register %d is not ready.\n", 1001 tid, renamed_reg); 1002 } 1003 1004 ++renameRenameLookups; |
1005 } 1006} 1007 1008template <class Impl> 1009inline void 1010DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid) 1011{ |
1012 ThreadContext *tc = inst->tcBase(); 1013 RenameMap *map = renameMap[tid]; |
1014 unsigned num_dest_regs = inst->numDestRegs(); 1015 1016 // Rename the destination registers. 1017 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) { 1018 RegIndex dest_reg = inst->destRegIdx(dest_idx); |
1019 RegIndex rel_dest_reg; 1020 RegIndex flat_rel_dest_reg; 1021 RegIndex flat_uni_dest_reg; 1022 typename RenameMap::RenameInfo rename_result; 1023 1024 switch (regIdxToClass(dest_reg, &rel_dest_reg)) { |
1025 case IntRegClass: |
1026 flat_rel_dest_reg = tc->flattenIntIndex(rel_dest_reg); 1027 rename_result = map->renameInt(flat_rel_dest_reg); 1028 flat_uni_dest_reg = flat_rel_dest_reg; // 1:1 mapping |
1029 break; 1030 1031 case FloatRegClass: |
1032 flat_rel_dest_reg = tc->flattenFloatIndex(rel_dest_reg); 1033 rename_result = map->renameFloat(flat_rel_dest_reg); 1034 flat_uni_dest_reg = flat_rel_dest_reg + TheISA::FP_Reg_Base; |
1035 break; 1036 1037 case MiscRegClass: |
1038 // misc regs don't get flattened 1039 flat_rel_dest_reg = rel_dest_reg; 1040 rename_result = map->renameMisc(flat_rel_dest_reg); 1041 flat_uni_dest_reg = flat_rel_dest_reg + TheISA::Misc_Reg_Base; |
1042 break; 1043 1044 default: 1045 panic("Reg index is out of bound: %d.", dest_reg); 1046 } 1047 |
1048 inst->flattenDestReg(dest_idx, flat_uni_dest_reg); |
1049 |
1050 // Mark Scoreboard entry as not ready |
1051 scoreboard->unsetReg(rename_result.first); 1052 1053 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical " |
1054 "reg %i.\n", tid, (int)flat_rel_dest_reg, |
1055 (int)rename_result.first); 1056 1057 // Record the rename information so that a history can be kept. |
1058 RenameHistory hb_entry(inst->seqNum, flat_uni_dest_reg, |
1059 rename_result.first, 1060 rename_result.second); 1061 1062 historyBuffer[tid].push_front(hb_entry); 1063 1064 DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer " 1065 "(size=%i), [sn:%lli].\n",tid, 1066 historyBuffer[tid].size(), --- 310 unchanged lines hidden --- |