1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 17 unchanged lines hidden (view full) --- 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 * Korey Sewell 30 */ 31 32#include <list> 33 |
34#include "config/full_system.hh" 35#include "cpu/o3/rename.hh" 36 37template <class Impl> 38DefaultRename<Impl>::DefaultRename(Params *params) 39 : iewToRenameDelay(params->iewToRenameDelay), 40 decodeToRenameDelay(params->decodeToRenameDelay), 41 commitToRenameDelay(params->commitToRenameDelay), 42 renameWidth(params->renameWidth), 43 commitWidth(params->commitWidth), |
44 numThreads(params->numberOfThreads), 45 maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs) 46{ 47 _status = Inactive; 48 49 for (int i=0; i< numThreads; i++) { 50 renameStatus[i] = Idle; 51 --- 275 unchanged lines hidden (view full) --- 327DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, unsigned tid) 328{ 329 DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid); 330 331 // Clear the stall signal if rename was blocked or unblocking before. 332 // If it still needs to block, the blocking should happen the next 333 // cycle and there should be space to hold everything due to the squash. 334 if (renameStatus[tid] == Blocked || |
335 renameStatus[tid] == Unblocking || 336 renameStatus[tid] == SerializeStall) { 337 |
338 toDecode->renameUnblock[tid] = 1; 339 |
340 serializeInst[tid] = NULL; |
341 } 342 343 // Set the status to Squashing. 344 renameStatus[tid] = Squashing; 345 346 // Squash any instructions from decode. 347 unsigned squashCount = 0; 348 --- 38 unchanged lines hidden (view full) --- 387 while (slist_it != skidBuffer[tid].end()) { 388 if ((*slist_it)->seqNum > squash_seq_num) { 389 (*slist_it)->setSquashed(); 390 DPRINTF(Rename, "Squashing skidbuffer instruction, [tid:%i] [sn:%i]" 391 "PC %08p.\n", tid, (*slist_it)->seqNum, (*slist_it)->PC); 392 } 393 slist_it++; 394 } |
395#else 396 skidBuffer[tid].clear(); 397#endif 398 doSquash(squash_seq_num, tid); 399} 400 401template <class Impl> 402void --- 4 unchanged lines hidden (view full) --- 407 blockThisCycle = false; 408 409 bool status_change = false; 410 411 toIEWIndex = 0; 412 413 sortInsts(); 414 |
415 std::list<unsigned>::iterator threads = activeThreads->begin(); 416 std::list<unsigned>::iterator end = activeThreads->end(); |
417 418 // Check stall and squash signals. |
419 while (threads != end) { |
420 unsigned tid = *threads++; 421 422 DPRINTF(Rename, "Processing [tid:%i]\n", tid); 423 424 status_change = checkSignalsAndUpdate(tid) || status_change; 425 426 rename(status_change, tid); 427 } 428 429 if (status_change) { 430 updateStatus(); 431 } 432 433 if (wroteToTimeBuffer) { 434 DPRINTF(Activity, "Activity this cycle.\n"); 435 cpu->activityThisCycle(); 436 } 437 |
438 threads = activeThreads->begin(); |
439 |
440 while (threads != end) { |
441 unsigned tid = *threads++; 442 443 // If we committed this cycle then doneSeqNum will be > 0 444 if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 445 !fromCommit->commitInfo[tid].squash && 446 renameStatus[tid] != Squashing) { 447 448 removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum, --- 22 unchanged lines hidden (view full) --- 471 // check if stall conditions have passed 472 473 if (renameStatus[tid] == Blocked) { 474 ++renameBlockCycles; 475 } else if (renameStatus[tid] == Squashing) { 476 ++renameSquashCycles; 477 } else if (renameStatus[tid] == SerializeStall) { 478 ++renameSerializeStallCycles; |
479 } 480 481 if (renameStatus[tid] == Running || 482 renameStatus[tid] == Idle) { 483 DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run " 484 "stage.\n", tid); 485 486 renameInsts(tid); --- 249 unchanged lines hidden (view full) --- 736 "skidBuffer\n", tid, inst->seqNum, inst->readPC()); 737 738 ++renameSkidInsts; 739 740 skidBuffer[tid].push_back(inst); 741 } 742 743 if (skidBuffer[tid].size() > skidBufferMax) |
744 panic("Skidbuffer Exceeded Max Size"); |
745} 746 747template <class Impl> 748void 749DefaultRename<Impl>::sortInsts() 750{ 751 int insts_from_decode = fromDecode->size; 752#ifdef DEBUG --- 7 unchanged lines hidden (view full) --- 760 insts[inst->threadNumber].push_back(inst); 761 } 762} 763 764template<class Impl> 765bool 766DefaultRename<Impl>::skidsEmpty() 767{ |
768 std::list<unsigned>::iterator threads = activeThreads->begin(); 769 std::list<unsigned>::iterator end = activeThreads->end(); |
770 |
771 while (threads != end) { 772 unsigned tid = *threads++; 773 774 if (!skidBuffer[tid].empty()) |
775 return false; 776 } 777 778 return true; 779} 780 781template<class Impl> 782void 783DefaultRename<Impl>::updateStatus() 784{ 785 bool any_unblocking = false; 786 |
787 std::list<unsigned>::iterator threads = activeThreads->begin(); 788 std::list<unsigned>::iterator end = activeThreads->end(); |
789 |
790 while (threads != end) { |
791 unsigned tid = *threads++; 792 793 if (renameStatus[tid] == Unblocking) { 794 any_unblocking = true; 795 break; 796 } 797 } 798 --- 26 unchanged lines hidden (view full) --- 825 826 // Add the current inputs onto the skid buffer, so they can be 827 // reprocessed when this stage unblocks. 828 skidInsert(tid); 829 830 // Only signal backwards to block if the previous stages do not think 831 // rename is already blocked. 832 if (renameStatus[tid] != Blocked) { |
833 if (renameStatus[tid] != Unblocking) { |
834 toDecode->renameBlock[tid] = true; 835 toDecode->renameUnblock[tid] = false; 836 wroteToTimeBuffer = true; 837 } 838 839 // Rename can not go from SerializeStall to Blocked, otherwise 840 // it would not know to complete the serialize stall. 841 if (renameStatus[tid] != SerializeStall) { --- 116 unchanged lines hidden (view full) --- 958 959 unsigned num_src_regs = inst->numSrcRegs(); 960 961 // Get the architectual register numbers from the source and 962 // destination operands, and redirect them to the right register. 963 // Will need to mark dependencies though. 964 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) { 965 RegIndex src_reg = inst->srcRegIdx(src_idx); |
966 967 // Look up the source registers to get the phys. register they've 968 // been renamed to, and set the sources to those registers. |
969 PhysRegIndex renamed_reg = renameMap[tid]->lookup(src_reg); |
970 971 DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got " |
972 "physical reg %i.\n", tid, (int)src_reg, |
973 (int)renamed_reg); 974 975 inst->renameSrcReg(src_idx, renamed_reg); 976 977 // See if the register is ready or not. 978 if (scoreboard->getReg(renamed_reg) == true) { 979 DPRINTF(Rename, "[tid:%u]: Register is ready.\n", tid); 980 --- 10 unchanged lines hidden (view full) --- 991{ 992 typename RenameMap::RenameInfo rename_result; 993 994 unsigned num_dest_regs = inst->numDestRegs(); 995 996 // Rename the destination registers. 997 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) { 998 RegIndex dest_reg = inst->destRegIdx(dest_idx); |
999 |
1000 // Get the physical register that the destination will be 1001 // renamed to. |
1002 rename_result = renameMap[tid]->rename(dest_reg); |
1003 1004 //Mark Scoreboard entry as not ready 1005 scoreboard->unsetReg(rename_result.first); 1006 1007 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical " |
1008 "reg %i.\n", tid, (int)dest_reg, |
1009 (int)rename_result.first); 1010 1011 // Record the rename information so that a history can be kept. |
1012 RenameHistory hb_entry(inst->seqNum, dest_reg, |
1013 rename_result.first, 1014 rename_result.second); 1015 1016 historyBuffer[tid].push_front(hb_entry); 1017 1018 DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer " 1019 "(size=%i), [sn:%lli].\n",tid, 1020 historyBuffer[tid].size(), --- 207 unchanged lines hidden (view full) --- 1228 unblock(tid); 1229 1230 return true; 1231 } 1232 1233 if (renameStatus[tid] == Squashing) { 1234 // Switch status to running if rename isn't being told to block or 1235 // squash this cycle. |
1236 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n", 1237 tid); |
1238 |
1239 renameStatus[tid] = Running; |
1240 |
1241 return false; |
1242 } 1243 1244 if (renameStatus[tid] == SerializeStall) { 1245 // Stall ends once the ROB is free. 1246 DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to " 1247 "unblocking.\n", tid); 1248 1249 DynInstPtr serial_inst = serializeInst[tid]; --- 85 unchanged lines hidden --- |