1/* 2 * Copyright (c) 2010-2012, 2014-2016 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 53 unchanged lines hidden (view full) --- 62template <class Impl> 63DefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params) 64 : cpu(_cpu), 65 iewToRenameDelay(params->iewToRenameDelay), 66 decodeToRenameDelay(params->decodeToRenameDelay), 67 commitToRenameDelay(params->commitToRenameDelay), 68 renameWidth(params->renameWidth), 69 commitWidth(params->commitWidth), |
70 numThreads(params->numThreads) |
71{ 72 if (renameWidth > Impl::MaxWidth) 73 fatal("renameWidth (%d) is larger than compiled limit (%d),\n" 74 "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 75 renameWidth, static_cast<int>(Impl::MaxWidth)); 76 77 // @todo: Make into a parameter. 78 skidBufferMax = (decodeToRenameDelay + 1) * params->decodeWidth; --- 96 unchanged lines hidden (view full) --- 175 intRenameLookups 176 .name(name() + ".int_rename_lookups") 177 .desc("Number of integer rename lookups") 178 .prereq(intRenameLookups); 179 fpRenameLookups 180 .name(name() + ".fp_rename_lookups") 181 .desc("Number of floating rename lookups") 182 .prereq(fpRenameLookups); |
183 vecRenameLookups 184 .name(name() + ".vec_rename_lookups") 185 .desc("Number of vector rename lookups") 186 .prereq(vecRenameLookups); |
187} 188 189template <class Impl> 190void 191DefaultRename<Impl>::regProbePoints() 192{ 193 ppRename = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Rename"); 194 ppSquashInRename = new ProbePointArg<SeqNumRegPair>(cpu->getProbeManager(), --- 447 unchanged lines hidden (view full) --- 642 643 DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with " 644 "PC %s.\n", tid, inst->seqNum, inst->pcState()); 645 646 // Check here to make sure there are enough destination registers 647 // to rename to. Otherwise block. 648 if (!renameMap[tid]->canRename(inst->numIntDestRegs(), 649 inst->numFPDestRegs(), |
650 inst->numVecDestRegs(), 651 inst->numVecElemDestRegs(), |
652 inst->numCCDestRegs())) { 653 DPRINTF(Rename, "Blocking due to lack of free " 654 "physical registers to rename to.\n"); 655 blockThisCycle = true; 656 insts_to_rename.push_front(inst); 657 ++renameFullRegistersEvents; 658 659 break; --- 578 unchanged lines hidden (view full) --- 1238 1239 if (fromCommit->commitInfo[tid].usedROB) { 1240 freeEntries[tid].robEntries = 1241 fromCommit->commitInfo[tid].freeROBEntries; 1242 emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB; 1243 } 1244 1245 DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, " |
1246 "Free LQ: %i, Free SQ: %i, FreeRM %i(%i %i %i %i)\n", |
1247 tid, 1248 freeEntries[tid].iqEntries, 1249 freeEntries[tid].robEntries, 1250 freeEntries[tid].lqEntries, |
1251 freeEntries[tid].sqEntries, 1252 renameMap[tid]->numFreeEntries(), 1253 renameMap[tid]->numFreeIntEntries(), 1254 renameMap[tid]->numFreeFloatEntries(), 1255 renameMap[tid]->numFreeVecEntries(), 1256 renameMap[tid]->numFreeCCEntries()); |
1257 1258 DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n", 1259 tid, instsInProgress[tid]); 1260} 1261 1262template <class Impl> 1263bool 1264DefaultRename<Impl>::checkSignalsAndUpdate(ThreadID tid) --- 161 unchanged lines hidden --- |