1/* 2 * Copyright (c) 2010-2012, 2014-2015 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 969 unchanged lines hidden (view full) --- 978 // Commit all the renames up until (and including) the committed sequence 979 // number. Some or even all of the committed instructions may not have 980 // rename histories if they did not have destination registers that were 981 // renamed. 982 while (!historyBuffer[tid].empty() && 983 hb_it != historyBuffer[tid].end() && 984 hb_it->instSeqNum <= inst_seq_num) { 985 |
986 DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i (%s), " |
987 "[sn:%lli].\n", |
988 tid, hb_it->prevPhysReg->regIdx, 989 RegClassStrings[hb_it->prevPhysReg->regClass], 990 hb_it->instSeqNum); |
991 992 // Don't free special phys regs like misc and zero regs, which 993 // can be recognized because the new mapping is the same as 994 // the old one. 995 if (hb_it->newPhysReg != hb_it->prevPhysReg) { 996 freeList->addReg(hb_it->prevPhysReg); 997 } 998 --- 11 unchanged lines hidden (view full) --- 1010 RenameMap *map = renameMap[tid]; 1011 unsigned num_src_regs = inst->numSrcRegs(); 1012 1013 // Get the architectual register numbers from the source and 1014 // operands, and redirect them to the right physical register. 1015 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) { 1016 RegId src_reg = inst->srcRegIdx(src_idx); 1017 RegIndex flat_src_reg; |
1018 PhysRegIdPtr renamed_reg; |
1019 1020 switch (src_reg.regClass) { 1021 case IntRegClass: 1022 flat_src_reg = tc->flattenIntIndex(src_reg.regIdx); 1023 renamed_reg = map->lookupInt(flat_src_reg); 1024 intRenameLookups++; 1025 break; 1026 --- 13 unchanged lines hidden (view full) --- 1040 flat_src_reg = src_reg.regIdx; 1041 renamed_reg = map->lookupMisc(flat_src_reg); 1042 break; 1043 1044 default: 1045 panic("Invalid register class: %d.", src_reg.regClass); 1046 } 1047 |
1048 DPRINTF(Rename, "[tid:%u]: Looking up %s arch reg %i" 1049 " (flattened %i), got phys reg %i (%s)\n", tid, 1050 RegClassStrings[src_reg.regClass], src_reg.regIdx, 1051 flat_src_reg, renamed_reg->regIdx, 1052 RegClassStrings[renamed_reg->regClass]); |
1053 1054 inst->renameSrcReg(src_idx, renamed_reg); 1055 1056 // See if the register is ready or not. 1057 if (scoreboard->getReg(renamed_reg)) { |
1058 DPRINTF(Rename, "[tid:%u]: Register %d (flat: %d) (%s)" 1059 " is ready.\n", tid, renamed_reg->regIdx, 1060 renamed_reg->flatIdx, 1061 RegClassStrings[renamed_reg->regClass]); |
1062 1063 inst->markSrcRegReady(src_idx); 1064 } else { |
1065 DPRINTF(Rename, "[tid:%u]: Register %d (flat: %d) (%s)" 1066 " is not ready.\n", tid, renamed_reg->regIdx, 1067 renamed_reg->flatIdx, 1068 RegClassStrings[renamed_reg->regClass]); |
1069 } 1070 1071 ++renameRenameLookups; 1072 } 1073} 1074 1075template <class Impl> 1076inline void --- 37 unchanged lines hidden (view full) --- 1114 1115 RegId flat_uni_dest_reg(dest_reg.regClass, flat_dest_reg); 1116 1117 inst->flattenDestReg(dest_idx, flat_uni_dest_reg); 1118 1119 // Mark Scoreboard entry as not ready 1120 scoreboard->unsetReg(rename_result.first); 1121 |
1122 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i (%s) to physical " 1123 "reg %i (%i).\n", tid, dest_reg.regIdx, 1124 RegClassStrings[dest_reg.regClass], 1125 rename_result.first->regIdx, 1126 rename_result.first->flatIdx); |
1127 1128 // Record the rename information so that a history can be kept. 1129 RenameHistory hb_entry(inst->seqNum, flat_uni_dest_reg, 1130 rename_result.first, 1131 rename_result.second); 1132 1133 historyBuffer[tid].push_front(hb_entry); 1134 --- 296 unchanged lines hidden (view full) --- 1431{ 1432 typename std::list<RenameHistory>::iterator buf_it; 1433 1434 for (ThreadID tid = 0; tid < numThreads; tid++) { 1435 1436 buf_it = historyBuffer[tid].begin(); 1437 1438 while (buf_it != historyBuffer[tid].end()) { |
1439 cprintf("Seq num: %i\nArch reg[%s]: %i New phys reg:" 1440 " %i[%s] Old phys reg: %i[%s]\n", 1441 (*buf_it).instSeqNum, |
1442 RegClassStrings[(*buf_it).archReg.regClass], 1443 (*buf_it).archReg.regIdx, |
1444 (*buf_it).newPhysReg->regIdx, 1445 RegClassStrings[(*buf_it).newPhysReg->regClass], 1446 (*buf_it).prevPhysReg->regIdx, 1447 RegClassStrings[(*buf_it).prevPhysReg->regClass]); |
1448 1449 buf_it++; 1450 } 1451 } 1452} 1453 1454#endif//__CPU_O3_RENAME_IMPL_HH__ |