1/* 2 * Copyright (c) 2010-2012, 2014-2015 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 997 unchanged lines hidden (view full) --- 1006{ 1007 ThreadContext *tc = inst->tcBase(); 1008 RenameMap *map = renameMap[tid]; 1009 unsigned num_src_regs = inst->numSrcRegs(); 1010 1011 // Get the architectual register numbers from the source and 1012 // operands, and redirect them to the right physical register. 1013 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) { |
1014 RegId src_reg = inst->srcRegIdx(src_idx); 1015 RegIndex flat_src_reg; |
1016 PhysRegIndex renamed_reg; 1017 |
1018 switch (src_reg.regClass) { |
1019 case IntRegClass: |
1020 flat_src_reg = tc->flattenIntIndex(src_reg.regIdx); 1021 renamed_reg = map->lookupInt(flat_src_reg); |
1022 intRenameLookups++; 1023 break; 1024 1025 case FloatRegClass: |
1026 flat_src_reg = tc->flattenFloatIndex(src_reg.regIdx); 1027 renamed_reg = map->lookupFloat(flat_src_reg); |
1028 fpRenameLookups++; 1029 break; 1030 1031 case CCRegClass: |
1032 flat_src_reg = tc->flattenCCIndex(src_reg.regIdx); 1033 renamed_reg = map->lookupCC(flat_src_reg); |
1034 break; 1035 1036 case MiscRegClass: 1037 // misc regs don't get flattened |
1038 flat_src_reg = src_reg.regIdx; 1039 renamed_reg = map->lookupMisc(flat_src_reg); |
1040 break; 1041 1042 default: |
1043 panic("Invalid register class: %d.", src_reg.regClass); |
1044 } 1045 1046 DPRINTF(Rename, "[tid:%u]: Looking up %s arch reg %i (flattened %i), " |
1047 "got phys reg %i\n", tid, RegClassStrings[src_reg.regClass], 1048 (int)src_reg.regIdx, (int)flat_src_reg, (int)renamed_reg); |
1049 1050 inst->renameSrcReg(src_idx, renamed_reg); 1051 1052 // See if the register is ready or not. 1053 if (scoreboard->getReg(renamed_reg)) { 1054 DPRINTF(Rename, "[tid:%u]: Register %d is ready.\n", 1055 tid, renamed_reg); 1056 --- 12 unchanged lines hidden (view full) --- 1069DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid) 1070{ 1071 ThreadContext *tc = inst->tcBase(); 1072 RenameMap *map = renameMap[tid]; 1073 unsigned num_dest_regs = inst->numDestRegs(); 1074 1075 // Rename the destination registers. 1076 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) { |
1077 RegId dest_reg = inst->destRegIdx(dest_idx); 1078 RegIndex flat_dest_reg; |
1079 typename RenameMap::RenameInfo rename_result; 1080 |
1081 switch (dest_reg.regClass) { |
1082 case IntRegClass: |
1083 flat_dest_reg = tc->flattenIntIndex(dest_reg.regIdx); 1084 rename_result = map->renameInt(flat_dest_reg); |
1085 break; 1086 1087 case FloatRegClass: |
1088 flat_dest_reg = tc->flattenFloatIndex(dest_reg.regIdx); 1089 rename_result = map->renameFloat(flat_dest_reg); |
1090 break; 1091 1092 case CCRegClass: |
1093 flat_dest_reg = tc->flattenCCIndex(dest_reg.regIdx); 1094 rename_result = map->renameCC(flat_dest_reg); |
1095 break; 1096 1097 case MiscRegClass: 1098 // misc regs don't get flattened |
1099 flat_dest_reg = dest_reg.regIdx; 1100 rename_result = map->renameMisc(dest_reg.regIdx); |
1101 break; 1102 1103 default: |
1104 panic("Invalid register class: %d.", dest_reg.regClass); |
1105 } 1106 |
1107 RegId flat_uni_dest_reg(dest_reg.regClass, flat_dest_reg); 1108 |
1109 inst->flattenDestReg(dest_idx, flat_uni_dest_reg); 1110 1111 // Mark Scoreboard entry as not ready 1112 scoreboard->unsetReg(rename_result.first); 1113 1114 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical " |
1115 "reg %i.\n", tid, (int)flat_dest_reg, |
1116 (int)rename_result.first); 1117 1118 // Record the rename information so that a history can be kept. 1119 RenameHistory hb_entry(inst->seqNum, flat_uni_dest_reg, 1120 rename_result.first, 1121 rename_result.second); 1122 1123 historyBuffer[tid].push_front(hb_entry); --- 297 unchanged lines hidden (view full) --- 1421{ 1422 typename std::list<RenameHistory>::iterator buf_it; 1423 1424 for (ThreadID tid = 0; tid < numThreads; tid++) { 1425 1426 buf_it = historyBuffer[tid].begin(); 1427 1428 while (buf_it != historyBuffer[tid].end()) { |
1429 cprintf("Seq num: %i\nArch reg[%s]: %i New phys reg: %i Old phys " 1430 "reg: %i\n", (*buf_it).instSeqNum, 1431 RegClassStrings[(*buf_it).archReg.regClass], 1432 (*buf_it).archReg.regIdx, |
1433 (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg); 1434 1435 buf_it++; 1436 } 1437 } 1438} 1439 1440#endif//__CPU_O3_RENAME_IMPL_HH__ |