1/* 2 * Copyright (c) 2010-2012, 2014-2015 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 55 unchanged lines hidden (view full) --- 64 : cpu(_cpu), 65 iewToRenameDelay(params->iewToRenameDelay), 66 decodeToRenameDelay(params->decodeToRenameDelay), 67 commitToRenameDelay(params->commitToRenameDelay), 68 renameWidth(params->renameWidth), 69 commitWidth(params->commitWidth), 70 numThreads(params->numThreads), 71 maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs |
72 + params->numPhysCCRegs) |
73{ 74 if (renameWidth > Impl::MaxWidth) 75 fatal("renameWidth (%d) is larger than compiled limit (%d),\n" 76 "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 77 renameWidth, static_cast<int>(Impl::MaxWidth)); 78 79 // @todo: Make into a parameter. 80 skidBufferMax = (decodeToRenameDelay + 1) * params->decodeWidth; --- 549 unchanged lines hidden (view full) --- 630 631 DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with " 632 "PC %s.\n", tid, inst->seqNum, inst->pcState()); 633 634 // Check here to make sure there are enough destination registers 635 // to rename to. Otherwise block. 636 if (!renameMap[tid]->canRename(inst->numIntDestRegs(), 637 inst->numFPDestRegs(), |
638 inst->numCCDestRegs())) { |
639 DPRINTF(Rename, "Blocking due to lack of free " 640 "physical registers to rename to.\n"); 641 blockThisCycle = true; 642 insts_to_rename.push_front(inst); 643 ++renameFullRegistersEvents; 644 645 break; 646 } --- 364 unchanged lines hidden (view full) --- 1011 fpRenameLookups++; 1012 break; 1013 1014 case CCRegClass: 1015 flat_rel_src_reg = tc->flattenCCIndex(rel_src_reg); 1016 renamed_reg = map->lookupCC(flat_rel_src_reg); 1017 break; 1018 |
1019 case MiscRegClass: 1020 // misc regs don't get flattened 1021 flat_rel_src_reg = rel_src_reg; 1022 renamed_reg = map->lookupMisc(flat_rel_src_reg); 1023 break; 1024 1025 default: 1026 panic("Reg index is out of bound: %d.", src_reg); --- 50 unchanged lines hidden (view full) --- 1077 break; 1078 1079 case CCRegClass: 1080 flat_rel_dest_reg = tc->flattenCCIndex(rel_dest_reg); 1081 rename_result = map->renameCC(flat_rel_dest_reg); 1082 flat_uni_dest_reg = flat_rel_dest_reg + TheISA::CC_Reg_Base; 1083 break; 1084 |
1085 case MiscRegClass: 1086 // misc regs don't get flattened 1087 flat_rel_dest_reg = rel_dest_reg; 1088 rename_result = map->renameMisc(flat_rel_dest_reg); 1089 flat_uni_dest_reg = flat_rel_dest_reg + TheISA::Misc_Reg_Base; 1090 break; 1091 1092 default: --- 58 unchanged lines hidden (view full) --- 1151 return num_free; 1152} 1153 1154template <class Impl> 1155inline int 1156DefaultRename<Impl>::calcFreeLQEntries(ThreadID tid) 1157{ 1158 int num_free = freeEntries[tid].lqEntries - |
1159 (loadsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLQ); |
1160 DPRINTF(Rename, "calcFreeLQEntries: free lqEntries: %d, loadsInProgress: %d, " 1161 "loads dispatchedToLQ: %d\n", freeEntries[tid].lqEntries, 1162 loadsInProgress[tid], fromIEW->iewInfo[tid].dispatchedToLQ); 1163 return num_free; 1164} 1165 1166template <class Impl> 1167inline int 1168DefaultRename<Impl>::calcFreeSQEntries(ThreadID tid) 1169{ 1170 int num_free = freeEntries[tid].sqEntries - |
1171 (storesInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToSQ); |
1172 DPRINTF(Rename, "calcFreeSQEntries: free sqEntries: %d, storesInProgress: %d, " 1173 "stores dispatchedToSQ: %d\n", freeEntries[tid].sqEntries, 1174 storesInProgress[tid], fromIEW->iewInfo[tid].dispatchedToSQ); 1175 return num_free; 1176} 1177 1178template <class Impl> 1179unsigned --- 246 unchanged lines hidden --- |