874c874
< (*hb_it).instSeqNum > squashed_seq_num) {
---
> hb_it->instSeqNum > squashed_seq_num) {
878c878
< "number %i.\n", tid, (*hb_it).instSeqNum);
---
> "number %i.\n", tid, hb_it->instSeqNum);
880,882c880,889
< // Tell the rename map to set the architected register to the
< // previous physical register that it was renamed to.
< renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
---
> // Undo the rename mapping only if it was really a change.
> // Special regs that are not really renamed (like misc regs
> // and the zero reg) can be recognized because the new mapping
> // is the same as the old one. While it would be merely a
> // waste of time to update the rename table, we definitely
> // don't want to put these on the free list.
> if (hb_it->newPhysReg != hb_it->prevPhysReg) {
> // Tell the rename map to set the architected register to the
> // previous physical register that it was renamed to.
> renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
884,885c891,893
< // Put the renamed physical register back on the free list.
< freeList->addReg(hb_it->newPhysReg);
---
> // Put the renamed physical register back on the free list.
> freeList->addReg(hb_it->newPhysReg);
> }
921c929
< (*hb_it).instSeqNum <= inst_seq_num) {
---
> hb_it->instSeqNum <= inst_seq_num) {
925c933
< tid, (*hb_it).prevPhysReg, (*hb_it).instSeqNum);
---
> tid, hb_it->prevPhysReg, hb_it->instSeqNum);
927c935,941
< freeList->addReg((*hb_it).prevPhysReg);
---
> // Don't free special phys regs like misc and zero regs, which
> // can be recognized because the new mapping is the same as
> // the old one.
> if (hb_it->newPhysReg != hb_it->prevPhysReg) {
> freeList->addReg(hb_it->prevPhysReg);
> }
>
938,939c952,953
< assert(renameMap[tid] != 0);
<
---
> ThreadContext *tc = inst->tcBase();
> RenameMap *map = renameMap[tid];
943,944c957
< // destination operands, and redirect them to the right register.
< // Will need to mark dependencies though.
---
> // operands, and redirect them to the right physical register.
947,948c960,964
< RegIndex flat_src_reg = src_reg;
< switch (regIdxToClass(src_reg)) {
---
> RegIndex rel_src_reg;
> RegIndex flat_rel_src_reg;
> PhysRegIndex renamed_reg;
>
> switch (regIdxToClass(src_reg, &rel_src_reg)) {
950,952c966,968
< flat_src_reg = inst->tcBase()->flattenIntIndex(src_reg);
< DPRINTF(Rename, "Flattening index %d to %d.\n",
< (int)src_reg, (int)flat_src_reg);
---
> flat_rel_src_reg = tc->flattenIntIndex(rel_src_reg);
> renamed_reg = map->lookupInt(flat_rel_src_reg);
> intRenameLookups++;
956,960c972,974
< src_reg = src_reg - TheISA::FP_Reg_Base;
< flat_src_reg = inst->tcBase()->flattenFloatIndex(src_reg);
< DPRINTF(Rename, "Flattening index %d to %d.\n",
< (int)src_reg, (int)flat_src_reg);
< flat_src_reg += TheISA::NumIntRegs;
---
> flat_rel_src_reg = tc->flattenFloatIndex(rel_src_reg);
> renamed_reg = map->lookupFloat(flat_rel_src_reg);
> fpRenameLookups++;
964,967c978,980
< flat_src_reg = src_reg - TheISA::Misc_Reg_Base +
< TheISA::NumFloatRegs + TheISA::NumIntRegs;
< DPRINTF(Rename, "Adjusting reg index from %d to %d.\n",
< src_reg, flat_src_reg);
---
> // misc regs don't get flattened
> flat_rel_src_reg = rel_src_reg;
> renamed_reg = map->lookupMisc(flat_rel_src_reg);
974,976c987,989
< // Look up the source registers to get the phys. register they've
< // been renamed to, and set the sources to those registers.
< PhysRegIndex renamed_reg = renameMap[tid]->lookup(flat_src_reg);
---
> DPRINTF(Rename, "[tid:%u]: Looking up %s arch reg %i (flattened %i), "
> "got phys reg %i\n", tid, RegClassStrings[regIdxToClass(src_reg)],
> (int)src_reg, (int)flat_rel_src_reg, (int)renamed_reg);
978,981d990
< DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got "
< "physical reg %i.\n", tid, (int)flat_src_reg,
< (int)renamed_reg);
<
985c994
< if (scoreboard->getReg(renamed_reg) == true) {
---
> if (scoreboard->getReg(renamed_reg)) {
996d1004
< inst->isFloating() ? fpRenameLookups++ : intRenameLookups++;
1004,1005c1012,1013
< typename RenameMap::RenameInfo rename_result;
<
---
> ThreadContext *tc = inst->tcBase();
> RenameMap *map = renameMap[tid];
1011,1012c1019,1024
< RegIndex flat_dest_reg = dest_reg;
< switch (regIdxToClass(dest_reg)) {
---
> RegIndex rel_dest_reg;
> RegIndex flat_rel_dest_reg;
> RegIndex flat_uni_dest_reg;
> typename RenameMap::RenameInfo rename_result;
>
> switch (regIdxToClass(dest_reg, &rel_dest_reg)) {
1014,1017c1026,1028
< // Integer registers are flattened.
< flat_dest_reg = inst->tcBase()->flattenIntIndex(dest_reg);
< DPRINTF(Rename, "Flattening index %d to %d.\n",
< (int)dest_reg, (int)flat_dest_reg);
---
> flat_rel_dest_reg = tc->flattenIntIndex(rel_dest_reg);
> rename_result = map->renameInt(flat_rel_dest_reg);
> flat_uni_dest_reg = flat_rel_dest_reg; // 1:1 mapping
1021,1025c1032,1034
< dest_reg = dest_reg - TheISA::FP_Reg_Base;
< flat_dest_reg = inst->tcBase()->flattenFloatIndex(dest_reg);
< DPRINTF(Rename, "Flattening index %d to %d.\n",
< (int)dest_reg, (int)flat_dest_reg);
< flat_dest_reg += TheISA::NumIntRegs;
---
> flat_rel_dest_reg = tc->flattenFloatIndex(rel_dest_reg);
> rename_result = map->renameFloat(flat_rel_dest_reg);
> flat_uni_dest_reg = flat_rel_dest_reg + TheISA::FP_Reg_Base;
1029,1034c1038,1041
< // Floating point and Miscellaneous registers need their indexes
< // adjusted to account for the expanded number of flattened int regs.
< flat_dest_reg = dest_reg - TheISA::Misc_Reg_Base +
< TheISA::NumIntRegs + TheISA::NumFloatRegs;
< DPRINTF(Rename, "Adjusting reg index from %d to %d.\n",
< dest_reg, flat_dest_reg);
---
> // misc regs don't get flattened
> flat_rel_dest_reg = rel_dest_reg;
> rename_result = map->renameMisc(flat_rel_dest_reg);
> flat_uni_dest_reg = flat_rel_dest_reg + TheISA::Misc_Reg_Base;
1041c1048
< inst->flattenDestReg(dest_idx, flat_dest_reg);
---
> inst->flattenDestReg(dest_idx, flat_uni_dest_reg);
1043,1047c1050
< // Get the physical register that the destination will be
< // renamed to.
< rename_result = renameMap[tid]->rename(flat_dest_reg);
<
< //Mark Scoreboard entry as not ready
---
> // Mark Scoreboard entry as not ready
1051c1054
< "reg %i.\n", tid, (int)flat_dest_reg,
---
> "reg %i.\n", tid, (int)flat_rel_dest_reg,
1055c1058
< RenameHistory hb_entry(inst->seqNum, flat_dest_reg,
---
> RenameHistory hb_entry(inst->seqNum, flat_uni_dest_reg,
< (*hb_it).instSeqNum > squashed_seq_num) {
---
> hb_it->instSeqNum > squashed_seq_num) {
878c878
< "number %i.\n", tid, (*hb_it).instSeqNum);
---
> "number %i.\n", tid, hb_it->instSeqNum);
880,882c880,889
< // Tell the rename map to set the architected register to the
< // previous physical register that it was renamed to.
< renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
---
> // Undo the rename mapping only if it was really a change.
> // Special regs that are not really renamed (like misc regs
> // and the zero reg) can be recognized because the new mapping
> // is the same as the old one. While it would be merely a
> // waste of time to update the rename table, we definitely
> // don't want to put these on the free list.
> if (hb_it->newPhysReg != hb_it->prevPhysReg) {
> // Tell the rename map to set the architected register to the
> // previous physical register that it was renamed to.
> renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
884,885c891,893
< // Put the renamed physical register back on the free list.
< freeList->addReg(hb_it->newPhysReg);
---
> // Put the renamed physical register back on the free list.
> freeList->addReg(hb_it->newPhysReg);
> }
921c929
< (*hb_it).instSeqNum <= inst_seq_num) {
---
> hb_it->instSeqNum <= inst_seq_num) {
925c933
< tid, (*hb_it).prevPhysReg, (*hb_it).instSeqNum);
---
> tid, hb_it->prevPhysReg, hb_it->instSeqNum);
927c935,941
< freeList->addReg((*hb_it).prevPhysReg);
---
> // Don't free special phys regs like misc and zero regs, which
> // can be recognized because the new mapping is the same as
> // the old one.
> if (hb_it->newPhysReg != hb_it->prevPhysReg) {
> freeList->addReg(hb_it->prevPhysReg);
> }
>
938,939c952,953
< assert(renameMap[tid] != 0);
<
---
> ThreadContext *tc = inst->tcBase();
> RenameMap *map = renameMap[tid];
943,944c957
< // destination operands, and redirect them to the right register.
< // Will need to mark dependencies though.
---
> // operands, and redirect them to the right physical register.
947,948c960,964
< RegIndex flat_src_reg = src_reg;
< switch (regIdxToClass(src_reg)) {
---
> RegIndex rel_src_reg;
> RegIndex flat_rel_src_reg;
> PhysRegIndex renamed_reg;
>
> switch (regIdxToClass(src_reg, &rel_src_reg)) {
950,952c966,968
< flat_src_reg = inst->tcBase()->flattenIntIndex(src_reg);
< DPRINTF(Rename, "Flattening index %d to %d.\n",
< (int)src_reg, (int)flat_src_reg);
---
> flat_rel_src_reg = tc->flattenIntIndex(rel_src_reg);
> renamed_reg = map->lookupInt(flat_rel_src_reg);
> intRenameLookups++;
956,960c972,974
< src_reg = src_reg - TheISA::FP_Reg_Base;
< flat_src_reg = inst->tcBase()->flattenFloatIndex(src_reg);
< DPRINTF(Rename, "Flattening index %d to %d.\n",
< (int)src_reg, (int)flat_src_reg);
< flat_src_reg += TheISA::NumIntRegs;
---
> flat_rel_src_reg = tc->flattenFloatIndex(rel_src_reg);
> renamed_reg = map->lookupFloat(flat_rel_src_reg);
> fpRenameLookups++;
964,967c978,980
< flat_src_reg = src_reg - TheISA::Misc_Reg_Base +
< TheISA::NumFloatRegs + TheISA::NumIntRegs;
< DPRINTF(Rename, "Adjusting reg index from %d to %d.\n",
< src_reg, flat_src_reg);
---
> // misc regs don't get flattened
> flat_rel_src_reg = rel_src_reg;
> renamed_reg = map->lookupMisc(flat_rel_src_reg);
974,976c987,989
< // Look up the source registers to get the phys. register they've
< // been renamed to, and set the sources to those registers.
< PhysRegIndex renamed_reg = renameMap[tid]->lookup(flat_src_reg);
---
> DPRINTF(Rename, "[tid:%u]: Looking up %s arch reg %i (flattened %i), "
> "got phys reg %i\n", tid, RegClassStrings[regIdxToClass(src_reg)],
> (int)src_reg, (int)flat_rel_src_reg, (int)renamed_reg);
978,981d990
< DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got "
< "physical reg %i.\n", tid, (int)flat_src_reg,
< (int)renamed_reg);
<
985c994
< if (scoreboard->getReg(renamed_reg) == true) {
---
> if (scoreboard->getReg(renamed_reg)) {
996d1004
< inst->isFloating() ? fpRenameLookups++ : intRenameLookups++;
1004,1005c1012,1013
< typename RenameMap::RenameInfo rename_result;
<
---
> ThreadContext *tc = inst->tcBase();
> RenameMap *map = renameMap[tid];
1011,1012c1019,1024
< RegIndex flat_dest_reg = dest_reg;
< switch (regIdxToClass(dest_reg)) {
---
> RegIndex rel_dest_reg;
> RegIndex flat_rel_dest_reg;
> RegIndex flat_uni_dest_reg;
> typename RenameMap::RenameInfo rename_result;
>
> switch (regIdxToClass(dest_reg, &rel_dest_reg)) {
1014,1017c1026,1028
< // Integer registers are flattened.
< flat_dest_reg = inst->tcBase()->flattenIntIndex(dest_reg);
< DPRINTF(Rename, "Flattening index %d to %d.\n",
< (int)dest_reg, (int)flat_dest_reg);
---
> flat_rel_dest_reg = tc->flattenIntIndex(rel_dest_reg);
> rename_result = map->renameInt(flat_rel_dest_reg);
> flat_uni_dest_reg = flat_rel_dest_reg; // 1:1 mapping
1021,1025c1032,1034
< dest_reg = dest_reg - TheISA::FP_Reg_Base;
< flat_dest_reg = inst->tcBase()->flattenFloatIndex(dest_reg);
< DPRINTF(Rename, "Flattening index %d to %d.\n",
< (int)dest_reg, (int)flat_dest_reg);
< flat_dest_reg += TheISA::NumIntRegs;
---
> flat_rel_dest_reg = tc->flattenFloatIndex(rel_dest_reg);
> rename_result = map->renameFloat(flat_rel_dest_reg);
> flat_uni_dest_reg = flat_rel_dest_reg + TheISA::FP_Reg_Base;
1029,1034c1038,1041
< // Floating point and Miscellaneous registers need their indexes
< // adjusted to account for the expanded number of flattened int regs.
< flat_dest_reg = dest_reg - TheISA::Misc_Reg_Base +
< TheISA::NumIntRegs + TheISA::NumFloatRegs;
< DPRINTF(Rename, "Adjusting reg index from %d to %d.\n",
< dest_reg, flat_dest_reg);
---
> // misc regs don't get flattened
> flat_rel_dest_reg = rel_dest_reg;
> rename_result = map->renameMisc(flat_rel_dest_reg);
> flat_uni_dest_reg = flat_rel_dest_reg + TheISA::Misc_Reg_Base;
1041c1048
< inst->flattenDestReg(dest_idx, flat_dest_reg);
---
> inst->flattenDestReg(dest_idx, flat_uni_dest_reg);
1043,1047c1050
< // Get the physical register that the destination will be
< // renamed to.
< rename_result = renameMap[tid]->rename(flat_dest_reg);
<
< //Mark Scoreboard entry as not ready
---
> // Mark Scoreboard entry as not ready
1051c1054
< "reg %i.\n", tid, (int)flat_dest_reg,
---
> "reg %i.\n", tid, (int)flat_rel_dest_reg,
1055c1058
< RenameHistory hb_entry(inst->seqNum, flat_dest_reg,
---
> RenameHistory hb_entry(inst->seqNum, flat_uni_dest_reg,