359,375c359
< // insts in them. Since we support multiple ISAs, we cant just:
< // "insts[tid].clear();" or "skidBuffer[tid].clear()" since there is
< // a possible delay slot inst for different architectures
< // insts[tid].clear();
< #if ISA_HAS_DELAY_SLOT
< DPRINTF(Rename, "[tid:%i] Squashing incoming decode instructions until "
< "[sn:%i].\n",tid, squash_seq_num);
< ListIt ilist_it = insts[tid].begin();
< while (ilist_it != insts[tid].end()) {
< if ((*ilist_it)->seqNum > squash_seq_num) {
< (*ilist_it)->setSquashed();
< DPRINTF(Rename, "Squashing incoming decode instruction, "
< "[tid:%i] [sn:%i] PC %08p.\n", tid, (*ilist_it)->seqNum, (*ilist_it)->PC);
< }
< ilist_it++;
< }
< #else
---
> // insts in them.
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< #endif
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< // See comments above.
< // skidBuffer[tid].clear();
< #if ISA_HAS_DELAY_SLOT
< DPRINTF(Rename, "[tid:%i] Squashing incoming skidbuffer instructions "
< "until [sn:%i].\n", tid, squash_seq_num);
< ListIt slist_it = skidBuffer[tid].begin();
< while (slist_it != skidBuffer[tid].end()) {
< if ((*slist_it)->seqNum > squash_seq_num) {
< (*slist_it)->setSquashed();
< DPRINTF(Rename, "Squashing skidbuffer instruction, [tid:%i] [sn:%i]"
< "PC %08p.\n", tid, (*slist_it)->seqNum, (*slist_it)->PC);
< }
< slist_it++;
< }
< resumeUnblocking = (skidBuffer[tid].size() != 0);
< DPRINTF(Rename, "Resume unblocking set to %s\n",
< resumeUnblocking ? "true" : "false");
< #else
399c364
< #endif
---
>
779d743
< #if !ISA_HAS_DELAY_SLOT
783d746
< #endif
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< #if ISA_HAS_DELAY_SLOT
< InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
< #else
< InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].doneSeqNum;
< #endif
---
> squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
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< squash(squashed_seq_num, tid);
<