33a34,35
> #include "arch/isa_traits.hh"
> #include "arch/regfile.hh"
43a46,47
> resumeSerialize(false),
> resumeUnblocking(false),
335,337c339
< renameStatus[tid] == Unblocking ||
< renameStatus[tid] == SerializeStall) {
<
---
> renameStatus[tid] == Unblocking) {
339a342
> resumeSerialize = false;
340a344,354
> } else if (renameStatus[tid] == SerializeStall) {
> if (serializeInst[tid]->seqNum <= squash_seq_num) {
> DPRINTF(Rename, "Rename will resume serializing after squash\n");
> resumeSerialize = true;
> assert(serializeInst[tid]);
> } else {
> resumeSerialize = false;
> toDecode->renameUnblock[tid] = 1;
>
> serializeInst[tid] = NULL;
> }
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> resumeUnblocking = (skidBuffer[tid].size() != 0);
> DPRINTF(Rename, "Resume unblocking set to %s\n",
> resumeUnblocking ? "true" : "false");
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> // If we are currently in SerializeStall and resumeSerialize
> // was set, then that means that we are resuming serializing
> // this cycle. Tell the previous stages to block.
> if (resumeSerialize) {
> resumeSerialize = false;
> block(tid);
> toDecode->renameUnblock[tid] = false;
> }
> } else if (renameStatus[tid] == Unblocking) {
> if (resumeUnblocking) {
> block(tid);
> resumeUnblocking = false;
> toDecode->renameUnblock[tid] = false;
> }
743a775,783
> {
> typename InstQueue::iterator it;
> warn("Skidbuffer contents:\n");
> for(it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++)
> {
> warn("[tid:%u]: %s [sn:%i].\n", tid,
> (*it)->staticInst->disassemble(inst->readPC()),
> (*it)->seqNum);
> }
744a785
> }
833c874,877
< if (renameStatus[tid] != Unblocking) {
---
> // If resumeUnblocking is set, we unblocked during the squash,
> // but now we're have unblocking status. We need to tell earlier
> // stages to block.
> if (resumeUnblocking || renameStatus[tid] != Unblocking) {
965a1010,1015
> RegIndex flat_src_reg = src_reg;
> if (src_reg < TheISA::FP_Base_DepTag) {
> flat_src_reg = TheISA::flattenIntIndex(inst->tcBase(), src_reg);
> DPRINTF(Rename, "Flattening index %d to %d.\n", (int)src_reg, (int)flat_src_reg);
> }
> inst->flattenSrcReg(src_idx, flat_src_reg);
969c1019
< PhysRegIndex renamed_reg = renameMap[tid]->lookup(src_reg);
---
> PhysRegIndex renamed_reg = renameMap[tid]->lookup(flat_src_reg);
972c1022
< "physical reg %i.\n", tid, (int)src_reg,
---
> "physical reg %i.\n", tid, (int)flat_src_reg,
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> RegIndex flat_dest_reg = dest_reg;
> if (dest_reg < TheISA::FP_Base_DepTag) {
> flat_dest_reg = TheISA::flattenIntIndex(inst->tcBase(), dest_reg);
> DPRINTF(Rename, "Flattening index %d to %d.\n", (int)dest_reg, (int)flat_dest_reg);
> }
999a1055,1056
> inst->flattenDestReg(dest_idx, flat_dest_reg);
>
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< rename_result = renameMap[tid]->rename(dest_reg);
---
> rename_result = renameMap[tid]->rename(flat_dest_reg);
1008c1065
< "reg %i.\n", tid, (int)dest_reg,
---
> "reg %i.\n", tid, (int)flat_dest_reg,
1012c1069
< RenameHistory hb_entry(inst->seqNum, dest_reg,
---
> RenameHistory hb_entry(inst->seqNum, flat_dest_reg,
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< DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n",
< tid);
---
> if (resumeSerialize) {
> DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n",
> tid);
1239c1297,1306
< renameStatus[tid] = Running;
---
> renameStatus[tid] = SerializeStall;
> return true;
> } else if (resumeUnblocking) {
> DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n",
> tid);
> renameStatus[tid] = Unblocking;
> return true;
> } else {
> DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n",
> tid);
1241c1308,1310
< return false;
---
> renameStatus[tid] = Running;
> return false;
> }