rename_impl.hh (9944:4ff1c5c6dcbc) rename_impl.hh (10172:790a214be1f4)
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 * Korey Sewell
43 */
44
45#ifndef __CPU_O3_RENAME_IMPL_HH__
46#define __CPU_O3_RENAME_IMPL_HH__
47
48#include <list>
49
50#include "arch/isa_traits.hh"
51#include "arch/registers.hh"
52#include "config/the_isa.hh"
53#include "cpu/o3/rename.hh"
54#include "cpu/reg_class.hh"
55#include "debug/Activity.hh"
56#include "debug/Rename.hh"
57#include "debug/O3PipeView.hh"
58#include "params/DerivO3CPU.hh"
59
60using namespace std;
61
62template <class Impl>
63DefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params)
64 : cpu(_cpu),
65 iewToRenameDelay(params->iewToRenameDelay),
66 decodeToRenameDelay(params->decodeToRenameDelay),
67 commitToRenameDelay(params->commitToRenameDelay),
68 renameWidth(params->renameWidth),
69 commitWidth(params->commitWidth),
70 numThreads(params->numThreads),
71 maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs
72 + params->numPhysCCRegs)
73{
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 * Korey Sewell
43 */
44
45#ifndef __CPU_O3_RENAME_IMPL_HH__
46#define __CPU_O3_RENAME_IMPL_HH__
47
48#include <list>
49
50#include "arch/isa_traits.hh"
51#include "arch/registers.hh"
52#include "config/the_isa.hh"
53#include "cpu/o3/rename.hh"
54#include "cpu/reg_class.hh"
55#include "debug/Activity.hh"
56#include "debug/Rename.hh"
57#include "debug/O3PipeView.hh"
58#include "params/DerivO3CPU.hh"
59
60using namespace std;
61
62template <class Impl>
63DefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params)
64 : cpu(_cpu),
65 iewToRenameDelay(params->iewToRenameDelay),
66 decodeToRenameDelay(params->decodeToRenameDelay),
67 commitToRenameDelay(params->commitToRenameDelay),
68 renameWidth(params->renameWidth),
69 commitWidth(params->commitWidth),
70 numThreads(params->numThreads),
71 maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs
72 + params->numPhysCCRegs)
73{
74 if (renameWidth > Impl::MaxWidth)
75 fatal("renameWidth (%d) is larger than compiled limit (%d),\n"
76 "\tincrease MaxWidth in src/cpu/o3/impl.hh\n",
77 renameWidth, static_cast<int>(Impl::MaxWidth));
78
74 // @todo: Make into a parameter.
75 skidBufferMax = (2 * (decodeToRenameDelay * params->decodeWidth)) + renameWidth;
76}
77
78template <class Impl>
79std::string
80DefaultRename<Impl>::name() const
81{
82 return cpu->name() + ".rename";
83}
84
85template <class Impl>
86void
87DefaultRename<Impl>::regStats()
88{
89 renameSquashCycles
90 .name(name() + ".SquashCycles")
91 .desc("Number of cycles rename is squashing")
92 .prereq(renameSquashCycles);
93 renameIdleCycles
94 .name(name() + ".IdleCycles")
95 .desc("Number of cycles rename is idle")
96 .prereq(renameIdleCycles);
97 renameBlockCycles
98 .name(name() + ".BlockCycles")
99 .desc("Number of cycles rename is blocking")
100 .prereq(renameBlockCycles);
101 renameSerializeStallCycles
102 .name(name() + ".serializeStallCycles")
103 .desc("count of cycles rename stalled for serializing inst")
104 .flags(Stats::total);
105 renameRunCycles
106 .name(name() + ".RunCycles")
107 .desc("Number of cycles rename is running")
108 .prereq(renameIdleCycles);
109 renameUnblockCycles
110 .name(name() + ".UnblockCycles")
111 .desc("Number of cycles rename is unblocking")
112 .prereq(renameUnblockCycles);
113 renameRenamedInsts
114 .name(name() + ".RenamedInsts")
115 .desc("Number of instructions processed by rename")
116 .prereq(renameRenamedInsts);
117 renameSquashedInsts
118 .name(name() + ".SquashedInsts")
119 .desc("Number of squashed instructions processed by rename")
120 .prereq(renameSquashedInsts);
121 renameROBFullEvents
122 .name(name() + ".ROBFullEvents")
123 .desc("Number of times rename has blocked due to ROB full")
124 .prereq(renameROBFullEvents);
125 renameIQFullEvents
126 .name(name() + ".IQFullEvents")
127 .desc("Number of times rename has blocked due to IQ full")
128 .prereq(renameIQFullEvents);
129 renameLSQFullEvents
130 .name(name() + ".LSQFullEvents")
131 .desc("Number of times rename has blocked due to LSQ full")
132 .prereq(renameLSQFullEvents);
133 renameFullRegistersEvents
134 .name(name() + ".FullRegisterEvents")
135 .desc("Number of times there has been no free registers")
136 .prereq(renameFullRegistersEvents);
137 renameRenamedOperands
138 .name(name() + ".RenamedOperands")
139 .desc("Number of destination operands rename has renamed")
140 .prereq(renameRenamedOperands);
141 renameRenameLookups
142 .name(name() + ".RenameLookups")
143 .desc("Number of register rename lookups that rename has made")
144 .prereq(renameRenameLookups);
145 renameCommittedMaps
146 .name(name() + ".CommittedMaps")
147 .desc("Number of HB maps that are committed")
148 .prereq(renameCommittedMaps);
149 renameUndoneMaps
150 .name(name() + ".UndoneMaps")
151 .desc("Number of HB maps that are undone due to squashing")
152 .prereq(renameUndoneMaps);
153 renamedSerializing
154 .name(name() + ".serializingInsts")
155 .desc("count of serializing insts renamed")
156 .flags(Stats::total)
157 ;
158 renamedTempSerializing
159 .name(name() + ".tempSerializingInsts")
160 .desc("count of temporary serializing insts renamed")
161 .flags(Stats::total)
162 ;
163 renameSkidInsts
164 .name(name() + ".skidInsts")
165 .desc("count of insts added to the skid buffer")
166 .flags(Stats::total)
167 ;
168 intRenameLookups
169 .name(name() + ".int_rename_lookups")
170 .desc("Number of integer rename lookups")
171 .prereq(intRenameLookups);
172 fpRenameLookups
173 .name(name() + ".fp_rename_lookups")
174 .desc("Number of floating rename lookups")
175 .prereq(fpRenameLookups);
176}
177
178template <class Impl>
179void
180DefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
181{
182 timeBuffer = tb_ptr;
183
184 // Setup wire to read information from time buffer, from IEW stage.
185 fromIEW = timeBuffer->getWire(-iewToRenameDelay);
186
187 // Setup wire to read infromation from time buffer, from commit stage.
188 fromCommit = timeBuffer->getWire(-commitToRenameDelay);
189
190 // Setup wire to write information to previous stages.
191 toDecode = timeBuffer->getWire(0);
192}
193
194template <class Impl>
195void
196DefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
197{
198 renameQueue = rq_ptr;
199
200 // Setup wire to write information to future stages.
201 toIEW = renameQueue->getWire(0);
202}
203
204template <class Impl>
205void
206DefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
207{
208 decodeQueue = dq_ptr;
209
210 // Setup wire to get information from decode.
211 fromDecode = decodeQueue->getWire(-decodeToRenameDelay);
212}
213
214template <class Impl>
215void
216DefaultRename<Impl>::startupStage()
217{
218 resetStage();
219}
220
221template <class Impl>
222void
223DefaultRename<Impl>::resetStage()
224{
225 _status = Inactive;
226
227 resumeSerialize = false;
228 resumeUnblocking = false;
229
230 // Grab the number of free entries directly from the stages.
231 for (ThreadID tid = 0; tid < numThreads; tid++) {
232 renameStatus[tid] = Idle;
233
234 freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid);
235 freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid);
236 freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid);
237 emptyROB[tid] = true;
238
239 stalls[tid].iew = false;
240 stalls[tid].commit = false;
241 serializeInst[tid] = NULL;
242
243 instsInProgress[tid] = 0;
244
245 serializeOnNextInst[tid] = false;
246 }
247}
248
249template<class Impl>
250void
251DefaultRename<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
252{
253 activeThreads = at_ptr;
254}
255
256
257template <class Impl>
258void
259DefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[])
260{
261 for (ThreadID tid = 0; tid < numThreads; tid++)
262 renameMap[tid] = &rm_ptr[tid];
263}
264
265template <class Impl>
266void
267DefaultRename<Impl>::setFreeList(FreeList *fl_ptr)
268{
269 freeList = fl_ptr;
270}
271
272template<class Impl>
273void
274DefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard)
275{
276 scoreboard = _scoreboard;
277}
278
279template <class Impl>
280bool
281DefaultRename<Impl>::isDrained() const
282{
283 for (ThreadID tid = 0; tid < numThreads; tid++) {
284 if (instsInProgress[tid] != 0 ||
285 !historyBuffer[tid].empty() ||
286 !skidBuffer[tid].empty() ||
287 !insts[tid].empty())
288 return false;
289 }
290 return true;
291}
292
293template <class Impl>
294void
295DefaultRename<Impl>::takeOverFrom()
296{
297 resetStage();
298}
299
300template <class Impl>
301void
302DefaultRename<Impl>::drainSanityCheck() const
303{
304 for (ThreadID tid = 0; tid < numThreads; tid++) {
305 assert(historyBuffer[tid].empty());
306 assert(insts[tid].empty());
307 assert(skidBuffer[tid].empty());
308 assert(instsInProgress[tid] == 0);
309 }
310}
311
312template <class Impl>
313void
314DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, ThreadID tid)
315{
316 DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid);
317
318 // Clear the stall signal if rename was blocked or unblocking before.
319 // If it still needs to block, the blocking should happen the next
320 // cycle and there should be space to hold everything due to the squash.
321 if (renameStatus[tid] == Blocked ||
322 renameStatus[tid] == Unblocking) {
323 toDecode->renameUnblock[tid] = 1;
324
325 resumeSerialize = false;
326 serializeInst[tid] = NULL;
327 } else if (renameStatus[tid] == SerializeStall) {
328 if (serializeInst[tid]->seqNum <= squash_seq_num) {
329 DPRINTF(Rename, "Rename will resume serializing after squash\n");
330 resumeSerialize = true;
331 assert(serializeInst[tid]);
332 } else {
333 resumeSerialize = false;
334 toDecode->renameUnblock[tid] = 1;
335
336 serializeInst[tid] = NULL;
337 }
338 }
339
340 // Set the status to Squashing.
341 renameStatus[tid] = Squashing;
342
343 // Squash any instructions from decode.
344 for (int i=0; i<fromDecode->size; i++) {
345 if (fromDecode->insts[i]->threadNumber == tid &&
346 fromDecode->insts[i]->seqNum > squash_seq_num) {
347 fromDecode->insts[i]->setSquashed();
348 wroteToTimeBuffer = true;
349 }
350
351 }
352
353 // Clear the instruction list and skid buffer in case they have any
354 // insts in them.
355 insts[tid].clear();
356
357 // Clear the skid buffer in case it has any data in it.
358 skidBuffer[tid].clear();
359
360 doSquash(squash_seq_num, tid);
361}
362
363template <class Impl>
364void
365DefaultRename<Impl>::tick()
366{
367 wroteToTimeBuffer = false;
368
369 blockThisCycle = false;
370
371 bool status_change = false;
372
373 toIEWIndex = 0;
374
375 sortInsts();
376
377 list<ThreadID>::iterator threads = activeThreads->begin();
378 list<ThreadID>::iterator end = activeThreads->end();
379
380 // Check stall and squash signals.
381 while (threads != end) {
382 ThreadID tid = *threads++;
383
384 DPRINTF(Rename, "Processing [tid:%i]\n", tid);
385
386 status_change = checkSignalsAndUpdate(tid) || status_change;
387
388 rename(status_change, tid);
389 }
390
391 if (status_change) {
392 updateStatus();
393 }
394
395 if (wroteToTimeBuffer) {
396 DPRINTF(Activity, "Activity this cycle.\n");
397 cpu->activityThisCycle();
398 }
399
400 threads = activeThreads->begin();
401
402 while (threads != end) {
403 ThreadID tid = *threads++;
404
405 // If we committed this cycle then doneSeqNum will be > 0
406 if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
407 !fromCommit->commitInfo[tid].squash &&
408 renameStatus[tid] != Squashing) {
409
410 removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum,
411 tid);
412 }
413 }
414
415 // @todo: make into updateProgress function
416 for (ThreadID tid = 0; tid < numThreads; tid++) {
417 instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched;
418
419 assert(instsInProgress[tid] >=0);
420 }
421
422}
423
424template<class Impl>
425void
426DefaultRename<Impl>::rename(bool &status_change, ThreadID tid)
427{
428 // If status is Running or idle,
429 // call renameInsts()
430 // If status is Unblocking,
431 // buffer any instructions coming from decode
432 // continue trying to empty skid buffer
433 // check if stall conditions have passed
434
435 if (renameStatus[tid] == Blocked) {
436 ++renameBlockCycles;
437 } else if (renameStatus[tid] == Squashing) {
438 ++renameSquashCycles;
439 } else if (renameStatus[tid] == SerializeStall) {
440 ++renameSerializeStallCycles;
441 // If we are currently in SerializeStall and resumeSerialize
442 // was set, then that means that we are resuming serializing
443 // this cycle. Tell the previous stages to block.
444 if (resumeSerialize) {
445 resumeSerialize = false;
446 block(tid);
447 toDecode->renameUnblock[tid] = false;
448 }
449 } else if (renameStatus[tid] == Unblocking) {
450 if (resumeUnblocking) {
451 block(tid);
452 resumeUnblocking = false;
453 toDecode->renameUnblock[tid] = false;
454 }
455 }
456
457 if (renameStatus[tid] == Running ||
458 renameStatus[tid] == Idle) {
459 DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run "
460 "stage.\n", tid);
461
462 renameInsts(tid);
463 } else if (renameStatus[tid] == Unblocking) {
464 renameInsts(tid);
465
466 if (validInsts()) {
467 // Add the current inputs to the skid buffer so they can be
468 // reprocessed when this stage unblocks.
469 skidInsert(tid);
470 }
471
472 // If we switched over to blocking, then there's a potential for
473 // an overall status change.
474 status_change = unblock(tid) || status_change || blockThisCycle;
475 }
476}
477
478template <class Impl>
479void
480DefaultRename<Impl>::renameInsts(ThreadID tid)
481{
482 // Instructions can be either in the skid buffer or the queue of
483 // instructions coming from decode, depending on the status.
484 int insts_available = renameStatus[tid] == Unblocking ?
485 skidBuffer[tid].size() : insts[tid].size();
486
487 // Check the decode queue to see if instructions are available.
488 // If there are no available instructions to rename, then do nothing.
489 if (insts_available == 0) {
490 DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n",
491 tid);
492 // Should I change status to idle?
493 ++renameIdleCycles;
494 return;
495 } else if (renameStatus[tid] == Unblocking) {
496 ++renameUnblockCycles;
497 } else if (renameStatus[tid] == Running) {
498 ++renameRunCycles;
499 }
500
501 DynInstPtr inst;
502
503 // Will have to do a different calculation for the number of free
504 // entries.
505 int free_rob_entries = calcFreeROBEntries(tid);
506 int free_iq_entries = calcFreeIQEntries(tid);
507 int free_lsq_entries = calcFreeLSQEntries(tid);
508 int min_free_entries = free_rob_entries;
509
510 FullSource source = ROB;
511
512 if (free_iq_entries < min_free_entries) {
513 min_free_entries = free_iq_entries;
514 source = IQ;
515 }
516
517 if (free_lsq_entries < min_free_entries) {
518 min_free_entries = free_lsq_entries;
519 source = LSQ;
520 }
521
522 // Check if there's any space left.
523 if (min_free_entries <= 0) {
524 DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ "
525 "entries.\n"
526 "ROB has %i free entries.\n"
527 "IQ has %i free entries.\n"
528 "LSQ has %i free entries.\n",
529 tid,
530 free_rob_entries,
531 free_iq_entries,
532 free_lsq_entries);
533
534 blockThisCycle = true;
535
536 block(tid);
537
538 incrFullStat(source);
539
540 return;
541 } else if (min_free_entries < insts_available) {
542 DPRINTF(Rename, "[tid:%u]: Will have to block this cycle."
543 "%i insts available, but only %i insts can be "
544 "renamed due to ROB/IQ/LSQ limits.\n",
545 tid, insts_available, min_free_entries);
546
547 insts_available = min_free_entries;
548
549 blockThisCycle = true;
550
551 incrFullStat(source);
552 }
553
554 InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ?
555 skidBuffer[tid] : insts[tid];
556
557 DPRINTF(Rename, "[tid:%u]: %i available instructions to "
558 "send iew.\n", tid, insts_available);
559
560 DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts "
561 "dispatched to IQ last cycle.\n",
562 tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched);
563
564 // Handle serializing the next instruction if necessary.
565 if (serializeOnNextInst[tid]) {
566 if (emptyROB[tid] && instsInProgress[tid] == 0) {
567 // ROB already empty; no need to serialize.
568 serializeOnNextInst[tid] = false;
569 } else if (!insts_to_rename.empty()) {
570 insts_to_rename.front()->setSerializeBefore();
571 }
572 }
573
574 int renamed_insts = 0;
575
576 while (insts_available > 0 && toIEWIndex < renameWidth) {
577 DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid);
578
579 assert(!insts_to_rename.empty());
580
581 inst = insts_to_rename.front();
582
583 insts_to_rename.pop_front();
584
585 if (renameStatus[tid] == Unblocking) {
586 DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%s from rename "
587 "skidBuffer\n", tid, inst->seqNum, inst->pcState());
588 }
589
590 if (inst->isSquashed()) {
591 DPRINTF(Rename, "[tid:%u]: instruction %i with PC %s is "
592 "squashed, skipping.\n", tid, inst->seqNum,
593 inst->pcState());
594
595 ++renameSquashedInsts;
596
597 // Decrement how many instructions are available.
598 --insts_available;
599
600 continue;
601 }
602
603 DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with "
604 "PC %s.\n", tid, inst->seqNum, inst->pcState());
605
606 // Check here to make sure there are enough destination registers
607 // to rename to. Otherwise block.
608 if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) {
609 DPRINTF(Rename, "Blocking due to lack of free "
610 "physical registers to rename to.\n");
611 blockThisCycle = true;
612 insts_to_rename.push_front(inst);
613 ++renameFullRegistersEvents;
614
615 break;
616 }
617
618 // Handle serializeAfter/serializeBefore instructions.
619 // serializeAfter marks the next instruction as serializeBefore.
620 // serializeBefore makes the instruction wait in rename until the ROB
621 // is empty.
622
623 // In this model, IPR accesses are serialize before
624 // instructions, and store conditionals are serialize after
625 // instructions. This is mainly due to lack of support for
626 // out-of-order operations of either of those classes of
627 // instructions.
628 if ((inst->isIprAccess() || inst->isSerializeBefore()) &&
629 !inst->isSerializeHandled()) {
630 DPRINTF(Rename, "Serialize before instruction encountered.\n");
631
632 if (!inst->isTempSerializeBefore()) {
633 renamedSerializing++;
634 inst->setSerializeHandled();
635 } else {
636 renamedTempSerializing++;
637 }
638
639 // Change status over to SerializeStall so that other stages know
640 // what this is blocked on.
641 renameStatus[tid] = SerializeStall;
642
643 serializeInst[tid] = inst;
644
645 blockThisCycle = true;
646
647 break;
648 } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) &&
649 !inst->isSerializeHandled()) {
650 DPRINTF(Rename, "Serialize after instruction encountered.\n");
651
652 renamedSerializing++;
653
654 inst->setSerializeHandled();
655
656 serializeAfter(insts_to_rename, tid);
657 }
658
659 renameSrcRegs(inst, inst->threadNumber);
660
661 renameDestRegs(inst, inst->threadNumber);
662
663 ++renamed_insts;
664
665
666 // Put instruction in rename queue.
667 toIEW->insts[toIEWIndex] = inst;
668 ++(toIEW->size);
669
670 // Increment which instruction we're on.
671 ++toIEWIndex;
672
673 // Decrement how many instructions are available.
674 --insts_available;
675 }
676
677 instsInProgress[tid] += renamed_insts;
678 renameRenamedInsts += renamed_insts;
679
680 // If we wrote to the time buffer, record this.
681 if (toIEWIndex) {
682 wroteToTimeBuffer = true;
683 }
684
685 // Check if there's any instructions left that haven't yet been renamed.
686 // If so then block.
687 if (insts_available) {
688 blockThisCycle = true;
689 }
690
691 if (blockThisCycle) {
692 block(tid);
693 toDecode->renameUnblock[tid] = false;
694 }
695}
696
697template<class Impl>
698void
699DefaultRename<Impl>::skidInsert(ThreadID tid)
700{
701 DynInstPtr inst = NULL;
702
703 while (!insts[tid].empty()) {
704 inst = insts[tid].front();
705
706 insts[tid].pop_front();
707
708 assert(tid == inst->threadNumber);
709
710 DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC: %s into Rename "
711 "skidBuffer\n", tid, inst->seqNum, inst->pcState());
712
713 ++renameSkidInsts;
714
715 skidBuffer[tid].push_back(inst);
716 }
717
718 if (skidBuffer[tid].size() > skidBufferMax)
719 {
720 typename InstQueue::iterator it;
721 warn("Skidbuffer contents:\n");
722 for(it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++)
723 {
724 warn("[tid:%u]: %s [sn:%i].\n", tid,
725 (*it)->staticInst->disassemble(inst->instAddr()),
726 (*it)->seqNum);
727 }
728 panic("Skidbuffer Exceeded Max Size");
729 }
730}
731
732template <class Impl>
733void
734DefaultRename<Impl>::sortInsts()
735{
736 int insts_from_decode = fromDecode->size;
737 for (int i = 0; i < insts_from_decode; ++i) {
738 DynInstPtr inst = fromDecode->insts[i];
739 insts[inst->threadNumber].push_back(inst);
740#if TRACING_ON
741 if (DTRACE(O3PipeView)) {
742 inst->renameTick = curTick() - inst->fetchTick;
743 }
744#endif
745 }
746}
747
748template<class Impl>
749bool
750DefaultRename<Impl>::skidsEmpty()
751{
752 list<ThreadID>::iterator threads = activeThreads->begin();
753 list<ThreadID>::iterator end = activeThreads->end();
754
755 while (threads != end) {
756 ThreadID tid = *threads++;
757
758 if (!skidBuffer[tid].empty())
759 return false;
760 }
761
762 return true;
763}
764
765template<class Impl>
766void
767DefaultRename<Impl>::updateStatus()
768{
769 bool any_unblocking = false;
770
771 list<ThreadID>::iterator threads = activeThreads->begin();
772 list<ThreadID>::iterator end = activeThreads->end();
773
774 while (threads != end) {
775 ThreadID tid = *threads++;
776
777 if (renameStatus[tid] == Unblocking) {
778 any_unblocking = true;
779 break;
780 }
781 }
782
783 // Rename will have activity if it's unblocking.
784 if (any_unblocking) {
785 if (_status == Inactive) {
786 _status = Active;
787
788 DPRINTF(Activity, "Activating stage.\n");
789
790 cpu->activateStage(O3CPU::RenameIdx);
791 }
792 } else {
793 // If it's not unblocking, then rename will not have any internal
794 // activity. Switch it to inactive.
795 if (_status == Active) {
796 _status = Inactive;
797 DPRINTF(Activity, "Deactivating stage.\n");
798
799 cpu->deactivateStage(O3CPU::RenameIdx);
800 }
801 }
802}
803
804template <class Impl>
805bool
806DefaultRename<Impl>::block(ThreadID tid)
807{
808 DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid);
809
810 // Add the current inputs onto the skid buffer, so they can be
811 // reprocessed when this stage unblocks.
812 skidInsert(tid);
813
814 // Only signal backwards to block if the previous stages do not think
815 // rename is already blocked.
816 if (renameStatus[tid] != Blocked) {
817 // If resumeUnblocking is set, we unblocked during the squash,
818 // but now we're have unblocking status. We need to tell earlier
819 // stages to block.
820 if (resumeUnblocking || renameStatus[tid] != Unblocking) {
821 toDecode->renameBlock[tid] = true;
822 toDecode->renameUnblock[tid] = false;
823 wroteToTimeBuffer = true;
824 }
825
826 // Rename can not go from SerializeStall to Blocked, otherwise
827 // it would not know to complete the serialize stall.
828 if (renameStatus[tid] != SerializeStall) {
829 // Set status to Blocked.
830 renameStatus[tid] = Blocked;
831 return true;
832 }
833 }
834
835 return false;
836}
837
838template <class Impl>
839bool
840DefaultRename<Impl>::unblock(ThreadID tid)
841{
842 DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid);
843
844 // Rename is done unblocking if the skid buffer is empty.
845 if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) {
846
847 DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid);
848
849 toDecode->renameUnblock[tid] = true;
850 wroteToTimeBuffer = true;
851
852 renameStatus[tid] = Running;
853 return true;
854 }
855
856 return false;
857}
858
859template <class Impl>
860void
861DefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, ThreadID tid)
862{
863 typename std::list<RenameHistory>::iterator hb_it =
864 historyBuffer[tid].begin();
865
866 // After a syscall squashes everything, the history buffer may be empty
867 // but the ROB may still be squashing instructions.
868 if (historyBuffer[tid].empty()) {
869 return;
870 }
871
872 // Go through the most recent instructions, undoing the mappings
873 // they did and freeing up the registers.
874 while (!historyBuffer[tid].empty() &&
875 hb_it->instSeqNum > squashed_seq_num) {
876 assert(hb_it != historyBuffer[tid].end());
877
878 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
879 "number %i.\n", tid, hb_it->instSeqNum);
880
881 // Undo the rename mapping only if it was really a change.
882 // Special regs that are not really renamed (like misc regs
883 // and the zero reg) can be recognized because the new mapping
884 // is the same as the old one. While it would be merely a
885 // waste of time to update the rename table, we definitely
886 // don't want to put these on the free list.
887 if (hb_it->newPhysReg != hb_it->prevPhysReg) {
888 // Tell the rename map to set the architected register to the
889 // previous physical register that it was renamed to.
890 renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
891
892 // Put the renamed physical register back on the free list.
893 freeList->addReg(hb_it->newPhysReg);
894 }
895
896 historyBuffer[tid].erase(hb_it++);
897
898 ++renameUndoneMaps;
899 }
900}
901
902template<class Impl>
903void
904DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid)
905{
906 DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the "
907 "history buffer %u (size=%i), until [sn:%lli].\n",
908 tid, tid, historyBuffer[tid].size(), inst_seq_num);
909
910 typename std::list<RenameHistory>::iterator hb_it =
911 historyBuffer[tid].end();
912
913 --hb_it;
914
915 if (historyBuffer[tid].empty()) {
916 DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid);
917 return;
918 } else if (hb_it->instSeqNum > inst_seq_num) {
919 DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure "
920 "that a syscall happened recently.\n", tid);
921 return;
922 }
923
924 // Commit all the renames up until (and including) the committed sequence
925 // number. Some or even all of the committed instructions may not have
926 // rename histories if they did not have destination registers that were
927 // renamed.
928 while (!historyBuffer[tid].empty() &&
929 hb_it != historyBuffer[tid].end() &&
930 hb_it->instSeqNum <= inst_seq_num) {
931
932 DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, "
933 "[sn:%lli].\n",
934 tid, hb_it->prevPhysReg, hb_it->instSeqNum);
935
936 // Don't free special phys regs like misc and zero regs, which
937 // can be recognized because the new mapping is the same as
938 // the old one.
939 if (hb_it->newPhysReg != hb_it->prevPhysReg) {
940 freeList->addReg(hb_it->prevPhysReg);
941 }
942
943 ++renameCommittedMaps;
944
945 historyBuffer[tid].erase(hb_it--);
946 }
947}
948
949template <class Impl>
950inline void
951DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid)
952{
953 ThreadContext *tc = inst->tcBase();
954 RenameMap *map = renameMap[tid];
955 unsigned num_src_regs = inst->numSrcRegs();
956
957 // Get the architectual register numbers from the source and
958 // operands, and redirect them to the right physical register.
959 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) {
960 RegIndex src_reg = inst->srcRegIdx(src_idx);
961 RegIndex rel_src_reg;
962 RegIndex flat_rel_src_reg;
963 PhysRegIndex renamed_reg;
964
965 switch (regIdxToClass(src_reg, &rel_src_reg)) {
966 case IntRegClass:
967 flat_rel_src_reg = tc->flattenIntIndex(rel_src_reg);
968 renamed_reg = map->lookupInt(flat_rel_src_reg);
969 intRenameLookups++;
970 break;
971
972 case FloatRegClass:
973 flat_rel_src_reg = tc->flattenFloatIndex(rel_src_reg);
974 renamed_reg = map->lookupFloat(flat_rel_src_reg);
975 fpRenameLookups++;
976 break;
977
978 case CCRegClass:
979 flat_rel_src_reg = tc->flattenCCIndex(rel_src_reg);
980 renamed_reg = map->lookupCC(flat_rel_src_reg);
981 break;
982
983 case MiscRegClass:
984 // misc regs don't get flattened
985 flat_rel_src_reg = rel_src_reg;
986 renamed_reg = map->lookupMisc(flat_rel_src_reg);
987 break;
988
989 default:
990 panic("Reg index is out of bound: %d.", src_reg);
991 }
992
993 DPRINTF(Rename, "[tid:%u]: Looking up %s arch reg %i (flattened %i), "
994 "got phys reg %i\n", tid, RegClassStrings[regIdxToClass(src_reg)],
995 (int)src_reg, (int)flat_rel_src_reg, (int)renamed_reg);
996
997 inst->renameSrcReg(src_idx, renamed_reg);
998
999 // See if the register is ready or not.
1000 if (scoreboard->getReg(renamed_reg)) {
1001 DPRINTF(Rename, "[tid:%u]: Register %d is ready.\n",
1002 tid, renamed_reg);
1003
1004 inst->markSrcRegReady(src_idx);
1005 } else {
1006 DPRINTF(Rename, "[tid:%u]: Register %d is not ready.\n",
1007 tid, renamed_reg);
1008 }
1009
1010 ++renameRenameLookups;
1011 }
1012}
1013
1014template <class Impl>
1015inline void
1016DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid)
1017{
1018 ThreadContext *tc = inst->tcBase();
1019 RenameMap *map = renameMap[tid];
1020 unsigned num_dest_regs = inst->numDestRegs();
1021
1022 // Rename the destination registers.
1023 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) {
1024 RegIndex dest_reg = inst->destRegIdx(dest_idx);
1025 RegIndex rel_dest_reg;
1026 RegIndex flat_rel_dest_reg;
1027 RegIndex flat_uni_dest_reg;
1028 typename RenameMap::RenameInfo rename_result;
1029
1030 switch (regIdxToClass(dest_reg, &rel_dest_reg)) {
1031 case IntRegClass:
1032 flat_rel_dest_reg = tc->flattenIntIndex(rel_dest_reg);
1033 rename_result = map->renameInt(flat_rel_dest_reg);
1034 flat_uni_dest_reg = flat_rel_dest_reg; // 1:1 mapping
1035 break;
1036
1037 case FloatRegClass:
1038 flat_rel_dest_reg = tc->flattenFloatIndex(rel_dest_reg);
1039 rename_result = map->renameFloat(flat_rel_dest_reg);
1040 flat_uni_dest_reg = flat_rel_dest_reg + TheISA::FP_Reg_Base;
1041 break;
1042
1043 case CCRegClass:
1044 flat_rel_dest_reg = tc->flattenCCIndex(rel_dest_reg);
1045 rename_result = map->renameCC(flat_rel_dest_reg);
1046 flat_uni_dest_reg = flat_rel_dest_reg + TheISA::CC_Reg_Base;
1047 break;
1048
1049 case MiscRegClass:
1050 // misc regs don't get flattened
1051 flat_rel_dest_reg = rel_dest_reg;
1052 rename_result = map->renameMisc(flat_rel_dest_reg);
1053 flat_uni_dest_reg = flat_rel_dest_reg + TheISA::Misc_Reg_Base;
1054 break;
1055
1056 default:
1057 panic("Reg index is out of bound: %d.", dest_reg);
1058 }
1059
1060 inst->flattenDestReg(dest_idx, flat_uni_dest_reg);
1061
1062 // Mark Scoreboard entry as not ready
1063 scoreboard->unsetReg(rename_result.first);
1064
1065 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical "
1066 "reg %i.\n", tid, (int)flat_rel_dest_reg,
1067 (int)rename_result.first);
1068
1069 // Record the rename information so that a history can be kept.
1070 RenameHistory hb_entry(inst->seqNum, flat_uni_dest_reg,
1071 rename_result.first,
1072 rename_result.second);
1073
1074 historyBuffer[tid].push_front(hb_entry);
1075
1076 DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer "
1077 "(size=%i), [sn:%lli].\n",tid,
1078 historyBuffer[tid].size(),
1079 (*historyBuffer[tid].begin()).instSeqNum);
1080
1081 // Tell the instruction to rename the appropriate destination
1082 // register (dest_idx) to the new physical register
1083 // (rename_result.first), and record the previous physical
1084 // register that the same logical register was renamed to
1085 // (rename_result.second).
1086 inst->renameDestReg(dest_idx,
1087 rename_result.first,
1088 rename_result.second);
1089
1090 ++renameRenamedOperands;
1091 }
1092}
1093
1094template <class Impl>
1095inline int
1096DefaultRename<Impl>::calcFreeROBEntries(ThreadID tid)
1097{
1098 int num_free = freeEntries[tid].robEntries -
1099 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1100
1101 //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free);
1102
1103 return num_free;
1104}
1105
1106template <class Impl>
1107inline int
1108DefaultRename<Impl>::calcFreeIQEntries(ThreadID tid)
1109{
1110 int num_free = freeEntries[tid].iqEntries -
1111 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1112
1113 //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free);
1114
1115 return num_free;
1116}
1117
1118template <class Impl>
1119inline int
1120DefaultRename<Impl>::calcFreeLSQEntries(ThreadID tid)
1121{
1122 int num_free = freeEntries[tid].lsqEntries -
1123 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ);
1124
1125 //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free);
1126
1127 return num_free;
1128}
1129
1130template <class Impl>
1131unsigned
1132DefaultRename<Impl>::validInsts()
1133{
1134 unsigned inst_count = 0;
1135
1136 for (int i=0; i<fromDecode->size; i++) {
1137 if (!fromDecode->insts[i]->isSquashed())
1138 inst_count++;
1139 }
1140
1141 return inst_count;
1142}
1143
1144template <class Impl>
1145void
1146DefaultRename<Impl>::readStallSignals(ThreadID tid)
1147{
1148 if (fromIEW->iewBlock[tid]) {
1149 stalls[tid].iew = true;
1150 }
1151
1152 if (fromIEW->iewUnblock[tid]) {
1153 assert(stalls[tid].iew);
1154 stalls[tid].iew = false;
1155 }
1156
1157 if (fromCommit->commitBlock[tid]) {
1158 stalls[tid].commit = true;
1159 }
1160
1161 if (fromCommit->commitUnblock[tid]) {
1162 assert(stalls[tid].commit);
1163 stalls[tid].commit = false;
1164 }
1165}
1166
1167template <class Impl>
1168bool
1169DefaultRename<Impl>::checkStall(ThreadID tid)
1170{
1171 bool ret_val = false;
1172
1173 if (stalls[tid].iew) {
1174 DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid);
1175 ret_val = true;
1176 } else if (stalls[tid].commit) {
1177 DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid);
1178 ret_val = true;
1179 } else if (calcFreeROBEntries(tid) <= 0) {
1180 DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid);
1181 ret_val = true;
1182 } else if (calcFreeIQEntries(tid) <= 0) {
1183 DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid);
1184 ret_val = true;
1185 } else if (calcFreeLSQEntries(tid) <= 0) {
1186 DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid);
1187 ret_val = true;
1188 } else if (renameMap[tid]->numFreeEntries() <= 0) {
1189 DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid);
1190 ret_val = true;
1191 } else if (renameStatus[tid] == SerializeStall &&
1192 (!emptyROB[tid] || instsInProgress[tid])) {
1193 DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not "
1194 "empty.\n",
1195 tid);
1196 ret_val = true;
1197 }
1198
1199 return ret_val;
1200}
1201
1202template <class Impl>
1203void
1204DefaultRename<Impl>::readFreeEntries(ThreadID tid)
1205{
1206 if (fromIEW->iewInfo[tid].usedIQ)
1207 freeEntries[tid].iqEntries = fromIEW->iewInfo[tid].freeIQEntries;
1208
1209 if (fromIEW->iewInfo[tid].usedLSQ)
1210 freeEntries[tid].lsqEntries = fromIEW->iewInfo[tid].freeLSQEntries;
1211
1212 if (fromCommit->commitInfo[tid].usedROB) {
1213 freeEntries[tid].robEntries =
1214 fromCommit->commitInfo[tid].freeROBEntries;
1215 emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB;
1216 }
1217
1218 DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n",
1219 tid,
1220 freeEntries[tid].iqEntries,
1221 freeEntries[tid].robEntries,
1222 freeEntries[tid].lsqEntries);
1223
1224 DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n",
1225 tid, instsInProgress[tid]);
1226}
1227
1228template <class Impl>
1229bool
1230DefaultRename<Impl>::checkSignalsAndUpdate(ThreadID tid)
1231{
1232 // Check if there's a squash signal, squash if there is
1233 // Check stall signals, block if necessary.
1234 // If status was blocked
1235 // check if stall conditions have passed
1236 // if so then go to unblocking
1237 // If status was Squashing
1238 // check if squashing is not high. Switch to running this cycle.
1239 // If status was serialize stall
1240 // check if ROB is empty and no insts are in flight to the ROB
1241
1242 readFreeEntries(tid);
1243 readStallSignals(tid);
1244
1245 if (fromCommit->commitInfo[tid].squash) {
1246 DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from "
1247 "commit.\n", tid);
1248
1249 squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
1250
1251 return true;
1252 }
1253
1254 if (fromCommit->commitInfo[tid].robSquashing) {
1255 DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid);
1256
1257 renameStatus[tid] = Squashing;
1258
1259 return true;
1260 }
1261
1262 if (checkStall(tid)) {
1263 return block(tid);
1264 }
1265
1266 if (renameStatus[tid] == Blocked) {
1267 DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n",
1268 tid);
1269
1270 renameStatus[tid] = Unblocking;
1271
1272 unblock(tid);
1273
1274 return true;
1275 }
1276
1277 if (renameStatus[tid] == Squashing) {
1278 // Switch status to running if rename isn't being told to block or
1279 // squash this cycle.
1280 if (resumeSerialize) {
1281 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n",
1282 tid);
1283
1284 renameStatus[tid] = SerializeStall;
1285 return true;
1286 } else if (resumeUnblocking) {
1287 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n",
1288 tid);
1289 renameStatus[tid] = Unblocking;
1290 return true;
1291 } else {
1292 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n",
1293 tid);
1294
1295 renameStatus[tid] = Running;
1296 return false;
1297 }
1298 }
1299
1300 if (renameStatus[tid] == SerializeStall) {
1301 // Stall ends once the ROB is free.
1302 DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to "
1303 "unblocking.\n", tid);
1304
1305 DynInstPtr serial_inst = serializeInst[tid];
1306
1307 renameStatus[tid] = Unblocking;
1308
1309 unblock(tid);
1310
1311 DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with "
1312 "PC %s.\n", tid, serial_inst->seqNum, serial_inst->pcState());
1313
1314 // Put instruction into queue here.
1315 serial_inst->clearSerializeBefore();
1316
1317 if (!skidBuffer[tid].empty()) {
1318 skidBuffer[tid].push_front(serial_inst);
1319 } else {
1320 insts[tid].push_front(serial_inst);
1321 }
1322
1323 DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename."
1324 " Adding to front of list.\n", tid);
1325
1326 serializeInst[tid] = NULL;
1327
1328 return true;
1329 }
1330
1331 // If we've reached this point, we have not gotten any signals that
1332 // cause rename to change its status. Rename remains the same as before.
1333 return false;
1334}
1335
1336template<class Impl>
1337void
1338DefaultRename<Impl>::serializeAfter(InstQueue &inst_list, ThreadID tid)
1339{
1340 if (inst_list.empty()) {
1341 // Mark a bit to say that I must serialize on the next instruction.
1342 serializeOnNextInst[tid] = true;
1343 return;
1344 }
1345
1346 // Set the next instruction as serializing.
1347 inst_list.front()->setSerializeBefore();
1348}
1349
1350template <class Impl>
1351inline void
1352DefaultRename<Impl>::incrFullStat(const FullSource &source)
1353{
1354 switch (source) {
1355 case ROB:
1356 ++renameROBFullEvents;
1357 break;
1358 case IQ:
1359 ++renameIQFullEvents;
1360 break;
1361 case LSQ:
1362 ++renameLSQFullEvents;
1363 break;
1364 default:
1365 panic("Rename full stall stat should be incremented for a reason!");
1366 break;
1367 }
1368}
1369
1370template <class Impl>
1371void
1372DefaultRename<Impl>::dumpHistory()
1373{
1374 typename std::list<RenameHistory>::iterator buf_it;
1375
1376 for (ThreadID tid = 0; tid < numThreads; tid++) {
1377
1378 buf_it = historyBuffer[tid].begin();
1379
1380 while (buf_it != historyBuffer[tid].end()) {
1381 cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys "
1382 "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg,
1383 (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg);
1384
1385 buf_it++;
1386 }
1387 }
1388}
1389
1390#endif//__CPU_O3_RENAME_IMPL_HH__
79 // @todo: Make into a parameter.
80 skidBufferMax = (2 * (decodeToRenameDelay * params->decodeWidth)) + renameWidth;
81}
82
83template <class Impl>
84std::string
85DefaultRename<Impl>::name() const
86{
87 return cpu->name() + ".rename";
88}
89
90template <class Impl>
91void
92DefaultRename<Impl>::regStats()
93{
94 renameSquashCycles
95 .name(name() + ".SquashCycles")
96 .desc("Number of cycles rename is squashing")
97 .prereq(renameSquashCycles);
98 renameIdleCycles
99 .name(name() + ".IdleCycles")
100 .desc("Number of cycles rename is idle")
101 .prereq(renameIdleCycles);
102 renameBlockCycles
103 .name(name() + ".BlockCycles")
104 .desc("Number of cycles rename is blocking")
105 .prereq(renameBlockCycles);
106 renameSerializeStallCycles
107 .name(name() + ".serializeStallCycles")
108 .desc("count of cycles rename stalled for serializing inst")
109 .flags(Stats::total);
110 renameRunCycles
111 .name(name() + ".RunCycles")
112 .desc("Number of cycles rename is running")
113 .prereq(renameIdleCycles);
114 renameUnblockCycles
115 .name(name() + ".UnblockCycles")
116 .desc("Number of cycles rename is unblocking")
117 .prereq(renameUnblockCycles);
118 renameRenamedInsts
119 .name(name() + ".RenamedInsts")
120 .desc("Number of instructions processed by rename")
121 .prereq(renameRenamedInsts);
122 renameSquashedInsts
123 .name(name() + ".SquashedInsts")
124 .desc("Number of squashed instructions processed by rename")
125 .prereq(renameSquashedInsts);
126 renameROBFullEvents
127 .name(name() + ".ROBFullEvents")
128 .desc("Number of times rename has blocked due to ROB full")
129 .prereq(renameROBFullEvents);
130 renameIQFullEvents
131 .name(name() + ".IQFullEvents")
132 .desc("Number of times rename has blocked due to IQ full")
133 .prereq(renameIQFullEvents);
134 renameLSQFullEvents
135 .name(name() + ".LSQFullEvents")
136 .desc("Number of times rename has blocked due to LSQ full")
137 .prereq(renameLSQFullEvents);
138 renameFullRegistersEvents
139 .name(name() + ".FullRegisterEvents")
140 .desc("Number of times there has been no free registers")
141 .prereq(renameFullRegistersEvents);
142 renameRenamedOperands
143 .name(name() + ".RenamedOperands")
144 .desc("Number of destination operands rename has renamed")
145 .prereq(renameRenamedOperands);
146 renameRenameLookups
147 .name(name() + ".RenameLookups")
148 .desc("Number of register rename lookups that rename has made")
149 .prereq(renameRenameLookups);
150 renameCommittedMaps
151 .name(name() + ".CommittedMaps")
152 .desc("Number of HB maps that are committed")
153 .prereq(renameCommittedMaps);
154 renameUndoneMaps
155 .name(name() + ".UndoneMaps")
156 .desc("Number of HB maps that are undone due to squashing")
157 .prereq(renameUndoneMaps);
158 renamedSerializing
159 .name(name() + ".serializingInsts")
160 .desc("count of serializing insts renamed")
161 .flags(Stats::total)
162 ;
163 renamedTempSerializing
164 .name(name() + ".tempSerializingInsts")
165 .desc("count of temporary serializing insts renamed")
166 .flags(Stats::total)
167 ;
168 renameSkidInsts
169 .name(name() + ".skidInsts")
170 .desc("count of insts added to the skid buffer")
171 .flags(Stats::total)
172 ;
173 intRenameLookups
174 .name(name() + ".int_rename_lookups")
175 .desc("Number of integer rename lookups")
176 .prereq(intRenameLookups);
177 fpRenameLookups
178 .name(name() + ".fp_rename_lookups")
179 .desc("Number of floating rename lookups")
180 .prereq(fpRenameLookups);
181}
182
183template <class Impl>
184void
185DefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
186{
187 timeBuffer = tb_ptr;
188
189 // Setup wire to read information from time buffer, from IEW stage.
190 fromIEW = timeBuffer->getWire(-iewToRenameDelay);
191
192 // Setup wire to read infromation from time buffer, from commit stage.
193 fromCommit = timeBuffer->getWire(-commitToRenameDelay);
194
195 // Setup wire to write information to previous stages.
196 toDecode = timeBuffer->getWire(0);
197}
198
199template <class Impl>
200void
201DefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
202{
203 renameQueue = rq_ptr;
204
205 // Setup wire to write information to future stages.
206 toIEW = renameQueue->getWire(0);
207}
208
209template <class Impl>
210void
211DefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
212{
213 decodeQueue = dq_ptr;
214
215 // Setup wire to get information from decode.
216 fromDecode = decodeQueue->getWire(-decodeToRenameDelay);
217}
218
219template <class Impl>
220void
221DefaultRename<Impl>::startupStage()
222{
223 resetStage();
224}
225
226template <class Impl>
227void
228DefaultRename<Impl>::resetStage()
229{
230 _status = Inactive;
231
232 resumeSerialize = false;
233 resumeUnblocking = false;
234
235 // Grab the number of free entries directly from the stages.
236 for (ThreadID tid = 0; tid < numThreads; tid++) {
237 renameStatus[tid] = Idle;
238
239 freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid);
240 freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid);
241 freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid);
242 emptyROB[tid] = true;
243
244 stalls[tid].iew = false;
245 stalls[tid].commit = false;
246 serializeInst[tid] = NULL;
247
248 instsInProgress[tid] = 0;
249
250 serializeOnNextInst[tid] = false;
251 }
252}
253
254template<class Impl>
255void
256DefaultRename<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
257{
258 activeThreads = at_ptr;
259}
260
261
262template <class Impl>
263void
264DefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[])
265{
266 for (ThreadID tid = 0; tid < numThreads; tid++)
267 renameMap[tid] = &rm_ptr[tid];
268}
269
270template <class Impl>
271void
272DefaultRename<Impl>::setFreeList(FreeList *fl_ptr)
273{
274 freeList = fl_ptr;
275}
276
277template<class Impl>
278void
279DefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard)
280{
281 scoreboard = _scoreboard;
282}
283
284template <class Impl>
285bool
286DefaultRename<Impl>::isDrained() const
287{
288 for (ThreadID tid = 0; tid < numThreads; tid++) {
289 if (instsInProgress[tid] != 0 ||
290 !historyBuffer[tid].empty() ||
291 !skidBuffer[tid].empty() ||
292 !insts[tid].empty())
293 return false;
294 }
295 return true;
296}
297
298template <class Impl>
299void
300DefaultRename<Impl>::takeOverFrom()
301{
302 resetStage();
303}
304
305template <class Impl>
306void
307DefaultRename<Impl>::drainSanityCheck() const
308{
309 for (ThreadID tid = 0; tid < numThreads; tid++) {
310 assert(historyBuffer[tid].empty());
311 assert(insts[tid].empty());
312 assert(skidBuffer[tid].empty());
313 assert(instsInProgress[tid] == 0);
314 }
315}
316
317template <class Impl>
318void
319DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, ThreadID tid)
320{
321 DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid);
322
323 // Clear the stall signal if rename was blocked or unblocking before.
324 // If it still needs to block, the blocking should happen the next
325 // cycle and there should be space to hold everything due to the squash.
326 if (renameStatus[tid] == Blocked ||
327 renameStatus[tid] == Unblocking) {
328 toDecode->renameUnblock[tid] = 1;
329
330 resumeSerialize = false;
331 serializeInst[tid] = NULL;
332 } else if (renameStatus[tid] == SerializeStall) {
333 if (serializeInst[tid]->seqNum <= squash_seq_num) {
334 DPRINTF(Rename, "Rename will resume serializing after squash\n");
335 resumeSerialize = true;
336 assert(serializeInst[tid]);
337 } else {
338 resumeSerialize = false;
339 toDecode->renameUnblock[tid] = 1;
340
341 serializeInst[tid] = NULL;
342 }
343 }
344
345 // Set the status to Squashing.
346 renameStatus[tid] = Squashing;
347
348 // Squash any instructions from decode.
349 for (int i=0; i<fromDecode->size; i++) {
350 if (fromDecode->insts[i]->threadNumber == tid &&
351 fromDecode->insts[i]->seqNum > squash_seq_num) {
352 fromDecode->insts[i]->setSquashed();
353 wroteToTimeBuffer = true;
354 }
355
356 }
357
358 // Clear the instruction list and skid buffer in case they have any
359 // insts in them.
360 insts[tid].clear();
361
362 // Clear the skid buffer in case it has any data in it.
363 skidBuffer[tid].clear();
364
365 doSquash(squash_seq_num, tid);
366}
367
368template <class Impl>
369void
370DefaultRename<Impl>::tick()
371{
372 wroteToTimeBuffer = false;
373
374 blockThisCycle = false;
375
376 bool status_change = false;
377
378 toIEWIndex = 0;
379
380 sortInsts();
381
382 list<ThreadID>::iterator threads = activeThreads->begin();
383 list<ThreadID>::iterator end = activeThreads->end();
384
385 // Check stall and squash signals.
386 while (threads != end) {
387 ThreadID tid = *threads++;
388
389 DPRINTF(Rename, "Processing [tid:%i]\n", tid);
390
391 status_change = checkSignalsAndUpdate(tid) || status_change;
392
393 rename(status_change, tid);
394 }
395
396 if (status_change) {
397 updateStatus();
398 }
399
400 if (wroteToTimeBuffer) {
401 DPRINTF(Activity, "Activity this cycle.\n");
402 cpu->activityThisCycle();
403 }
404
405 threads = activeThreads->begin();
406
407 while (threads != end) {
408 ThreadID tid = *threads++;
409
410 // If we committed this cycle then doneSeqNum will be > 0
411 if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
412 !fromCommit->commitInfo[tid].squash &&
413 renameStatus[tid] != Squashing) {
414
415 removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum,
416 tid);
417 }
418 }
419
420 // @todo: make into updateProgress function
421 for (ThreadID tid = 0; tid < numThreads; tid++) {
422 instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched;
423
424 assert(instsInProgress[tid] >=0);
425 }
426
427}
428
429template<class Impl>
430void
431DefaultRename<Impl>::rename(bool &status_change, ThreadID tid)
432{
433 // If status is Running or idle,
434 // call renameInsts()
435 // If status is Unblocking,
436 // buffer any instructions coming from decode
437 // continue trying to empty skid buffer
438 // check if stall conditions have passed
439
440 if (renameStatus[tid] == Blocked) {
441 ++renameBlockCycles;
442 } else if (renameStatus[tid] == Squashing) {
443 ++renameSquashCycles;
444 } else if (renameStatus[tid] == SerializeStall) {
445 ++renameSerializeStallCycles;
446 // If we are currently in SerializeStall and resumeSerialize
447 // was set, then that means that we are resuming serializing
448 // this cycle. Tell the previous stages to block.
449 if (resumeSerialize) {
450 resumeSerialize = false;
451 block(tid);
452 toDecode->renameUnblock[tid] = false;
453 }
454 } else if (renameStatus[tid] == Unblocking) {
455 if (resumeUnblocking) {
456 block(tid);
457 resumeUnblocking = false;
458 toDecode->renameUnblock[tid] = false;
459 }
460 }
461
462 if (renameStatus[tid] == Running ||
463 renameStatus[tid] == Idle) {
464 DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run "
465 "stage.\n", tid);
466
467 renameInsts(tid);
468 } else if (renameStatus[tid] == Unblocking) {
469 renameInsts(tid);
470
471 if (validInsts()) {
472 // Add the current inputs to the skid buffer so they can be
473 // reprocessed when this stage unblocks.
474 skidInsert(tid);
475 }
476
477 // If we switched over to blocking, then there's a potential for
478 // an overall status change.
479 status_change = unblock(tid) || status_change || blockThisCycle;
480 }
481}
482
483template <class Impl>
484void
485DefaultRename<Impl>::renameInsts(ThreadID tid)
486{
487 // Instructions can be either in the skid buffer or the queue of
488 // instructions coming from decode, depending on the status.
489 int insts_available = renameStatus[tid] == Unblocking ?
490 skidBuffer[tid].size() : insts[tid].size();
491
492 // Check the decode queue to see if instructions are available.
493 // If there are no available instructions to rename, then do nothing.
494 if (insts_available == 0) {
495 DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n",
496 tid);
497 // Should I change status to idle?
498 ++renameIdleCycles;
499 return;
500 } else if (renameStatus[tid] == Unblocking) {
501 ++renameUnblockCycles;
502 } else if (renameStatus[tid] == Running) {
503 ++renameRunCycles;
504 }
505
506 DynInstPtr inst;
507
508 // Will have to do a different calculation for the number of free
509 // entries.
510 int free_rob_entries = calcFreeROBEntries(tid);
511 int free_iq_entries = calcFreeIQEntries(tid);
512 int free_lsq_entries = calcFreeLSQEntries(tid);
513 int min_free_entries = free_rob_entries;
514
515 FullSource source = ROB;
516
517 if (free_iq_entries < min_free_entries) {
518 min_free_entries = free_iq_entries;
519 source = IQ;
520 }
521
522 if (free_lsq_entries < min_free_entries) {
523 min_free_entries = free_lsq_entries;
524 source = LSQ;
525 }
526
527 // Check if there's any space left.
528 if (min_free_entries <= 0) {
529 DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ "
530 "entries.\n"
531 "ROB has %i free entries.\n"
532 "IQ has %i free entries.\n"
533 "LSQ has %i free entries.\n",
534 tid,
535 free_rob_entries,
536 free_iq_entries,
537 free_lsq_entries);
538
539 blockThisCycle = true;
540
541 block(tid);
542
543 incrFullStat(source);
544
545 return;
546 } else if (min_free_entries < insts_available) {
547 DPRINTF(Rename, "[tid:%u]: Will have to block this cycle."
548 "%i insts available, but only %i insts can be "
549 "renamed due to ROB/IQ/LSQ limits.\n",
550 tid, insts_available, min_free_entries);
551
552 insts_available = min_free_entries;
553
554 blockThisCycle = true;
555
556 incrFullStat(source);
557 }
558
559 InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ?
560 skidBuffer[tid] : insts[tid];
561
562 DPRINTF(Rename, "[tid:%u]: %i available instructions to "
563 "send iew.\n", tid, insts_available);
564
565 DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts "
566 "dispatched to IQ last cycle.\n",
567 tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched);
568
569 // Handle serializing the next instruction if necessary.
570 if (serializeOnNextInst[tid]) {
571 if (emptyROB[tid] && instsInProgress[tid] == 0) {
572 // ROB already empty; no need to serialize.
573 serializeOnNextInst[tid] = false;
574 } else if (!insts_to_rename.empty()) {
575 insts_to_rename.front()->setSerializeBefore();
576 }
577 }
578
579 int renamed_insts = 0;
580
581 while (insts_available > 0 && toIEWIndex < renameWidth) {
582 DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid);
583
584 assert(!insts_to_rename.empty());
585
586 inst = insts_to_rename.front();
587
588 insts_to_rename.pop_front();
589
590 if (renameStatus[tid] == Unblocking) {
591 DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%s from rename "
592 "skidBuffer\n", tid, inst->seqNum, inst->pcState());
593 }
594
595 if (inst->isSquashed()) {
596 DPRINTF(Rename, "[tid:%u]: instruction %i with PC %s is "
597 "squashed, skipping.\n", tid, inst->seqNum,
598 inst->pcState());
599
600 ++renameSquashedInsts;
601
602 // Decrement how many instructions are available.
603 --insts_available;
604
605 continue;
606 }
607
608 DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with "
609 "PC %s.\n", tid, inst->seqNum, inst->pcState());
610
611 // Check here to make sure there are enough destination registers
612 // to rename to. Otherwise block.
613 if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) {
614 DPRINTF(Rename, "Blocking due to lack of free "
615 "physical registers to rename to.\n");
616 blockThisCycle = true;
617 insts_to_rename.push_front(inst);
618 ++renameFullRegistersEvents;
619
620 break;
621 }
622
623 // Handle serializeAfter/serializeBefore instructions.
624 // serializeAfter marks the next instruction as serializeBefore.
625 // serializeBefore makes the instruction wait in rename until the ROB
626 // is empty.
627
628 // In this model, IPR accesses are serialize before
629 // instructions, and store conditionals are serialize after
630 // instructions. This is mainly due to lack of support for
631 // out-of-order operations of either of those classes of
632 // instructions.
633 if ((inst->isIprAccess() || inst->isSerializeBefore()) &&
634 !inst->isSerializeHandled()) {
635 DPRINTF(Rename, "Serialize before instruction encountered.\n");
636
637 if (!inst->isTempSerializeBefore()) {
638 renamedSerializing++;
639 inst->setSerializeHandled();
640 } else {
641 renamedTempSerializing++;
642 }
643
644 // Change status over to SerializeStall so that other stages know
645 // what this is blocked on.
646 renameStatus[tid] = SerializeStall;
647
648 serializeInst[tid] = inst;
649
650 blockThisCycle = true;
651
652 break;
653 } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) &&
654 !inst->isSerializeHandled()) {
655 DPRINTF(Rename, "Serialize after instruction encountered.\n");
656
657 renamedSerializing++;
658
659 inst->setSerializeHandled();
660
661 serializeAfter(insts_to_rename, tid);
662 }
663
664 renameSrcRegs(inst, inst->threadNumber);
665
666 renameDestRegs(inst, inst->threadNumber);
667
668 ++renamed_insts;
669
670
671 // Put instruction in rename queue.
672 toIEW->insts[toIEWIndex] = inst;
673 ++(toIEW->size);
674
675 // Increment which instruction we're on.
676 ++toIEWIndex;
677
678 // Decrement how many instructions are available.
679 --insts_available;
680 }
681
682 instsInProgress[tid] += renamed_insts;
683 renameRenamedInsts += renamed_insts;
684
685 // If we wrote to the time buffer, record this.
686 if (toIEWIndex) {
687 wroteToTimeBuffer = true;
688 }
689
690 // Check if there's any instructions left that haven't yet been renamed.
691 // If so then block.
692 if (insts_available) {
693 blockThisCycle = true;
694 }
695
696 if (blockThisCycle) {
697 block(tid);
698 toDecode->renameUnblock[tid] = false;
699 }
700}
701
702template<class Impl>
703void
704DefaultRename<Impl>::skidInsert(ThreadID tid)
705{
706 DynInstPtr inst = NULL;
707
708 while (!insts[tid].empty()) {
709 inst = insts[tid].front();
710
711 insts[tid].pop_front();
712
713 assert(tid == inst->threadNumber);
714
715 DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC: %s into Rename "
716 "skidBuffer\n", tid, inst->seqNum, inst->pcState());
717
718 ++renameSkidInsts;
719
720 skidBuffer[tid].push_back(inst);
721 }
722
723 if (skidBuffer[tid].size() > skidBufferMax)
724 {
725 typename InstQueue::iterator it;
726 warn("Skidbuffer contents:\n");
727 for(it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++)
728 {
729 warn("[tid:%u]: %s [sn:%i].\n", tid,
730 (*it)->staticInst->disassemble(inst->instAddr()),
731 (*it)->seqNum);
732 }
733 panic("Skidbuffer Exceeded Max Size");
734 }
735}
736
737template <class Impl>
738void
739DefaultRename<Impl>::sortInsts()
740{
741 int insts_from_decode = fromDecode->size;
742 for (int i = 0; i < insts_from_decode; ++i) {
743 DynInstPtr inst = fromDecode->insts[i];
744 insts[inst->threadNumber].push_back(inst);
745#if TRACING_ON
746 if (DTRACE(O3PipeView)) {
747 inst->renameTick = curTick() - inst->fetchTick;
748 }
749#endif
750 }
751}
752
753template<class Impl>
754bool
755DefaultRename<Impl>::skidsEmpty()
756{
757 list<ThreadID>::iterator threads = activeThreads->begin();
758 list<ThreadID>::iterator end = activeThreads->end();
759
760 while (threads != end) {
761 ThreadID tid = *threads++;
762
763 if (!skidBuffer[tid].empty())
764 return false;
765 }
766
767 return true;
768}
769
770template<class Impl>
771void
772DefaultRename<Impl>::updateStatus()
773{
774 bool any_unblocking = false;
775
776 list<ThreadID>::iterator threads = activeThreads->begin();
777 list<ThreadID>::iterator end = activeThreads->end();
778
779 while (threads != end) {
780 ThreadID tid = *threads++;
781
782 if (renameStatus[tid] == Unblocking) {
783 any_unblocking = true;
784 break;
785 }
786 }
787
788 // Rename will have activity if it's unblocking.
789 if (any_unblocking) {
790 if (_status == Inactive) {
791 _status = Active;
792
793 DPRINTF(Activity, "Activating stage.\n");
794
795 cpu->activateStage(O3CPU::RenameIdx);
796 }
797 } else {
798 // If it's not unblocking, then rename will not have any internal
799 // activity. Switch it to inactive.
800 if (_status == Active) {
801 _status = Inactive;
802 DPRINTF(Activity, "Deactivating stage.\n");
803
804 cpu->deactivateStage(O3CPU::RenameIdx);
805 }
806 }
807}
808
809template <class Impl>
810bool
811DefaultRename<Impl>::block(ThreadID tid)
812{
813 DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid);
814
815 // Add the current inputs onto the skid buffer, so they can be
816 // reprocessed when this stage unblocks.
817 skidInsert(tid);
818
819 // Only signal backwards to block if the previous stages do not think
820 // rename is already blocked.
821 if (renameStatus[tid] != Blocked) {
822 // If resumeUnblocking is set, we unblocked during the squash,
823 // but now we're have unblocking status. We need to tell earlier
824 // stages to block.
825 if (resumeUnblocking || renameStatus[tid] != Unblocking) {
826 toDecode->renameBlock[tid] = true;
827 toDecode->renameUnblock[tid] = false;
828 wroteToTimeBuffer = true;
829 }
830
831 // Rename can not go from SerializeStall to Blocked, otherwise
832 // it would not know to complete the serialize stall.
833 if (renameStatus[tid] != SerializeStall) {
834 // Set status to Blocked.
835 renameStatus[tid] = Blocked;
836 return true;
837 }
838 }
839
840 return false;
841}
842
843template <class Impl>
844bool
845DefaultRename<Impl>::unblock(ThreadID tid)
846{
847 DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid);
848
849 // Rename is done unblocking if the skid buffer is empty.
850 if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) {
851
852 DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid);
853
854 toDecode->renameUnblock[tid] = true;
855 wroteToTimeBuffer = true;
856
857 renameStatus[tid] = Running;
858 return true;
859 }
860
861 return false;
862}
863
864template <class Impl>
865void
866DefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, ThreadID tid)
867{
868 typename std::list<RenameHistory>::iterator hb_it =
869 historyBuffer[tid].begin();
870
871 // After a syscall squashes everything, the history buffer may be empty
872 // but the ROB may still be squashing instructions.
873 if (historyBuffer[tid].empty()) {
874 return;
875 }
876
877 // Go through the most recent instructions, undoing the mappings
878 // they did and freeing up the registers.
879 while (!historyBuffer[tid].empty() &&
880 hb_it->instSeqNum > squashed_seq_num) {
881 assert(hb_it != historyBuffer[tid].end());
882
883 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
884 "number %i.\n", tid, hb_it->instSeqNum);
885
886 // Undo the rename mapping only if it was really a change.
887 // Special regs that are not really renamed (like misc regs
888 // and the zero reg) can be recognized because the new mapping
889 // is the same as the old one. While it would be merely a
890 // waste of time to update the rename table, we definitely
891 // don't want to put these on the free list.
892 if (hb_it->newPhysReg != hb_it->prevPhysReg) {
893 // Tell the rename map to set the architected register to the
894 // previous physical register that it was renamed to.
895 renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
896
897 // Put the renamed physical register back on the free list.
898 freeList->addReg(hb_it->newPhysReg);
899 }
900
901 historyBuffer[tid].erase(hb_it++);
902
903 ++renameUndoneMaps;
904 }
905}
906
907template<class Impl>
908void
909DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid)
910{
911 DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the "
912 "history buffer %u (size=%i), until [sn:%lli].\n",
913 tid, tid, historyBuffer[tid].size(), inst_seq_num);
914
915 typename std::list<RenameHistory>::iterator hb_it =
916 historyBuffer[tid].end();
917
918 --hb_it;
919
920 if (historyBuffer[tid].empty()) {
921 DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid);
922 return;
923 } else if (hb_it->instSeqNum > inst_seq_num) {
924 DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure "
925 "that a syscall happened recently.\n", tid);
926 return;
927 }
928
929 // Commit all the renames up until (and including) the committed sequence
930 // number. Some or even all of the committed instructions may not have
931 // rename histories if they did not have destination registers that were
932 // renamed.
933 while (!historyBuffer[tid].empty() &&
934 hb_it != historyBuffer[tid].end() &&
935 hb_it->instSeqNum <= inst_seq_num) {
936
937 DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, "
938 "[sn:%lli].\n",
939 tid, hb_it->prevPhysReg, hb_it->instSeqNum);
940
941 // Don't free special phys regs like misc and zero regs, which
942 // can be recognized because the new mapping is the same as
943 // the old one.
944 if (hb_it->newPhysReg != hb_it->prevPhysReg) {
945 freeList->addReg(hb_it->prevPhysReg);
946 }
947
948 ++renameCommittedMaps;
949
950 historyBuffer[tid].erase(hb_it--);
951 }
952}
953
954template <class Impl>
955inline void
956DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid)
957{
958 ThreadContext *tc = inst->tcBase();
959 RenameMap *map = renameMap[tid];
960 unsigned num_src_regs = inst->numSrcRegs();
961
962 // Get the architectual register numbers from the source and
963 // operands, and redirect them to the right physical register.
964 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) {
965 RegIndex src_reg = inst->srcRegIdx(src_idx);
966 RegIndex rel_src_reg;
967 RegIndex flat_rel_src_reg;
968 PhysRegIndex renamed_reg;
969
970 switch (regIdxToClass(src_reg, &rel_src_reg)) {
971 case IntRegClass:
972 flat_rel_src_reg = tc->flattenIntIndex(rel_src_reg);
973 renamed_reg = map->lookupInt(flat_rel_src_reg);
974 intRenameLookups++;
975 break;
976
977 case FloatRegClass:
978 flat_rel_src_reg = tc->flattenFloatIndex(rel_src_reg);
979 renamed_reg = map->lookupFloat(flat_rel_src_reg);
980 fpRenameLookups++;
981 break;
982
983 case CCRegClass:
984 flat_rel_src_reg = tc->flattenCCIndex(rel_src_reg);
985 renamed_reg = map->lookupCC(flat_rel_src_reg);
986 break;
987
988 case MiscRegClass:
989 // misc regs don't get flattened
990 flat_rel_src_reg = rel_src_reg;
991 renamed_reg = map->lookupMisc(flat_rel_src_reg);
992 break;
993
994 default:
995 panic("Reg index is out of bound: %d.", src_reg);
996 }
997
998 DPRINTF(Rename, "[tid:%u]: Looking up %s arch reg %i (flattened %i), "
999 "got phys reg %i\n", tid, RegClassStrings[regIdxToClass(src_reg)],
1000 (int)src_reg, (int)flat_rel_src_reg, (int)renamed_reg);
1001
1002 inst->renameSrcReg(src_idx, renamed_reg);
1003
1004 // See if the register is ready or not.
1005 if (scoreboard->getReg(renamed_reg)) {
1006 DPRINTF(Rename, "[tid:%u]: Register %d is ready.\n",
1007 tid, renamed_reg);
1008
1009 inst->markSrcRegReady(src_idx);
1010 } else {
1011 DPRINTF(Rename, "[tid:%u]: Register %d is not ready.\n",
1012 tid, renamed_reg);
1013 }
1014
1015 ++renameRenameLookups;
1016 }
1017}
1018
1019template <class Impl>
1020inline void
1021DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid)
1022{
1023 ThreadContext *tc = inst->tcBase();
1024 RenameMap *map = renameMap[tid];
1025 unsigned num_dest_regs = inst->numDestRegs();
1026
1027 // Rename the destination registers.
1028 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) {
1029 RegIndex dest_reg = inst->destRegIdx(dest_idx);
1030 RegIndex rel_dest_reg;
1031 RegIndex flat_rel_dest_reg;
1032 RegIndex flat_uni_dest_reg;
1033 typename RenameMap::RenameInfo rename_result;
1034
1035 switch (regIdxToClass(dest_reg, &rel_dest_reg)) {
1036 case IntRegClass:
1037 flat_rel_dest_reg = tc->flattenIntIndex(rel_dest_reg);
1038 rename_result = map->renameInt(flat_rel_dest_reg);
1039 flat_uni_dest_reg = flat_rel_dest_reg; // 1:1 mapping
1040 break;
1041
1042 case FloatRegClass:
1043 flat_rel_dest_reg = tc->flattenFloatIndex(rel_dest_reg);
1044 rename_result = map->renameFloat(flat_rel_dest_reg);
1045 flat_uni_dest_reg = flat_rel_dest_reg + TheISA::FP_Reg_Base;
1046 break;
1047
1048 case CCRegClass:
1049 flat_rel_dest_reg = tc->flattenCCIndex(rel_dest_reg);
1050 rename_result = map->renameCC(flat_rel_dest_reg);
1051 flat_uni_dest_reg = flat_rel_dest_reg + TheISA::CC_Reg_Base;
1052 break;
1053
1054 case MiscRegClass:
1055 // misc regs don't get flattened
1056 flat_rel_dest_reg = rel_dest_reg;
1057 rename_result = map->renameMisc(flat_rel_dest_reg);
1058 flat_uni_dest_reg = flat_rel_dest_reg + TheISA::Misc_Reg_Base;
1059 break;
1060
1061 default:
1062 panic("Reg index is out of bound: %d.", dest_reg);
1063 }
1064
1065 inst->flattenDestReg(dest_idx, flat_uni_dest_reg);
1066
1067 // Mark Scoreboard entry as not ready
1068 scoreboard->unsetReg(rename_result.first);
1069
1070 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical "
1071 "reg %i.\n", tid, (int)flat_rel_dest_reg,
1072 (int)rename_result.first);
1073
1074 // Record the rename information so that a history can be kept.
1075 RenameHistory hb_entry(inst->seqNum, flat_uni_dest_reg,
1076 rename_result.first,
1077 rename_result.second);
1078
1079 historyBuffer[tid].push_front(hb_entry);
1080
1081 DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer "
1082 "(size=%i), [sn:%lli].\n",tid,
1083 historyBuffer[tid].size(),
1084 (*historyBuffer[tid].begin()).instSeqNum);
1085
1086 // Tell the instruction to rename the appropriate destination
1087 // register (dest_idx) to the new physical register
1088 // (rename_result.first), and record the previous physical
1089 // register that the same logical register was renamed to
1090 // (rename_result.second).
1091 inst->renameDestReg(dest_idx,
1092 rename_result.first,
1093 rename_result.second);
1094
1095 ++renameRenamedOperands;
1096 }
1097}
1098
1099template <class Impl>
1100inline int
1101DefaultRename<Impl>::calcFreeROBEntries(ThreadID tid)
1102{
1103 int num_free = freeEntries[tid].robEntries -
1104 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1105
1106 //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free);
1107
1108 return num_free;
1109}
1110
1111template <class Impl>
1112inline int
1113DefaultRename<Impl>::calcFreeIQEntries(ThreadID tid)
1114{
1115 int num_free = freeEntries[tid].iqEntries -
1116 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1117
1118 //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free);
1119
1120 return num_free;
1121}
1122
1123template <class Impl>
1124inline int
1125DefaultRename<Impl>::calcFreeLSQEntries(ThreadID tid)
1126{
1127 int num_free = freeEntries[tid].lsqEntries -
1128 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ);
1129
1130 //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free);
1131
1132 return num_free;
1133}
1134
1135template <class Impl>
1136unsigned
1137DefaultRename<Impl>::validInsts()
1138{
1139 unsigned inst_count = 0;
1140
1141 for (int i=0; i<fromDecode->size; i++) {
1142 if (!fromDecode->insts[i]->isSquashed())
1143 inst_count++;
1144 }
1145
1146 return inst_count;
1147}
1148
1149template <class Impl>
1150void
1151DefaultRename<Impl>::readStallSignals(ThreadID tid)
1152{
1153 if (fromIEW->iewBlock[tid]) {
1154 stalls[tid].iew = true;
1155 }
1156
1157 if (fromIEW->iewUnblock[tid]) {
1158 assert(stalls[tid].iew);
1159 stalls[tid].iew = false;
1160 }
1161
1162 if (fromCommit->commitBlock[tid]) {
1163 stalls[tid].commit = true;
1164 }
1165
1166 if (fromCommit->commitUnblock[tid]) {
1167 assert(stalls[tid].commit);
1168 stalls[tid].commit = false;
1169 }
1170}
1171
1172template <class Impl>
1173bool
1174DefaultRename<Impl>::checkStall(ThreadID tid)
1175{
1176 bool ret_val = false;
1177
1178 if (stalls[tid].iew) {
1179 DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid);
1180 ret_val = true;
1181 } else if (stalls[tid].commit) {
1182 DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid);
1183 ret_val = true;
1184 } else if (calcFreeROBEntries(tid) <= 0) {
1185 DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid);
1186 ret_val = true;
1187 } else if (calcFreeIQEntries(tid) <= 0) {
1188 DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid);
1189 ret_val = true;
1190 } else if (calcFreeLSQEntries(tid) <= 0) {
1191 DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid);
1192 ret_val = true;
1193 } else if (renameMap[tid]->numFreeEntries() <= 0) {
1194 DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid);
1195 ret_val = true;
1196 } else if (renameStatus[tid] == SerializeStall &&
1197 (!emptyROB[tid] || instsInProgress[tid])) {
1198 DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not "
1199 "empty.\n",
1200 tid);
1201 ret_val = true;
1202 }
1203
1204 return ret_val;
1205}
1206
1207template <class Impl>
1208void
1209DefaultRename<Impl>::readFreeEntries(ThreadID tid)
1210{
1211 if (fromIEW->iewInfo[tid].usedIQ)
1212 freeEntries[tid].iqEntries = fromIEW->iewInfo[tid].freeIQEntries;
1213
1214 if (fromIEW->iewInfo[tid].usedLSQ)
1215 freeEntries[tid].lsqEntries = fromIEW->iewInfo[tid].freeLSQEntries;
1216
1217 if (fromCommit->commitInfo[tid].usedROB) {
1218 freeEntries[tid].robEntries =
1219 fromCommit->commitInfo[tid].freeROBEntries;
1220 emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB;
1221 }
1222
1223 DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n",
1224 tid,
1225 freeEntries[tid].iqEntries,
1226 freeEntries[tid].robEntries,
1227 freeEntries[tid].lsqEntries);
1228
1229 DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n",
1230 tid, instsInProgress[tid]);
1231}
1232
1233template <class Impl>
1234bool
1235DefaultRename<Impl>::checkSignalsAndUpdate(ThreadID tid)
1236{
1237 // Check if there's a squash signal, squash if there is
1238 // Check stall signals, block if necessary.
1239 // If status was blocked
1240 // check if stall conditions have passed
1241 // if so then go to unblocking
1242 // If status was Squashing
1243 // check if squashing is not high. Switch to running this cycle.
1244 // If status was serialize stall
1245 // check if ROB is empty and no insts are in flight to the ROB
1246
1247 readFreeEntries(tid);
1248 readStallSignals(tid);
1249
1250 if (fromCommit->commitInfo[tid].squash) {
1251 DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from "
1252 "commit.\n", tid);
1253
1254 squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
1255
1256 return true;
1257 }
1258
1259 if (fromCommit->commitInfo[tid].robSquashing) {
1260 DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid);
1261
1262 renameStatus[tid] = Squashing;
1263
1264 return true;
1265 }
1266
1267 if (checkStall(tid)) {
1268 return block(tid);
1269 }
1270
1271 if (renameStatus[tid] == Blocked) {
1272 DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n",
1273 tid);
1274
1275 renameStatus[tid] = Unblocking;
1276
1277 unblock(tid);
1278
1279 return true;
1280 }
1281
1282 if (renameStatus[tid] == Squashing) {
1283 // Switch status to running if rename isn't being told to block or
1284 // squash this cycle.
1285 if (resumeSerialize) {
1286 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n",
1287 tid);
1288
1289 renameStatus[tid] = SerializeStall;
1290 return true;
1291 } else if (resumeUnblocking) {
1292 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n",
1293 tid);
1294 renameStatus[tid] = Unblocking;
1295 return true;
1296 } else {
1297 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n",
1298 tid);
1299
1300 renameStatus[tid] = Running;
1301 return false;
1302 }
1303 }
1304
1305 if (renameStatus[tid] == SerializeStall) {
1306 // Stall ends once the ROB is free.
1307 DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to "
1308 "unblocking.\n", tid);
1309
1310 DynInstPtr serial_inst = serializeInst[tid];
1311
1312 renameStatus[tid] = Unblocking;
1313
1314 unblock(tid);
1315
1316 DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with "
1317 "PC %s.\n", tid, serial_inst->seqNum, serial_inst->pcState());
1318
1319 // Put instruction into queue here.
1320 serial_inst->clearSerializeBefore();
1321
1322 if (!skidBuffer[tid].empty()) {
1323 skidBuffer[tid].push_front(serial_inst);
1324 } else {
1325 insts[tid].push_front(serial_inst);
1326 }
1327
1328 DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename."
1329 " Adding to front of list.\n", tid);
1330
1331 serializeInst[tid] = NULL;
1332
1333 return true;
1334 }
1335
1336 // If we've reached this point, we have not gotten any signals that
1337 // cause rename to change its status. Rename remains the same as before.
1338 return false;
1339}
1340
1341template<class Impl>
1342void
1343DefaultRename<Impl>::serializeAfter(InstQueue &inst_list, ThreadID tid)
1344{
1345 if (inst_list.empty()) {
1346 // Mark a bit to say that I must serialize on the next instruction.
1347 serializeOnNextInst[tid] = true;
1348 return;
1349 }
1350
1351 // Set the next instruction as serializing.
1352 inst_list.front()->setSerializeBefore();
1353}
1354
1355template <class Impl>
1356inline void
1357DefaultRename<Impl>::incrFullStat(const FullSource &source)
1358{
1359 switch (source) {
1360 case ROB:
1361 ++renameROBFullEvents;
1362 break;
1363 case IQ:
1364 ++renameIQFullEvents;
1365 break;
1366 case LSQ:
1367 ++renameLSQFullEvents;
1368 break;
1369 default:
1370 panic("Rename full stall stat should be incremented for a reason!");
1371 break;
1372 }
1373}
1374
1375template <class Impl>
1376void
1377DefaultRename<Impl>::dumpHistory()
1378{
1379 typename std::list<RenameHistory>::iterator buf_it;
1380
1381 for (ThreadID tid = 0; tid < numThreads; tid++) {
1382
1383 buf_it = historyBuffer[tid].begin();
1384
1385 while (buf_it != historyBuffer[tid].end()) {
1386 cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys "
1387 "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg,
1388 (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg);
1389
1390 buf_it++;
1391 }
1392 }
1393}
1394
1395#endif//__CPU_O3_RENAME_IMPL_HH__