1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 * Korey Sewell
43 */
44
45#include <list>
46
47#include "arch/isa_traits.hh"
48#include "arch/registers.hh"
49#include "config/the_isa.hh"
50#include "cpu/o3/rename.hh"
51#include "cpu/reg_class.hh"
52#include "debug/Activity.hh"
53#include "debug/Rename.hh"
54#include "debug/O3PipeView.hh"
55#include "params/DerivO3CPU.hh"
56
57using namespace std;
58
59template <class Impl>
60DefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params)
61 : cpu(_cpu),
62 iewToRenameDelay(params->iewToRenameDelay),
63 decodeToRenameDelay(params->decodeToRenameDelay),
64 commitToRenameDelay(params->commitToRenameDelay),
65 renameWidth(params->renameWidth),
66 commitWidth(params->commitWidth),
67 numThreads(params->numThreads),
| 1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 * Korey Sewell
43 */
44
45#include <list>
46
47#include "arch/isa_traits.hh"
48#include "arch/registers.hh"
49#include "config/the_isa.hh"
50#include "cpu/o3/rename.hh"
51#include "cpu/reg_class.hh"
52#include "debug/Activity.hh"
53#include "debug/Rename.hh"
54#include "debug/O3PipeView.hh"
55#include "params/DerivO3CPU.hh"
56
57using namespace std;
58
59template <class Impl>
60DefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params)
61 : cpu(_cpu),
62 iewToRenameDelay(params->iewToRenameDelay),
63 decodeToRenameDelay(params->decodeToRenameDelay),
64 commitToRenameDelay(params->commitToRenameDelay),
65 renameWidth(params->renameWidth),
66 commitWidth(params->commitWidth),
67 numThreads(params->numThreads),
|
68 maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs)
| 68 maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs
69 + params->numPhysCCRegs)
|
69{
70 // @todo: Make into a parameter.
71 skidBufferMax = (2 * (decodeToRenameDelay * params->decodeWidth)) + renameWidth;
72}
73
74template <class Impl>
75std::string
76DefaultRename<Impl>::name() const
77{
78 return cpu->name() + ".rename";
79}
80
81template <class Impl>
82void
83DefaultRename<Impl>::regStats()
84{
85 renameSquashCycles
86 .name(name() + ".SquashCycles")
87 .desc("Number of cycles rename is squashing")
88 .prereq(renameSquashCycles);
89 renameIdleCycles
90 .name(name() + ".IdleCycles")
91 .desc("Number of cycles rename is idle")
92 .prereq(renameIdleCycles);
93 renameBlockCycles
94 .name(name() + ".BlockCycles")
95 .desc("Number of cycles rename is blocking")
96 .prereq(renameBlockCycles);
97 renameSerializeStallCycles
98 .name(name() + ".serializeStallCycles")
99 .desc("count of cycles rename stalled for serializing inst")
100 .flags(Stats::total);
101 renameRunCycles
102 .name(name() + ".RunCycles")
103 .desc("Number of cycles rename is running")
104 .prereq(renameIdleCycles);
105 renameUnblockCycles
106 .name(name() + ".UnblockCycles")
107 .desc("Number of cycles rename is unblocking")
108 .prereq(renameUnblockCycles);
109 renameRenamedInsts
110 .name(name() + ".RenamedInsts")
111 .desc("Number of instructions processed by rename")
112 .prereq(renameRenamedInsts);
113 renameSquashedInsts
114 .name(name() + ".SquashedInsts")
115 .desc("Number of squashed instructions processed by rename")
116 .prereq(renameSquashedInsts);
117 renameROBFullEvents
118 .name(name() + ".ROBFullEvents")
119 .desc("Number of times rename has blocked due to ROB full")
120 .prereq(renameROBFullEvents);
121 renameIQFullEvents
122 .name(name() + ".IQFullEvents")
123 .desc("Number of times rename has blocked due to IQ full")
124 .prereq(renameIQFullEvents);
125 renameLSQFullEvents
126 .name(name() + ".LSQFullEvents")
127 .desc("Number of times rename has blocked due to LSQ full")
128 .prereq(renameLSQFullEvents);
129 renameFullRegistersEvents
130 .name(name() + ".FullRegisterEvents")
131 .desc("Number of times there has been no free registers")
132 .prereq(renameFullRegistersEvents);
133 renameRenamedOperands
134 .name(name() + ".RenamedOperands")
135 .desc("Number of destination operands rename has renamed")
136 .prereq(renameRenamedOperands);
137 renameRenameLookups
138 .name(name() + ".RenameLookups")
139 .desc("Number of register rename lookups that rename has made")
140 .prereq(renameRenameLookups);
141 renameCommittedMaps
142 .name(name() + ".CommittedMaps")
143 .desc("Number of HB maps that are committed")
144 .prereq(renameCommittedMaps);
145 renameUndoneMaps
146 .name(name() + ".UndoneMaps")
147 .desc("Number of HB maps that are undone due to squashing")
148 .prereq(renameUndoneMaps);
149 renamedSerializing
150 .name(name() + ".serializingInsts")
151 .desc("count of serializing insts renamed")
152 .flags(Stats::total)
153 ;
154 renamedTempSerializing
155 .name(name() + ".tempSerializingInsts")
156 .desc("count of temporary serializing insts renamed")
157 .flags(Stats::total)
158 ;
159 renameSkidInsts
160 .name(name() + ".skidInsts")
161 .desc("count of insts added to the skid buffer")
162 .flags(Stats::total)
163 ;
164 intRenameLookups
165 .name(name() + ".int_rename_lookups")
166 .desc("Number of integer rename lookups")
167 .prereq(intRenameLookups);
168 fpRenameLookups
169 .name(name() + ".fp_rename_lookups")
170 .desc("Number of floating rename lookups")
171 .prereq(fpRenameLookups);
172}
173
174template <class Impl>
175void
176DefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
177{
178 timeBuffer = tb_ptr;
179
180 // Setup wire to read information from time buffer, from IEW stage.
181 fromIEW = timeBuffer->getWire(-iewToRenameDelay);
182
183 // Setup wire to read infromation from time buffer, from commit stage.
184 fromCommit = timeBuffer->getWire(-commitToRenameDelay);
185
186 // Setup wire to write information to previous stages.
187 toDecode = timeBuffer->getWire(0);
188}
189
190template <class Impl>
191void
192DefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
193{
194 renameQueue = rq_ptr;
195
196 // Setup wire to write information to future stages.
197 toIEW = renameQueue->getWire(0);
198}
199
200template <class Impl>
201void
202DefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
203{
204 decodeQueue = dq_ptr;
205
206 // Setup wire to get information from decode.
207 fromDecode = decodeQueue->getWire(-decodeToRenameDelay);
208}
209
210template <class Impl>
211void
212DefaultRename<Impl>::startupStage()
213{
214 resetStage();
215}
216
217template <class Impl>
218void
219DefaultRename<Impl>::resetStage()
220{
221 _status = Inactive;
222
223 resumeSerialize = false;
224 resumeUnblocking = false;
225
226 // Grab the number of free entries directly from the stages.
227 for (ThreadID tid = 0; tid < numThreads; tid++) {
228 renameStatus[tid] = Idle;
229
230 freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid);
231 freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid);
232 freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid);
233 emptyROB[tid] = true;
234
235 stalls[tid].iew = false;
236 stalls[tid].commit = false;
237 serializeInst[tid] = NULL;
238
239 instsInProgress[tid] = 0;
240
241 serializeOnNextInst[tid] = false;
242 }
243}
244
245template<class Impl>
246void
247DefaultRename<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
248{
249 activeThreads = at_ptr;
250}
251
252
253template <class Impl>
254void
255DefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[])
256{
257 for (ThreadID tid = 0; tid < numThreads; tid++)
258 renameMap[tid] = &rm_ptr[tid];
259}
260
261template <class Impl>
262void
263DefaultRename<Impl>::setFreeList(FreeList *fl_ptr)
264{
265 freeList = fl_ptr;
266}
267
268template<class Impl>
269void
270DefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard)
271{
272 scoreboard = _scoreboard;
273}
274
275template <class Impl>
276bool
277DefaultRename<Impl>::isDrained() const
278{
279 for (ThreadID tid = 0; tid < numThreads; tid++) {
280 if (instsInProgress[tid] != 0 ||
281 !historyBuffer[tid].empty() ||
282 !skidBuffer[tid].empty() ||
283 !insts[tid].empty())
284 return false;
285 }
286 return true;
287}
288
289template <class Impl>
290void
291DefaultRename<Impl>::takeOverFrom()
292{
293 resetStage();
294}
295
296template <class Impl>
297void
298DefaultRename<Impl>::drainSanityCheck() const
299{
300 for (ThreadID tid = 0; tid < numThreads; tid++) {
301 assert(historyBuffer[tid].empty());
302 assert(insts[tid].empty());
303 assert(skidBuffer[tid].empty());
304 assert(instsInProgress[tid] == 0);
305 }
306}
307
308template <class Impl>
309void
310DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, ThreadID tid)
311{
312 DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid);
313
314 // Clear the stall signal if rename was blocked or unblocking before.
315 // If it still needs to block, the blocking should happen the next
316 // cycle and there should be space to hold everything due to the squash.
317 if (renameStatus[tid] == Blocked ||
318 renameStatus[tid] == Unblocking) {
319 toDecode->renameUnblock[tid] = 1;
320
321 resumeSerialize = false;
322 serializeInst[tid] = NULL;
323 } else if (renameStatus[tid] == SerializeStall) {
324 if (serializeInst[tid]->seqNum <= squash_seq_num) {
325 DPRINTF(Rename, "Rename will resume serializing after squash\n");
326 resumeSerialize = true;
327 assert(serializeInst[tid]);
328 } else {
329 resumeSerialize = false;
330 toDecode->renameUnblock[tid] = 1;
331
332 serializeInst[tid] = NULL;
333 }
334 }
335
336 // Set the status to Squashing.
337 renameStatus[tid] = Squashing;
338
339 // Squash any instructions from decode.
340 unsigned squashCount = 0;
341
342 for (int i=0; i<fromDecode->size; i++) {
343 if (fromDecode->insts[i]->threadNumber == tid &&
344 fromDecode->insts[i]->seqNum > squash_seq_num) {
345 fromDecode->insts[i]->setSquashed();
346 wroteToTimeBuffer = true;
347 squashCount++;
348 }
349
350 }
351
352 // Clear the instruction list and skid buffer in case they have any
353 // insts in them.
354 insts[tid].clear();
355
356 // Clear the skid buffer in case it has any data in it.
357 skidBuffer[tid].clear();
358
359 doSquash(squash_seq_num, tid);
360}
361
362template <class Impl>
363void
364DefaultRename<Impl>::tick()
365{
366 wroteToTimeBuffer = false;
367
368 blockThisCycle = false;
369
370 bool status_change = false;
371
372 toIEWIndex = 0;
373
374 sortInsts();
375
376 list<ThreadID>::iterator threads = activeThreads->begin();
377 list<ThreadID>::iterator end = activeThreads->end();
378
379 // Check stall and squash signals.
380 while (threads != end) {
381 ThreadID tid = *threads++;
382
383 DPRINTF(Rename, "Processing [tid:%i]\n", tid);
384
385 status_change = checkSignalsAndUpdate(tid) || status_change;
386
387 rename(status_change, tid);
388 }
389
390 if (status_change) {
391 updateStatus();
392 }
393
394 if (wroteToTimeBuffer) {
395 DPRINTF(Activity, "Activity this cycle.\n");
396 cpu->activityThisCycle();
397 }
398
399 threads = activeThreads->begin();
400
401 while (threads != end) {
402 ThreadID tid = *threads++;
403
404 // If we committed this cycle then doneSeqNum will be > 0
405 if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
406 !fromCommit->commitInfo[tid].squash &&
407 renameStatus[tid] != Squashing) {
408
409 removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum,
410 tid);
411 }
412 }
413
414 // @todo: make into updateProgress function
415 for (ThreadID tid = 0; tid < numThreads; tid++) {
416 instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched;
417
418 assert(instsInProgress[tid] >=0);
419 }
420
421}
422
423template<class Impl>
424void
425DefaultRename<Impl>::rename(bool &status_change, ThreadID tid)
426{
427 // If status is Running or idle,
428 // call renameInsts()
429 // If status is Unblocking,
430 // buffer any instructions coming from decode
431 // continue trying to empty skid buffer
432 // check if stall conditions have passed
433
434 if (renameStatus[tid] == Blocked) {
435 ++renameBlockCycles;
436 } else if (renameStatus[tid] == Squashing) {
437 ++renameSquashCycles;
438 } else if (renameStatus[tid] == SerializeStall) {
439 ++renameSerializeStallCycles;
440 // If we are currently in SerializeStall and resumeSerialize
441 // was set, then that means that we are resuming serializing
442 // this cycle. Tell the previous stages to block.
443 if (resumeSerialize) {
444 resumeSerialize = false;
445 block(tid);
446 toDecode->renameUnblock[tid] = false;
447 }
448 } else if (renameStatus[tid] == Unblocking) {
449 if (resumeUnblocking) {
450 block(tid);
451 resumeUnblocking = false;
452 toDecode->renameUnblock[tid] = false;
453 }
454 }
455
456 if (renameStatus[tid] == Running ||
457 renameStatus[tid] == Idle) {
458 DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run "
459 "stage.\n", tid);
460
461 renameInsts(tid);
462 } else if (renameStatus[tid] == Unblocking) {
463 renameInsts(tid);
464
465 if (validInsts()) {
466 // Add the current inputs to the skid buffer so they can be
467 // reprocessed when this stage unblocks.
468 skidInsert(tid);
469 }
470
471 // If we switched over to blocking, then there's a potential for
472 // an overall status change.
473 status_change = unblock(tid) || status_change || blockThisCycle;
474 }
475}
476
477template <class Impl>
478void
479DefaultRename<Impl>::renameInsts(ThreadID tid)
480{
481 // Instructions can be either in the skid buffer or the queue of
482 // instructions coming from decode, depending on the status.
483 int insts_available = renameStatus[tid] == Unblocking ?
484 skidBuffer[tid].size() : insts[tid].size();
485
486 // Check the decode queue to see if instructions are available.
487 // If there are no available instructions to rename, then do nothing.
488 if (insts_available == 0) {
489 DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n",
490 tid);
491 // Should I change status to idle?
492 ++renameIdleCycles;
493 return;
494 } else if (renameStatus[tid] == Unblocking) {
495 ++renameUnblockCycles;
496 } else if (renameStatus[tid] == Running) {
497 ++renameRunCycles;
498 }
499
500 DynInstPtr inst;
501
502 // Will have to do a different calculation for the number of free
503 // entries.
504 int free_rob_entries = calcFreeROBEntries(tid);
505 int free_iq_entries = calcFreeIQEntries(tid);
506 int free_lsq_entries = calcFreeLSQEntries(tid);
507 int min_free_entries = free_rob_entries;
508
509 FullSource source = ROB;
510
511 if (free_iq_entries < min_free_entries) {
512 min_free_entries = free_iq_entries;
513 source = IQ;
514 }
515
516 if (free_lsq_entries < min_free_entries) {
517 min_free_entries = free_lsq_entries;
518 source = LSQ;
519 }
520
521 // Check if there's any space left.
522 if (min_free_entries <= 0) {
523 DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ "
524 "entries.\n"
525 "ROB has %i free entries.\n"
526 "IQ has %i free entries.\n"
527 "LSQ has %i free entries.\n",
528 tid,
529 free_rob_entries,
530 free_iq_entries,
531 free_lsq_entries);
532
533 blockThisCycle = true;
534
535 block(tid);
536
537 incrFullStat(source);
538
539 return;
540 } else if (min_free_entries < insts_available) {
541 DPRINTF(Rename, "[tid:%u]: Will have to block this cycle."
542 "%i insts available, but only %i insts can be "
543 "renamed due to ROB/IQ/LSQ limits.\n",
544 tid, insts_available, min_free_entries);
545
546 insts_available = min_free_entries;
547
548 blockThisCycle = true;
549
550 incrFullStat(source);
551 }
552
553 InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ?
554 skidBuffer[tid] : insts[tid];
555
556 DPRINTF(Rename, "[tid:%u]: %i available instructions to "
557 "send iew.\n", tid, insts_available);
558
559 DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts "
560 "dispatched to IQ last cycle.\n",
561 tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched);
562
563 // Handle serializing the next instruction if necessary.
564 if (serializeOnNextInst[tid]) {
565 if (emptyROB[tid] && instsInProgress[tid] == 0) {
566 // ROB already empty; no need to serialize.
567 serializeOnNextInst[tid] = false;
568 } else if (!insts_to_rename.empty()) {
569 insts_to_rename.front()->setSerializeBefore();
570 }
571 }
572
573 int renamed_insts = 0;
574
575 while (insts_available > 0 && toIEWIndex < renameWidth) {
576 DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid);
577
578 assert(!insts_to_rename.empty());
579
580 inst = insts_to_rename.front();
581
582 insts_to_rename.pop_front();
583
584 if (renameStatus[tid] == Unblocking) {
585 DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%s from rename "
586 "skidBuffer\n", tid, inst->seqNum, inst->pcState());
587 }
588
589 if (inst->isSquashed()) {
590 DPRINTF(Rename, "[tid:%u]: instruction %i with PC %s is "
591 "squashed, skipping.\n", tid, inst->seqNum,
592 inst->pcState());
593
594 ++renameSquashedInsts;
595
596 // Decrement how many instructions are available.
597 --insts_available;
598
599 continue;
600 }
601
602 DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with "
603 "PC %s.\n", tid, inst->seqNum, inst->pcState());
604
605 // Check here to make sure there are enough destination registers
606 // to rename to. Otherwise block.
607 if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) {
608 DPRINTF(Rename, "Blocking due to lack of free "
609 "physical registers to rename to.\n");
610 blockThisCycle = true;
611 insts_to_rename.push_front(inst);
612 ++renameFullRegistersEvents;
613
614 break;
615 }
616
617 // Handle serializeAfter/serializeBefore instructions.
618 // serializeAfter marks the next instruction as serializeBefore.
619 // serializeBefore makes the instruction wait in rename until the ROB
620 // is empty.
621
622 // In this model, IPR accesses are serialize before
623 // instructions, and store conditionals are serialize after
624 // instructions. This is mainly due to lack of support for
625 // out-of-order operations of either of those classes of
626 // instructions.
627 if ((inst->isIprAccess() || inst->isSerializeBefore()) &&
628 !inst->isSerializeHandled()) {
629 DPRINTF(Rename, "Serialize before instruction encountered.\n");
630
631 if (!inst->isTempSerializeBefore()) {
632 renamedSerializing++;
633 inst->setSerializeHandled();
634 } else {
635 renamedTempSerializing++;
636 }
637
638 // Change status over to SerializeStall so that other stages know
639 // what this is blocked on.
640 renameStatus[tid] = SerializeStall;
641
642 serializeInst[tid] = inst;
643
644 blockThisCycle = true;
645
646 break;
647 } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) &&
648 !inst->isSerializeHandled()) {
649 DPRINTF(Rename, "Serialize after instruction encountered.\n");
650
651 renamedSerializing++;
652
653 inst->setSerializeHandled();
654
655 serializeAfter(insts_to_rename, tid);
656 }
657
658 renameSrcRegs(inst, inst->threadNumber);
659
660 renameDestRegs(inst, inst->threadNumber);
661
662 ++renamed_insts;
663
664
665 // Put instruction in rename queue.
666 toIEW->insts[toIEWIndex] = inst;
667 ++(toIEW->size);
668
669 // Increment which instruction we're on.
670 ++toIEWIndex;
671
672 // Decrement how many instructions are available.
673 --insts_available;
674 }
675
676 instsInProgress[tid] += renamed_insts;
677 renameRenamedInsts += renamed_insts;
678
679 // If we wrote to the time buffer, record this.
680 if (toIEWIndex) {
681 wroteToTimeBuffer = true;
682 }
683
684 // Check if there's any instructions left that haven't yet been renamed.
685 // If so then block.
686 if (insts_available) {
687 blockThisCycle = true;
688 }
689
690 if (blockThisCycle) {
691 block(tid);
692 toDecode->renameUnblock[tid] = false;
693 }
694}
695
696template<class Impl>
697void
698DefaultRename<Impl>::skidInsert(ThreadID tid)
699{
700 DynInstPtr inst = NULL;
701
702 while (!insts[tid].empty()) {
703 inst = insts[tid].front();
704
705 insts[tid].pop_front();
706
707 assert(tid == inst->threadNumber);
708
709 DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC: %s into Rename "
710 "skidBuffer\n", tid, inst->seqNum, inst->pcState());
711
712 ++renameSkidInsts;
713
714 skidBuffer[tid].push_back(inst);
715 }
716
717 if (skidBuffer[tid].size() > skidBufferMax)
718 {
719 typename InstQueue::iterator it;
720 warn("Skidbuffer contents:\n");
721 for(it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++)
722 {
723 warn("[tid:%u]: %s [sn:%i].\n", tid,
724 (*it)->staticInst->disassemble(inst->instAddr()),
725 (*it)->seqNum);
726 }
727 panic("Skidbuffer Exceeded Max Size");
728 }
729}
730
731template <class Impl>
732void
733DefaultRename<Impl>::sortInsts()
734{
735 int insts_from_decode = fromDecode->size;
736 for (int i = 0; i < insts_from_decode; ++i) {
737 DynInstPtr inst = fromDecode->insts[i];
738 insts[inst->threadNumber].push_back(inst);
739#if TRACING_ON
740 if (DTRACE(O3PipeView)) {
741 inst->renameTick = curTick() - inst->fetchTick;
742 }
743#endif
744 }
745}
746
747template<class Impl>
748bool
749DefaultRename<Impl>::skidsEmpty()
750{
751 list<ThreadID>::iterator threads = activeThreads->begin();
752 list<ThreadID>::iterator end = activeThreads->end();
753
754 while (threads != end) {
755 ThreadID tid = *threads++;
756
757 if (!skidBuffer[tid].empty())
758 return false;
759 }
760
761 return true;
762}
763
764template<class Impl>
765void
766DefaultRename<Impl>::updateStatus()
767{
768 bool any_unblocking = false;
769
770 list<ThreadID>::iterator threads = activeThreads->begin();
771 list<ThreadID>::iterator end = activeThreads->end();
772
773 while (threads != end) {
774 ThreadID tid = *threads++;
775
776 if (renameStatus[tid] == Unblocking) {
777 any_unblocking = true;
778 break;
779 }
780 }
781
782 // Rename will have activity if it's unblocking.
783 if (any_unblocking) {
784 if (_status == Inactive) {
785 _status = Active;
786
787 DPRINTF(Activity, "Activating stage.\n");
788
789 cpu->activateStage(O3CPU::RenameIdx);
790 }
791 } else {
792 // If it's not unblocking, then rename will not have any internal
793 // activity. Switch it to inactive.
794 if (_status == Active) {
795 _status = Inactive;
796 DPRINTF(Activity, "Deactivating stage.\n");
797
798 cpu->deactivateStage(O3CPU::RenameIdx);
799 }
800 }
801}
802
803template <class Impl>
804bool
805DefaultRename<Impl>::block(ThreadID tid)
806{
807 DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid);
808
809 // Add the current inputs onto the skid buffer, so they can be
810 // reprocessed when this stage unblocks.
811 skidInsert(tid);
812
813 // Only signal backwards to block if the previous stages do not think
814 // rename is already blocked.
815 if (renameStatus[tid] != Blocked) {
816 // If resumeUnblocking is set, we unblocked during the squash,
817 // but now we're have unblocking status. We need to tell earlier
818 // stages to block.
819 if (resumeUnblocking || renameStatus[tid] != Unblocking) {
820 toDecode->renameBlock[tid] = true;
821 toDecode->renameUnblock[tid] = false;
822 wroteToTimeBuffer = true;
823 }
824
825 // Rename can not go from SerializeStall to Blocked, otherwise
826 // it would not know to complete the serialize stall.
827 if (renameStatus[tid] != SerializeStall) {
828 // Set status to Blocked.
829 renameStatus[tid] = Blocked;
830 return true;
831 }
832 }
833
834 return false;
835}
836
837template <class Impl>
838bool
839DefaultRename<Impl>::unblock(ThreadID tid)
840{
841 DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid);
842
843 // Rename is done unblocking if the skid buffer is empty.
844 if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) {
845
846 DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid);
847
848 toDecode->renameUnblock[tid] = true;
849 wroteToTimeBuffer = true;
850
851 renameStatus[tid] = Running;
852 return true;
853 }
854
855 return false;
856}
857
858template <class Impl>
859void
860DefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, ThreadID tid)
861{
862 typename std::list<RenameHistory>::iterator hb_it =
863 historyBuffer[tid].begin();
864
865 // After a syscall squashes everything, the history buffer may be empty
866 // but the ROB may still be squashing instructions.
867 if (historyBuffer[tid].empty()) {
868 return;
869 }
870
871 // Go through the most recent instructions, undoing the mappings
872 // they did and freeing up the registers.
873 while (!historyBuffer[tid].empty() &&
874 hb_it->instSeqNum > squashed_seq_num) {
875 assert(hb_it != historyBuffer[tid].end());
876
877 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
878 "number %i.\n", tid, hb_it->instSeqNum);
879
880 // Undo the rename mapping only if it was really a change.
881 // Special regs that are not really renamed (like misc regs
882 // and the zero reg) can be recognized because the new mapping
883 // is the same as the old one. While it would be merely a
884 // waste of time to update the rename table, we definitely
885 // don't want to put these on the free list.
886 if (hb_it->newPhysReg != hb_it->prevPhysReg) {
887 // Tell the rename map to set the architected register to the
888 // previous physical register that it was renamed to.
889 renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
890
891 // Put the renamed physical register back on the free list.
892 freeList->addReg(hb_it->newPhysReg);
893 }
894
895 historyBuffer[tid].erase(hb_it++);
896
897 ++renameUndoneMaps;
898 }
899}
900
901template<class Impl>
902void
903DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid)
904{
905 DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the "
906 "history buffer %u (size=%i), until [sn:%lli].\n",
907 tid, tid, historyBuffer[tid].size(), inst_seq_num);
908
909 typename std::list<RenameHistory>::iterator hb_it =
910 historyBuffer[tid].end();
911
912 --hb_it;
913
914 if (historyBuffer[tid].empty()) {
915 DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid);
916 return;
917 } else if (hb_it->instSeqNum > inst_seq_num) {
918 DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure "
919 "that a syscall happened recently.\n", tid);
920 return;
921 }
922
923 // Commit all the renames up until (and including) the committed sequence
924 // number. Some or even all of the committed instructions may not have
925 // rename histories if they did not have destination registers that were
926 // renamed.
927 while (!historyBuffer[tid].empty() &&
928 hb_it != historyBuffer[tid].end() &&
929 hb_it->instSeqNum <= inst_seq_num) {
930
931 DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, "
932 "[sn:%lli].\n",
933 tid, hb_it->prevPhysReg, hb_it->instSeqNum);
934
935 // Don't free special phys regs like misc and zero regs, which
936 // can be recognized because the new mapping is the same as
937 // the old one.
938 if (hb_it->newPhysReg != hb_it->prevPhysReg) {
939 freeList->addReg(hb_it->prevPhysReg);
940 }
941
942 ++renameCommittedMaps;
943
944 historyBuffer[tid].erase(hb_it--);
945 }
946}
947
948template <class Impl>
949inline void
950DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid)
951{
952 ThreadContext *tc = inst->tcBase();
953 RenameMap *map = renameMap[tid];
954 unsigned num_src_regs = inst->numSrcRegs();
955
956 // Get the architectual register numbers from the source and
957 // operands, and redirect them to the right physical register.
958 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) {
959 RegIndex src_reg = inst->srcRegIdx(src_idx);
960 RegIndex rel_src_reg;
961 RegIndex flat_rel_src_reg;
962 PhysRegIndex renamed_reg;
963
964 switch (regIdxToClass(src_reg, &rel_src_reg)) {
965 case IntRegClass:
966 flat_rel_src_reg = tc->flattenIntIndex(rel_src_reg);
967 renamed_reg = map->lookupInt(flat_rel_src_reg);
968 intRenameLookups++;
969 break;
970
971 case FloatRegClass:
972 flat_rel_src_reg = tc->flattenFloatIndex(rel_src_reg);
973 renamed_reg = map->lookupFloat(flat_rel_src_reg);
974 fpRenameLookups++;
975 break;
976
| 70{
71 // @todo: Make into a parameter.
72 skidBufferMax = (2 * (decodeToRenameDelay * params->decodeWidth)) + renameWidth;
73}
74
75template <class Impl>
76std::string
77DefaultRename<Impl>::name() const
78{
79 return cpu->name() + ".rename";
80}
81
82template <class Impl>
83void
84DefaultRename<Impl>::regStats()
85{
86 renameSquashCycles
87 .name(name() + ".SquashCycles")
88 .desc("Number of cycles rename is squashing")
89 .prereq(renameSquashCycles);
90 renameIdleCycles
91 .name(name() + ".IdleCycles")
92 .desc("Number of cycles rename is idle")
93 .prereq(renameIdleCycles);
94 renameBlockCycles
95 .name(name() + ".BlockCycles")
96 .desc("Number of cycles rename is blocking")
97 .prereq(renameBlockCycles);
98 renameSerializeStallCycles
99 .name(name() + ".serializeStallCycles")
100 .desc("count of cycles rename stalled for serializing inst")
101 .flags(Stats::total);
102 renameRunCycles
103 .name(name() + ".RunCycles")
104 .desc("Number of cycles rename is running")
105 .prereq(renameIdleCycles);
106 renameUnblockCycles
107 .name(name() + ".UnblockCycles")
108 .desc("Number of cycles rename is unblocking")
109 .prereq(renameUnblockCycles);
110 renameRenamedInsts
111 .name(name() + ".RenamedInsts")
112 .desc("Number of instructions processed by rename")
113 .prereq(renameRenamedInsts);
114 renameSquashedInsts
115 .name(name() + ".SquashedInsts")
116 .desc("Number of squashed instructions processed by rename")
117 .prereq(renameSquashedInsts);
118 renameROBFullEvents
119 .name(name() + ".ROBFullEvents")
120 .desc("Number of times rename has blocked due to ROB full")
121 .prereq(renameROBFullEvents);
122 renameIQFullEvents
123 .name(name() + ".IQFullEvents")
124 .desc("Number of times rename has blocked due to IQ full")
125 .prereq(renameIQFullEvents);
126 renameLSQFullEvents
127 .name(name() + ".LSQFullEvents")
128 .desc("Number of times rename has blocked due to LSQ full")
129 .prereq(renameLSQFullEvents);
130 renameFullRegistersEvents
131 .name(name() + ".FullRegisterEvents")
132 .desc("Number of times there has been no free registers")
133 .prereq(renameFullRegistersEvents);
134 renameRenamedOperands
135 .name(name() + ".RenamedOperands")
136 .desc("Number of destination operands rename has renamed")
137 .prereq(renameRenamedOperands);
138 renameRenameLookups
139 .name(name() + ".RenameLookups")
140 .desc("Number of register rename lookups that rename has made")
141 .prereq(renameRenameLookups);
142 renameCommittedMaps
143 .name(name() + ".CommittedMaps")
144 .desc("Number of HB maps that are committed")
145 .prereq(renameCommittedMaps);
146 renameUndoneMaps
147 .name(name() + ".UndoneMaps")
148 .desc("Number of HB maps that are undone due to squashing")
149 .prereq(renameUndoneMaps);
150 renamedSerializing
151 .name(name() + ".serializingInsts")
152 .desc("count of serializing insts renamed")
153 .flags(Stats::total)
154 ;
155 renamedTempSerializing
156 .name(name() + ".tempSerializingInsts")
157 .desc("count of temporary serializing insts renamed")
158 .flags(Stats::total)
159 ;
160 renameSkidInsts
161 .name(name() + ".skidInsts")
162 .desc("count of insts added to the skid buffer")
163 .flags(Stats::total)
164 ;
165 intRenameLookups
166 .name(name() + ".int_rename_lookups")
167 .desc("Number of integer rename lookups")
168 .prereq(intRenameLookups);
169 fpRenameLookups
170 .name(name() + ".fp_rename_lookups")
171 .desc("Number of floating rename lookups")
172 .prereq(fpRenameLookups);
173}
174
175template <class Impl>
176void
177DefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
178{
179 timeBuffer = tb_ptr;
180
181 // Setup wire to read information from time buffer, from IEW stage.
182 fromIEW = timeBuffer->getWire(-iewToRenameDelay);
183
184 // Setup wire to read infromation from time buffer, from commit stage.
185 fromCommit = timeBuffer->getWire(-commitToRenameDelay);
186
187 // Setup wire to write information to previous stages.
188 toDecode = timeBuffer->getWire(0);
189}
190
191template <class Impl>
192void
193DefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
194{
195 renameQueue = rq_ptr;
196
197 // Setup wire to write information to future stages.
198 toIEW = renameQueue->getWire(0);
199}
200
201template <class Impl>
202void
203DefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
204{
205 decodeQueue = dq_ptr;
206
207 // Setup wire to get information from decode.
208 fromDecode = decodeQueue->getWire(-decodeToRenameDelay);
209}
210
211template <class Impl>
212void
213DefaultRename<Impl>::startupStage()
214{
215 resetStage();
216}
217
218template <class Impl>
219void
220DefaultRename<Impl>::resetStage()
221{
222 _status = Inactive;
223
224 resumeSerialize = false;
225 resumeUnblocking = false;
226
227 // Grab the number of free entries directly from the stages.
228 for (ThreadID tid = 0; tid < numThreads; tid++) {
229 renameStatus[tid] = Idle;
230
231 freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid);
232 freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid);
233 freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid);
234 emptyROB[tid] = true;
235
236 stalls[tid].iew = false;
237 stalls[tid].commit = false;
238 serializeInst[tid] = NULL;
239
240 instsInProgress[tid] = 0;
241
242 serializeOnNextInst[tid] = false;
243 }
244}
245
246template<class Impl>
247void
248DefaultRename<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
249{
250 activeThreads = at_ptr;
251}
252
253
254template <class Impl>
255void
256DefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[])
257{
258 for (ThreadID tid = 0; tid < numThreads; tid++)
259 renameMap[tid] = &rm_ptr[tid];
260}
261
262template <class Impl>
263void
264DefaultRename<Impl>::setFreeList(FreeList *fl_ptr)
265{
266 freeList = fl_ptr;
267}
268
269template<class Impl>
270void
271DefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard)
272{
273 scoreboard = _scoreboard;
274}
275
276template <class Impl>
277bool
278DefaultRename<Impl>::isDrained() const
279{
280 for (ThreadID tid = 0; tid < numThreads; tid++) {
281 if (instsInProgress[tid] != 0 ||
282 !historyBuffer[tid].empty() ||
283 !skidBuffer[tid].empty() ||
284 !insts[tid].empty())
285 return false;
286 }
287 return true;
288}
289
290template <class Impl>
291void
292DefaultRename<Impl>::takeOverFrom()
293{
294 resetStage();
295}
296
297template <class Impl>
298void
299DefaultRename<Impl>::drainSanityCheck() const
300{
301 for (ThreadID tid = 0; tid < numThreads; tid++) {
302 assert(historyBuffer[tid].empty());
303 assert(insts[tid].empty());
304 assert(skidBuffer[tid].empty());
305 assert(instsInProgress[tid] == 0);
306 }
307}
308
309template <class Impl>
310void
311DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, ThreadID tid)
312{
313 DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid);
314
315 // Clear the stall signal if rename was blocked or unblocking before.
316 // If it still needs to block, the blocking should happen the next
317 // cycle and there should be space to hold everything due to the squash.
318 if (renameStatus[tid] == Blocked ||
319 renameStatus[tid] == Unblocking) {
320 toDecode->renameUnblock[tid] = 1;
321
322 resumeSerialize = false;
323 serializeInst[tid] = NULL;
324 } else if (renameStatus[tid] == SerializeStall) {
325 if (serializeInst[tid]->seqNum <= squash_seq_num) {
326 DPRINTF(Rename, "Rename will resume serializing after squash\n");
327 resumeSerialize = true;
328 assert(serializeInst[tid]);
329 } else {
330 resumeSerialize = false;
331 toDecode->renameUnblock[tid] = 1;
332
333 serializeInst[tid] = NULL;
334 }
335 }
336
337 // Set the status to Squashing.
338 renameStatus[tid] = Squashing;
339
340 // Squash any instructions from decode.
341 unsigned squashCount = 0;
342
343 for (int i=0; i<fromDecode->size; i++) {
344 if (fromDecode->insts[i]->threadNumber == tid &&
345 fromDecode->insts[i]->seqNum > squash_seq_num) {
346 fromDecode->insts[i]->setSquashed();
347 wroteToTimeBuffer = true;
348 squashCount++;
349 }
350
351 }
352
353 // Clear the instruction list and skid buffer in case they have any
354 // insts in them.
355 insts[tid].clear();
356
357 // Clear the skid buffer in case it has any data in it.
358 skidBuffer[tid].clear();
359
360 doSquash(squash_seq_num, tid);
361}
362
363template <class Impl>
364void
365DefaultRename<Impl>::tick()
366{
367 wroteToTimeBuffer = false;
368
369 blockThisCycle = false;
370
371 bool status_change = false;
372
373 toIEWIndex = 0;
374
375 sortInsts();
376
377 list<ThreadID>::iterator threads = activeThreads->begin();
378 list<ThreadID>::iterator end = activeThreads->end();
379
380 // Check stall and squash signals.
381 while (threads != end) {
382 ThreadID tid = *threads++;
383
384 DPRINTF(Rename, "Processing [tid:%i]\n", tid);
385
386 status_change = checkSignalsAndUpdate(tid) || status_change;
387
388 rename(status_change, tid);
389 }
390
391 if (status_change) {
392 updateStatus();
393 }
394
395 if (wroteToTimeBuffer) {
396 DPRINTF(Activity, "Activity this cycle.\n");
397 cpu->activityThisCycle();
398 }
399
400 threads = activeThreads->begin();
401
402 while (threads != end) {
403 ThreadID tid = *threads++;
404
405 // If we committed this cycle then doneSeqNum will be > 0
406 if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
407 !fromCommit->commitInfo[tid].squash &&
408 renameStatus[tid] != Squashing) {
409
410 removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum,
411 tid);
412 }
413 }
414
415 // @todo: make into updateProgress function
416 for (ThreadID tid = 0; tid < numThreads; tid++) {
417 instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched;
418
419 assert(instsInProgress[tid] >=0);
420 }
421
422}
423
424template<class Impl>
425void
426DefaultRename<Impl>::rename(bool &status_change, ThreadID tid)
427{
428 // If status is Running or idle,
429 // call renameInsts()
430 // If status is Unblocking,
431 // buffer any instructions coming from decode
432 // continue trying to empty skid buffer
433 // check if stall conditions have passed
434
435 if (renameStatus[tid] == Blocked) {
436 ++renameBlockCycles;
437 } else if (renameStatus[tid] == Squashing) {
438 ++renameSquashCycles;
439 } else if (renameStatus[tid] == SerializeStall) {
440 ++renameSerializeStallCycles;
441 // If we are currently in SerializeStall and resumeSerialize
442 // was set, then that means that we are resuming serializing
443 // this cycle. Tell the previous stages to block.
444 if (resumeSerialize) {
445 resumeSerialize = false;
446 block(tid);
447 toDecode->renameUnblock[tid] = false;
448 }
449 } else if (renameStatus[tid] == Unblocking) {
450 if (resumeUnblocking) {
451 block(tid);
452 resumeUnblocking = false;
453 toDecode->renameUnblock[tid] = false;
454 }
455 }
456
457 if (renameStatus[tid] == Running ||
458 renameStatus[tid] == Idle) {
459 DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run "
460 "stage.\n", tid);
461
462 renameInsts(tid);
463 } else if (renameStatus[tid] == Unblocking) {
464 renameInsts(tid);
465
466 if (validInsts()) {
467 // Add the current inputs to the skid buffer so they can be
468 // reprocessed when this stage unblocks.
469 skidInsert(tid);
470 }
471
472 // If we switched over to blocking, then there's a potential for
473 // an overall status change.
474 status_change = unblock(tid) || status_change || blockThisCycle;
475 }
476}
477
478template <class Impl>
479void
480DefaultRename<Impl>::renameInsts(ThreadID tid)
481{
482 // Instructions can be either in the skid buffer or the queue of
483 // instructions coming from decode, depending on the status.
484 int insts_available = renameStatus[tid] == Unblocking ?
485 skidBuffer[tid].size() : insts[tid].size();
486
487 // Check the decode queue to see if instructions are available.
488 // If there are no available instructions to rename, then do nothing.
489 if (insts_available == 0) {
490 DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n",
491 tid);
492 // Should I change status to idle?
493 ++renameIdleCycles;
494 return;
495 } else if (renameStatus[tid] == Unblocking) {
496 ++renameUnblockCycles;
497 } else if (renameStatus[tid] == Running) {
498 ++renameRunCycles;
499 }
500
501 DynInstPtr inst;
502
503 // Will have to do a different calculation for the number of free
504 // entries.
505 int free_rob_entries = calcFreeROBEntries(tid);
506 int free_iq_entries = calcFreeIQEntries(tid);
507 int free_lsq_entries = calcFreeLSQEntries(tid);
508 int min_free_entries = free_rob_entries;
509
510 FullSource source = ROB;
511
512 if (free_iq_entries < min_free_entries) {
513 min_free_entries = free_iq_entries;
514 source = IQ;
515 }
516
517 if (free_lsq_entries < min_free_entries) {
518 min_free_entries = free_lsq_entries;
519 source = LSQ;
520 }
521
522 // Check if there's any space left.
523 if (min_free_entries <= 0) {
524 DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ "
525 "entries.\n"
526 "ROB has %i free entries.\n"
527 "IQ has %i free entries.\n"
528 "LSQ has %i free entries.\n",
529 tid,
530 free_rob_entries,
531 free_iq_entries,
532 free_lsq_entries);
533
534 blockThisCycle = true;
535
536 block(tid);
537
538 incrFullStat(source);
539
540 return;
541 } else if (min_free_entries < insts_available) {
542 DPRINTF(Rename, "[tid:%u]: Will have to block this cycle."
543 "%i insts available, but only %i insts can be "
544 "renamed due to ROB/IQ/LSQ limits.\n",
545 tid, insts_available, min_free_entries);
546
547 insts_available = min_free_entries;
548
549 blockThisCycle = true;
550
551 incrFullStat(source);
552 }
553
554 InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ?
555 skidBuffer[tid] : insts[tid];
556
557 DPRINTF(Rename, "[tid:%u]: %i available instructions to "
558 "send iew.\n", tid, insts_available);
559
560 DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts "
561 "dispatched to IQ last cycle.\n",
562 tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched);
563
564 // Handle serializing the next instruction if necessary.
565 if (serializeOnNextInst[tid]) {
566 if (emptyROB[tid] && instsInProgress[tid] == 0) {
567 // ROB already empty; no need to serialize.
568 serializeOnNextInst[tid] = false;
569 } else if (!insts_to_rename.empty()) {
570 insts_to_rename.front()->setSerializeBefore();
571 }
572 }
573
574 int renamed_insts = 0;
575
576 while (insts_available > 0 && toIEWIndex < renameWidth) {
577 DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid);
578
579 assert(!insts_to_rename.empty());
580
581 inst = insts_to_rename.front();
582
583 insts_to_rename.pop_front();
584
585 if (renameStatus[tid] == Unblocking) {
586 DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%s from rename "
587 "skidBuffer\n", tid, inst->seqNum, inst->pcState());
588 }
589
590 if (inst->isSquashed()) {
591 DPRINTF(Rename, "[tid:%u]: instruction %i with PC %s is "
592 "squashed, skipping.\n", tid, inst->seqNum,
593 inst->pcState());
594
595 ++renameSquashedInsts;
596
597 // Decrement how many instructions are available.
598 --insts_available;
599
600 continue;
601 }
602
603 DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with "
604 "PC %s.\n", tid, inst->seqNum, inst->pcState());
605
606 // Check here to make sure there are enough destination registers
607 // to rename to. Otherwise block.
608 if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) {
609 DPRINTF(Rename, "Blocking due to lack of free "
610 "physical registers to rename to.\n");
611 blockThisCycle = true;
612 insts_to_rename.push_front(inst);
613 ++renameFullRegistersEvents;
614
615 break;
616 }
617
618 // Handle serializeAfter/serializeBefore instructions.
619 // serializeAfter marks the next instruction as serializeBefore.
620 // serializeBefore makes the instruction wait in rename until the ROB
621 // is empty.
622
623 // In this model, IPR accesses are serialize before
624 // instructions, and store conditionals are serialize after
625 // instructions. This is mainly due to lack of support for
626 // out-of-order operations of either of those classes of
627 // instructions.
628 if ((inst->isIprAccess() || inst->isSerializeBefore()) &&
629 !inst->isSerializeHandled()) {
630 DPRINTF(Rename, "Serialize before instruction encountered.\n");
631
632 if (!inst->isTempSerializeBefore()) {
633 renamedSerializing++;
634 inst->setSerializeHandled();
635 } else {
636 renamedTempSerializing++;
637 }
638
639 // Change status over to SerializeStall so that other stages know
640 // what this is blocked on.
641 renameStatus[tid] = SerializeStall;
642
643 serializeInst[tid] = inst;
644
645 blockThisCycle = true;
646
647 break;
648 } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) &&
649 !inst->isSerializeHandled()) {
650 DPRINTF(Rename, "Serialize after instruction encountered.\n");
651
652 renamedSerializing++;
653
654 inst->setSerializeHandled();
655
656 serializeAfter(insts_to_rename, tid);
657 }
658
659 renameSrcRegs(inst, inst->threadNumber);
660
661 renameDestRegs(inst, inst->threadNumber);
662
663 ++renamed_insts;
664
665
666 // Put instruction in rename queue.
667 toIEW->insts[toIEWIndex] = inst;
668 ++(toIEW->size);
669
670 // Increment which instruction we're on.
671 ++toIEWIndex;
672
673 // Decrement how many instructions are available.
674 --insts_available;
675 }
676
677 instsInProgress[tid] += renamed_insts;
678 renameRenamedInsts += renamed_insts;
679
680 // If we wrote to the time buffer, record this.
681 if (toIEWIndex) {
682 wroteToTimeBuffer = true;
683 }
684
685 // Check if there's any instructions left that haven't yet been renamed.
686 // If so then block.
687 if (insts_available) {
688 blockThisCycle = true;
689 }
690
691 if (blockThisCycle) {
692 block(tid);
693 toDecode->renameUnblock[tid] = false;
694 }
695}
696
697template<class Impl>
698void
699DefaultRename<Impl>::skidInsert(ThreadID tid)
700{
701 DynInstPtr inst = NULL;
702
703 while (!insts[tid].empty()) {
704 inst = insts[tid].front();
705
706 insts[tid].pop_front();
707
708 assert(tid == inst->threadNumber);
709
710 DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC: %s into Rename "
711 "skidBuffer\n", tid, inst->seqNum, inst->pcState());
712
713 ++renameSkidInsts;
714
715 skidBuffer[tid].push_back(inst);
716 }
717
718 if (skidBuffer[tid].size() > skidBufferMax)
719 {
720 typename InstQueue::iterator it;
721 warn("Skidbuffer contents:\n");
722 for(it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++)
723 {
724 warn("[tid:%u]: %s [sn:%i].\n", tid,
725 (*it)->staticInst->disassemble(inst->instAddr()),
726 (*it)->seqNum);
727 }
728 panic("Skidbuffer Exceeded Max Size");
729 }
730}
731
732template <class Impl>
733void
734DefaultRename<Impl>::sortInsts()
735{
736 int insts_from_decode = fromDecode->size;
737 for (int i = 0; i < insts_from_decode; ++i) {
738 DynInstPtr inst = fromDecode->insts[i];
739 insts[inst->threadNumber].push_back(inst);
740#if TRACING_ON
741 if (DTRACE(O3PipeView)) {
742 inst->renameTick = curTick() - inst->fetchTick;
743 }
744#endif
745 }
746}
747
748template<class Impl>
749bool
750DefaultRename<Impl>::skidsEmpty()
751{
752 list<ThreadID>::iterator threads = activeThreads->begin();
753 list<ThreadID>::iterator end = activeThreads->end();
754
755 while (threads != end) {
756 ThreadID tid = *threads++;
757
758 if (!skidBuffer[tid].empty())
759 return false;
760 }
761
762 return true;
763}
764
765template<class Impl>
766void
767DefaultRename<Impl>::updateStatus()
768{
769 bool any_unblocking = false;
770
771 list<ThreadID>::iterator threads = activeThreads->begin();
772 list<ThreadID>::iterator end = activeThreads->end();
773
774 while (threads != end) {
775 ThreadID tid = *threads++;
776
777 if (renameStatus[tid] == Unblocking) {
778 any_unblocking = true;
779 break;
780 }
781 }
782
783 // Rename will have activity if it's unblocking.
784 if (any_unblocking) {
785 if (_status == Inactive) {
786 _status = Active;
787
788 DPRINTF(Activity, "Activating stage.\n");
789
790 cpu->activateStage(O3CPU::RenameIdx);
791 }
792 } else {
793 // If it's not unblocking, then rename will not have any internal
794 // activity. Switch it to inactive.
795 if (_status == Active) {
796 _status = Inactive;
797 DPRINTF(Activity, "Deactivating stage.\n");
798
799 cpu->deactivateStage(O3CPU::RenameIdx);
800 }
801 }
802}
803
804template <class Impl>
805bool
806DefaultRename<Impl>::block(ThreadID tid)
807{
808 DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid);
809
810 // Add the current inputs onto the skid buffer, so they can be
811 // reprocessed when this stage unblocks.
812 skidInsert(tid);
813
814 // Only signal backwards to block if the previous stages do not think
815 // rename is already blocked.
816 if (renameStatus[tid] != Blocked) {
817 // If resumeUnblocking is set, we unblocked during the squash,
818 // but now we're have unblocking status. We need to tell earlier
819 // stages to block.
820 if (resumeUnblocking || renameStatus[tid] != Unblocking) {
821 toDecode->renameBlock[tid] = true;
822 toDecode->renameUnblock[tid] = false;
823 wroteToTimeBuffer = true;
824 }
825
826 // Rename can not go from SerializeStall to Blocked, otherwise
827 // it would not know to complete the serialize stall.
828 if (renameStatus[tid] != SerializeStall) {
829 // Set status to Blocked.
830 renameStatus[tid] = Blocked;
831 return true;
832 }
833 }
834
835 return false;
836}
837
838template <class Impl>
839bool
840DefaultRename<Impl>::unblock(ThreadID tid)
841{
842 DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid);
843
844 // Rename is done unblocking if the skid buffer is empty.
845 if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) {
846
847 DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid);
848
849 toDecode->renameUnblock[tid] = true;
850 wroteToTimeBuffer = true;
851
852 renameStatus[tid] = Running;
853 return true;
854 }
855
856 return false;
857}
858
859template <class Impl>
860void
861DefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, ThreadID tid)
862{
863 typename std::list<RenameHistory>::iterator hb_it =
864 historyBuffer[tid].begin();
865
866 // After a syscall squashes everything, the history buffer may be empty
867 // but the ROB may still be squashing instructions.
868 if (historyBuffer[tid].empty()) {
869 return;
870 }
871
872 // Go through the most recent instructions, undoing the mappings
873 // they did and freeing up the registers.
874 while (!historyBuffer[tid].empty() &&
875 hb_it->instSeqNum > squashed_seq_num) {
876 assert(hb_it != historyBuffer[tid].end());
877
878 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
879 "number %i.\n", tid, hb_it->instSeqNum);
880
881 // Undo the rename mapping only if it was really a change.
882 // Special regs that are not really renamed (like misc regs
883 // and the zero reg) can be recognized because the new mapping
884 // is the same as the old one. While it would be merely a
885 // waste of time to update the rename table, we definitely
886 // don't want to put these on the free list.
887 if (hb_it->newPhysReg != hb_it->prevPhysReg) {
888 // Tell the rename map to set the architected register to the
889 // previous physical register that it was renamed to.
890 renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
891
892 // Put the renamed physical register back on the free list.
893 freeList->addReg(hb_it->newPhysReg);
894 }
895
896 historyBuffer[tid].erase(hb_it++);
897
898 ++renameUndoneMaps;
899 }
900}
901
902template<class Impl>
903void
904DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid)
905{
906 DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the "
907 "history buffer %u (size=%i), until [sn:%lli].\n",
908 tid, tid, historyBuffer[tid].size(), inst_seq_num);
909
910 typename std::list<RenameHistory>::iterator hb_it =
911 historyBuffer[tid].end();
912
913 --hb_it;
914
915 if (historyBuffer[tid].empty()) {
916 DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid);
917 return;
918 } else if (hb_it->instSeqNum > inst_seq_num) {
919 DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure "
920 "that a syscall happened recently.\n", tid);
921 return;
922 }
923
924 // Commit all the renames up until (and including) the committed sequence
925 // number. Some or even all of the committed instructions may not have
926 // rename histories if they did not have destination registers that were
927 // renamed.
928 while (!historyBuffer[tid].empty() &&
929 hb_it != historyBuffer[tid].end() &&
930 hb_it->instSeqNum <= inst_seq_num) {
931
932 DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, "
933 "[sn:%lli].\n",
934 tid, hb_it->prevPhysReg, hb_it->instSeqNum);
935
936 // Don't free special phys regs like misc and zero regs, which
937 // can be recognized because the new mapping is the same as
938 // the old one.
939 if (hb_it->newPhysReg != hb_it->prevPhysReg) {
940 freeList->addReg(hb_it->prevPhysReg);
941 }
942
943 ++renameCommittedMaps;
944
945 historyBuffer[tid].erase(hb_it--);
946 }
947}
948
949template <class Impl>
950inline void
951DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid)
952{
953 ThreadContext *tc = inst->tcBase();
954 RenameMap *map = renameMap[tid];
955 unsigned num_src_regs = inst->numSrcRegs();
956
957 // Get the architectual register numbers from the source and
958 // operands, and redirect them to the right physical register.
959 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) {
960 RegIndex src_reg = inst->srcRegIdx(src_idx);
961 RegIndex rel_src_reg;
962 RegIndex flat_rel_src_reg;
963 PhysRegIndex renamed_reg;
964
965 switch (regIdxToClass(src_reg, &rel_src_reg)) {
966 case IntRegClass:
967 flat_rel_src_reg = tc->flattenIntIndex(rel_src_reg);
968 renamed_reg = map->lookupInt(flat_rel_src_reg);
969 intRenameLookups++;
970 break;
971
972 case FloatRegClass:
973 flat_rel_src_reg = tc->flattenFloatIndex(rel_src_reg);
974 renamed_reg = map->lookupFloat(flat_rel_src_reg);
975 fpRenameLookups++;
976 break;
977
|
| 978 case CCRegClass:
979 flat_rel_src_reg = tc->flattenCCIndex(rel_src_reg);
980 renamed_reg = map->lookupCC(flat_rel_src_reg);
981 break;
982
|
977 case MiscRegClass:
978 // misc regs don't get flattened
979 flat_rel_src_reg = rel_src_reg;
980 renamed_reg = map->lookupMisc(flat_rel_src_reg);
981 break;
982
983 default:
984 panic("Reg index is out of bound: %d.", src_reg);
985 }
986
987 DPRINTF(Rename, "[tid:%u]: Looking up %s arch reg %i (flattened %i), "
988 "got phys reg %i\n", tid, RegClassStrings[regIdxToClass(src_reg)],
989 (int)src_reg, (int)flat_rel_src_reg, (int)renamed_reg);
990
991 inst->renameSrcReg(src_idx, renamed_reg);
992
993 // See if the register is ready or not.
994 if (scoreboard->getReg(renamed_reg)) {
995 DPRINTF(Rename, "[tid:%u]: Register %d is ready.\n",
996 tid, renamed_reg);
997
998 inst->markSrcRegReady(src_idx);
999 } else {
1000 DPRINTF(Rename, "[tid:%u]: Register %d is not ready.\n",
1001 tid, renamed_reg);
1002 }
1003
1004 ++renameRenameLookups;
1005 }
1006}
1007
1008template <class Impl>
1009inline void
1010DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid)
1011{
1012 ThreadContext *tc = inst->tcBase();
1013 RenameMap *map = renameMap[tid];
1014 unsigned num_dest_regs = inst->numDestRegs();
1015
1016 // Rename the destination registers.
1017 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) {
1018 RegIndex dest_reg = inst->destRegIdx(dest_idx);
1019 RegIndex rel_dest_reg;
1020 RegIndex flat_rel_dest_reg;
1021 RegIndex flat_uni_dest_reg;
1022 typename RenameMap::RenameInfo rename_result;
1023
1024 switch (regIdxToClass(dest_reg, &rel_dest_reg)) {
1025 case IntRegClass:
1026 flat_rel_dest_reg = tc->flattenIntIndex(rel_dest_reg);
1027 rename_result = map->renameInt(flat_rel_dest_reg);
1028 flat_uni_dest_reg = flat_rel_dest_reg; // 1:1 mapping
1029 break;
1030
1031 case FloatRegClass:
1032 flat_rel_dest_reg = tc->flattenFloatIndex(rel_dest_reg);
1033 rename_result = map->renameFloat(flat_rel_dest_reg);
1034 flat_uni_dest_reg = flat_rel_dest_reg + TheISA::FP_Reg_Base;
1035 break;
1036
| 983 case MiscRegClass:
984 // misc regs don't get flattened
985 flat_rel_src_reg = rel_src_reg;
986 renamed_reg = map->lookupMisc(flat_rel_src_reg);
987 break;
988
989 default:
990 panic("Reg index is out of bound: %d.", src_reg);
991 }
992
993 DPRINTF(Rename, "[tid:%u]: Looking up %s arch reg %i (flattened %i), "
994 "got phys reg %i\n", tid, RegClassStrings[regIdxToClass(src_reg)],
995 (int)src_reg, (int)flat_rel_src_reg, (int)renamed_reg);
996
997 inst->renameSrcReg(src_idx, renamed_reg);
998
999 // See if the register is ready or not.
1000 if (scoreboard->getReg(renamed_reg)) {
1001 DPRINTF(Rename, "[tid:%u]: Register %d is ready.\n",
1002 tid, renamed_reg);
1003
1004 inst->markSrcRegReady(src_idx);
1005 } else {
1006 DPRINTF(Rename, "[tid:%u]: Register %d is not ready.\n",
1007 tid, renamed_reg);
1008 }
1009
1010 ++renameRenameLookups;
1011 }
1012}
1013
1014template <class Impl>
1015inline void
1016DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid)
1017{
1018 ThreadContext *tc = inst->tcBase();
1019 RenameMap *map = renameMap[tid];
1020 unsigned num_dest_regs = inst->numDestRegs();
1021
1022 // Rename the destination registers.
1023 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) {
1024 RegIndex dest_reg = inst->destRegIdx(dest_idx);
1025 RegIndex rel_dest_reg;
1026 RegIndex flat_rel_dest_reg;
1027 RegIndex flat_uni_dest_reg;
1028 typename RenameMap::RenameInfo rename_result;
1029
1030 switch (regIdxToClass(dest_reg, &rel_dest_reg)) {
1031 case IntRegClass:
1032 flat_rel_dest_reg = tc->flattenIntIndex(rel_dest_reg);
1033 rename_result = map->renameInt(flat_rel_dest_reg);
1034 flat_uni_dest_reg = flat_rel_dest_reg; // 1:1 mapping
1035 break;
1036
1037 case FloatRegClass:
1038 flat_rel_dest_reg = tc->flattenFloatIndex(rel_dest_reg);
1039 rename_result = map->renameFloat(flat_rel_dest_reg);
1040 flat_uni_dest_reg = flat_rel_dest_reg + TheISA::FP_Reg_Base;
1041 break;
1042
|
| 1043 case CCRegClass:
1044 flat_rel_dest_reg = tc->flattenCCIndex(rel_dest_reg);
1045 rename_result = map->renameCC(flat_rel_dest_reg);
1046 flat_uni_dest_reg = flat_rel_dest_reg + TheISA::CC_Reg_Base;
1047 break;
1048
|
1037 case MiscRegClass:
1038 // misc regs don't get flattened
1039 flat_rel_dest_reg = rel_dest_reg;
1040 rename_result = map->renameMisc(flat_rel_dest_reg);
1041 flat_uni_dest_reg = flat_rel_dest_reg + TheISA::Misc_Reg_Base;
1042 break;
1043
1044 default:
1045 panic("Reg index is out of bound: %d.", dest_reg);
1046 }
1047
1048 inst->flattenDestReg(dest_idx, flat_uni_dest_reg);
1049
1050 // Mark Scoreboard entry as not ready
1051 scoreboard->unsetReg(rename_result.first);
1052
1053 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical "
1054 "reg %i.\n", tid, (int)flat_rel_dest_reg,
1055 (int)rename_result.first);
1056
1057 // Record the rename information so that a history can be kept.
1058 RenameHistory hb_entry(inst->seqNum, flat_uni_dest_reg,
1059 rename_result.first,
1060 rename_result.second);
1061
1062 historyBuffer[tid].push_front(hb_entry);
1063
1064 DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer "
1065 "(size=%i), [sn:%lli].\n",tid,
1066 historyBuffer[tid].size(),
1067 (*historyBuffer[tid].begin()).instSeqNum);
1068
1069 // Tell the instruction to rename the appropriate destination
1070 // register (dest_idx) to the new physical register
1071 // (rename_result.first), and record the previous physical
1072 // register that the same logical register was renamed to
1073 // (rename_result.second).
1074 inst->renameDestReg(dest_idx,
1075 rename_result.first,
1076 rename_result.second);
1077
1078 ++renameRenamedOperands;
1079 }
1080}
1081
1082template <class Impl>
1083inline int
1084DefaultRename<Impl>::calcFreeROBEntries(ThreadID tid)
1085{
1086 int num_free = freeEntries[tid].robEntries -
1087 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1088
1089 //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free);
1090
1091 return num_free;
1092}
1093
1094template <class Impl>
1095inline int
1096DefaultRename<Impl>::calcFreeIQEntries(ThreadID tid)
1097{
1098 int num_free = freeEntries[tid].iqEntries -
1099 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1100
1101 //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free);
1102
1103 return num_free;
1104}
1105
1106template <class Impl>
1107inline int
1108DefaultRename<Impl>::calcFreeLSQEntries(ThreadID tid)
1109{
1110 int num_free = freeEntries[tid].lsqEntries -
1111 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ);
1112
1113 //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free);
1114
1115 return num_free;
1116}
1117
1118template <class Impl>
1119unsigned
1120DefaultRename<Impl>::validInsts()
1121{
1122 unsigned inst_count = 0;
1123
1124 for (int i=0; i<fromDecode->size; i++) {
1125 if (!fromDecode->insts[i]->isSquashed())
1126 inst_count++;
1127 }
1128
1129 return inst_count;
1130}
1131
1132template <class Impl>
1133void
1134DefaultRename<Impl>::readStallSignals(ThreadID tid)
1135{
1136 if (fromIEW->iewBlock[tid]) {
1137 stalls[tid].iew = true;
1138 }
1139
1140 if (fromIEW->iewUnblock[tid]) {
1141 assert(stalls[tid].iew);
1142 stalls[tid].iew = false;
1143 }
1144
1145 if (fromCommit->commitBlock[tid]) {
1146 stalls[tid].commit = true;
1147 }
1148
1149 if (fromCommit->commitUnblock[tid]) {
1150 assert(stalls[tid].commit);
1151 stalls[tid].commit = false;
1152 }
1153}
1154
1155template <class Impl>
1156bool
1157DefaultRename<Impl>::checkStall(ThreadID tid)
1158{
1159 bool ret_val = false;
1160
1161 if (stalls[tid].iew) {
1162 DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid);
1163 ret_val = true;
1164 } else if (stalls[tid].commit) {
1165 DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid);
1166 ret_val = true;
1167 } else if (calcFreeROBEntries(tid) <= 0) {
1168 DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid);
1169 ret_val = true;
1170 } else if (calcFreeIQEntries(tid) <= 0) {
1171 DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid);
1172 ret_val = true;
1173 } else if (calcFreeLSQEntries(tid) <= 0) {
1174 DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid);
1175 ret_val = true;
1176 } else if (renameMap[tid]->numFreeEntries() <= 0) {
1177 DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid);
1178 ret_val = true;
1179 } else if (renameStatus[tid] == SerializeStall &&
1180 (!emptyROB[tid] || instsInProgress[tid])) {
1181 DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not "
1182 "empty.\n",
1183 tid);
1184 ret_val = true;
1185 }
1186
1187 return ret_val;
1188}
1189
1190template <class Impl>
1191void
1192DefaultRename<Impl>::readFreeEntries(ThreadID tid)
1193{
1194 if (fromIEW->iewInfo[tid].usedIQ)
1195 freeEntries[tid].iqEntries = fromIEW->iewInfo[tid].freeIQEntries;
1196
1197 if (fromIEW->iewInfo[tid].usedLSQ)
1198 freeEntries[tid].lsqEntries = fromIEW->iewInfo[tid].freeLSQEntries;
1199
1200 if (fromCommit->commitInfo[tid].usedROB) {
1201 freeEntries[tid].robEntries =
1202 fromCommit->commitInfo[tid].freeROBEntries;
1203 emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB;
1204 }
1205
1206 DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n",
1207 tid,
1208 freeEntries[tid].iqEntries,
1209 freeEntries[tid].robEntries,
1210 freeEntries[tid].lsqEntries);
1211
1212 DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n",
1213 tid, instsInProgress[tid]);
1214}
1215
1216template <class Impl>
1217bool
1218DefaultRename<Impl>::checkSignalsAndUpdate(ThreadID tid)
1219{
1220 // Check if there's a squash signal, squash if there is
1221 // Check stall signals, block if necessary.
1222 // If status was blocked
1223 // check if stall conditions have passed
1224 // if so then go to unblocking
1225 // If status was Squashing
1226 // check if squashing is not high. Switch to running this cycle.
1227 // If status was serialize stall
1228 // check if ROB is empty and no insts are in flight to the ROB
1229
1230 readFreeEntries(tid);
1231 readStallSignals(tid);
1232
1233 if (fromCommit->commitInfo[tid].squash) {
1234 DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from "
1235 "commit.\n", tid);
1236
1237 squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
1238
1239 return true;
1240 }
1241
1242 if (fromCommit->commitInfo[tid].robSquashing) {
1243 DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid);
1244
1245 renameStatus[tid] = Squashing;
1246
1247 return true;
1248 }
1249
1250 if (checkStall(tid)) {
1251 return block(tid);
1252 }
1253
1254 if (renameStatus[tid] == Blocked) {
1255 DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n",
1256 tid);
1257
1258 renameStatus[tid] = Unblocking;
1259
1260 unblock(tid);
1261
1262 return true;
1263 }
1264
1265 if (renameStatus[tid] == Squashing) {
1266 // Switch status to running if rename isn't being told to block or
1267 // squash this cycle.
1268 if (resumeSerialize) {
1269 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n",
1270 tid);
1271
1272 renameStatus[tid] = SerializeStall;
1273 return true;
1274 } else if (resumeUnblocking) {
1275 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n",
1276 tid);
1277 renameStatus[tid] = Unblocking;
1278 return true;
1279 } else {
1280 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n",
1281 tid);
1282
1283 renameStatus[tid] = Running;
1284 return false;
1285 }
1286 }
1287
1288 if (renameStatus[tid] == SerializeStall) {
1289 // Stall ends once the ROB is free.
1290 DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to "
1291 "unblocking.\n", tid);
1292
1293 DynInstPtr serial_inst = serializeInst[tid];
1294
1295 renameStatus[tid] = Unblocking;
1296
1297 unblock(tid);
1298
1299 DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with "
1300 "PC %s.\n", tid, serial_inst->seqNum, serial_inst->pcState());
1301
1302 // Put instruction into queue here.
1303 serial_inst->clearSerializeBefore();
1304
1305 if (!skidBuffer[tid].empty()) {
1306 skidBuffer[tid].push_front(serial_inst);
1307 } else {
1308 insts[tid].push_front(serial_inst);
1309 }
1310
1311 DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename."
1312 " Adding to front of list.\n", tid);
1313
1314 serializeInst[tid] = NULL;
1315
1316 return true;
1317 }
1318
1319 // If we've reached this point, we have not gotten any signals that
1320 // cause rename to change its status. Rename remains the same as before.
1321 return false;
1322}
1323
1324template<class Impl>
1325void
1326DefaultRename<Impl>::serializeAfter(InstQueue &inst_list, ThreadID tid)
1327{
1328 if (inst_list.empty()) {
1329 // Mark a bit to say that I must serialize on the next instruction.
1330 serializeOnNextInst[tid] = true;
1331 return;
1332 }
1333
1334 // Set the next instruction as serializing.
1335 inst_list.front()->setSerializeBefore();
1336}
1337
1338template <class Impl>
1339inline void
1340DefaultRename<Impl>::incrFullStat(const FullSource &source)
1341{
1342 switch (source) {
1343 case ROB:
1344 ++renameROBFullEvents;
1345 break;
1346 case IQ:
1347 ++renameIQFullEvents;
1348 break;
1349 case LSQ:
1350 ++renameLSQFullEvents;
1351 break;
1352 default:
1353 panic("Rename full stall stat should be incremented for a reason!");
1354 break;
1355 }
1356}
1357
1358template <class Impl>
1359void
1360DefaultRename<Impl>::dumpHistory()
1361{
1362 typename std::list<RenameHistory>::iterator buf_it;
1363
1364 for (ThreadID tid = 0; tid < numThreads; tid++) {
1365
1366 buf_it = historyBuffer[tid].begin();
1367
1368 while (buf_it != historyBuffer[tid].end()) {
1369 cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys "
1370 "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg,
1371 (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg);
1372
1373 buf_it++;
1374 }
1375 }
1376}
| 1049 case MiscRegClass:
1050 // misc regs don't get flattened
1051 flat_rel_dest_reg = rel_dest_reg;
1052 rename_result = map->renameMisc(flat_rel_dest_reg);
1053 flat_uni_dest_reg = flat_rel_dest_reg + TheISA::Misc_Reg_Base;
1054 break;
1055
1056 default:
1057 panic("Reg index is out of bound: %d.", dest_reg);
1058 }
1059
1060 inst->flattenDestReg(dest_idx, flat_uni_dest_reg);
1061
1062 // Mark Scoreboard entry as not ready
1063 scoreboard->unsetReg(rename_result.first);
1064
1065 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical "
1066 "reg %i.\n", tid, (int)flat_rel_dest_reg,
1067 (int)rename_result.first);
1068
1069 // Record the rename information so that a history can be kept.
1070 RenameHistory hb_entry(inst->seqNum, flat_uni_dest_reg,
1071 rename_result.first,
1072 rename_result.second);
1073
1074 historyBuffer[tid].push_front(hb_entry);
1075
1076 DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer "
1077 "(size=%i), [sn:%lli].\n",tid,
1078 historyBuffer[tid].size(),
1079 (*historyBuffer[tid].begin()).instSeqNum);
1080
1081 // Tell the instruction to rename the appropriate destination
1082 // register (dest_idx) to the new physical register
1083 // (rename_result.first), and record the previous physical
1084 // register that the same logical register was renamed to
1085 // (rename_result.second).
1086 inst->renameDestReg(dest_idx,
1087 rename_result.first,
1088 rename_result.second);
1089
1090 ++renameRenamedOperands;
1091 }
1092}
1093
1094template <class Impl>
1095inline int
1096DefaultRename<Impl>::calcFreeROBEntries(ThreadID tid)
1097{
1098 int num_free = freeEntries[tid].robEntries -
1099 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1100
1101 //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free);
1102
1103 return num_free;
1104}
1105
1106template <class Impl>
1107inline int
1108DefaultRename<Impl>::calcFreeIQEntries(ThreadID tid)
1109{
1110 int num_free = freeEntries[tid].iqEntries -
1111 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1112
1113 //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free);
1114
1115 return num_free;
1116}
1117
1118template <class Impl>
1119inline int
1120DefaultRename<Impl>::calcFreeLSQEntries(ThreadID tid)
1121{
1122 int num_free = freeEntries[tid].lsqEntries -
1123 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ);
1124
1125 //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free);
1126
1127 return num_free;
1128}
1129
1130template <class Impl>
1131unsigned
1132DefaultRename<Impl>::validInsts()
1133{
1134 unsigned inst_count = 0;
1135
1136 for (int i=0; i<fromDecode->size; i++) {
1137 if (!fromDecode->insts[i]->isSquashed())
1138 inst_count++;
1139 }
1140
1141 return inst_count;
1142}
1143
1144template <class Impl>
1145void
1146DefaultRename<Impl>::readStallSignals(ThreadID tid)
1147{
1148 if (fromIEW->iewBlock[tid]) {
1149 stalls[tid].iew = true;
1150 }
1151
1152 if (fromIEW->iewUnblock[tid]) {
1153 assert(stalls[tid].iew);
1154 stalls[tid].iew = false;
1155 }
1156
1157 if (fromCommit->commitBlock[tid]) {
1158 stalls[tid].commit = true;
1159 }
1160
1161 if (fromCommit->commitUnblock[tid]) {
1162 assert(stalls[tid].commit);
1163 stalls[tid].commit = false;
1164 }
1165}
1166
1167template <class Impl>
1168bool
1169DefaultRename<Impl>::checkStall(ThreadID tid)
1170{
1171 bool ret_val = false;
1172
1173 if (stalls[tid].iew) {
1174 DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid);
1175 ret_val = true;
1176 } else if (stalls[tid].commit) {
1177 DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid);
1178 ret_val = true;
1179 } else if (calcFreeROBEntries(tid) <= 0) {
1180 DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid);
1181 ret_val = true;
1182 } else if (calcFreeIQEntries(tid) <= 0) {
1183 DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid);
1184 ret_val = true;
1185 } else if (calcFreeLSQEntries(tid) <= 0) {
1186 DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid);
1187 ret_val = true;
1188 } else if (renameMap[tid]->numFreeEntries() <= 0) {
1189 DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid);
1190 ret_val = true;
1191 } else if (renameStatus[tid] == SerializeStall &&
1192 (!emptyROB[tid] || instsInProgress[tid])) {
1193 DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not "
1194 "empty.\n",
1195 tid);
1196 ret_val = true;
1197 }
1198
1199 return ret_val;
1200}
1201
1202template <class Impl>
1203void
1204DefaultRename<Impl>::readFreeEntries(ThreadID tid)
1205{
1206 if (fromIEW->iewInfo[tid].usedIQ)
1207 freeEntries[tid].iqEntries = fromIEW->iewInfo[tid].freeIQEntries;
1208
1209 if (fromIEW->iewInfo[tid].usedLSQ)
1210 freeEntries[tid].lsqEntries = fromIEW->iewInfo[tid].freeLSQEntries;
1211
1212 if (fromCommit->commitInfo[tid].usedROB) {
1213 freeEntries[tid].robEntries =
1214 fromCommit->commitInfo[tid].freeROBEntries;
1215 emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB;
1216 }
1217
1218 DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n",
1219 tid,
1220 freeEntries[tid].iqEntries,
1221 freeEntries[tid].robEntries,
1222 freeEntries[tid].lsqEntries);
1223
1224 DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n",
1225 tid, instsInProgress[tid]);
1226}
1227
1228template <class Impl>
1229bool
1230DefaultRename<Impl>::checkSignalsAndUpdate(ThreadID tid)
1231{
1232 // Check if there's a squash signal, squash if there is
1233 // Check stall signals, block if necessary.
1234 // If status was blocked
1235 // check if stall conditions have passed
1236 // if so then go to unblocking
1237 // If status was Squashing
1238 // check if squashing is not high. Switch to running this cycle.
1239 // If status was serialize stall
1240 // check if ROB is empty and no insts are in flight to the ROB
1241
1242 readFreeEntries(tid);
1243 readStallSignals(tid);
1244
1245 if (fromCommit->commitInfo[tid].squash) {
1246 DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from "
1247 "commit.\n", tid);
1248
1249 squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
1250
1251 return true;
1252 }
1253
1254 if (fromCommit->commitInfo[tid].robSquashing) {
1255 DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid);
1256
1257 renameStatus[tid] = Squashing;
1258
1259 return true;
1260 }
1261
1262 if (checkStall(tid)) {
1263 return block(tid);
1264 }
1265
1266 if (renameStatus[tid] == Blocked) {
1267 DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n",
1268 tid);
1269
1270 renameStatus[tid] = Unblocking;
1271
1272 unblock(tid);
1273
1274 return true;
1275 }
1276
1277 if (renameStatus[tid] == Squashing) {
1278 // Switch status to running if rename isn't being told to block or
1279 // squash this cycle.
1280 if (resumeSerialize) {
1281 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n",
1282 tid);
1283
1284 renameStatus[tid] = SerializeStall;
1285 return true;
1286 } else if (resumeUnblocking) {
1287 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n",
1288 tid);
1289 renameStatus[tid] = Unblocking;
1290 return true;
1291 } else {
1292 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n",
1293 tid);
1294
1295 renameStatus[tid] = Running;
1296 return false;
1297 }
1298 }
1299
1300 if (renameStatus[tid] == SerializeStall) {
1301 // Stall ends once the ROB is free.
1302 DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to "
1303 "unblocking.\n", tid);
1304
1305 DynInstPtr serial_inst = serializeInst[tid];
1306
1307 renameStatus[tid] = Unblocking;
1308
1309 unblock(tid);
1310
1311 DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with "
1312 "PC %s.\n", tid, serial_inst->seqNum, serial_inst->pcState());
1313
1314 // Put instruction into queue here.
1315 serial_inst->clearSerializeBefore();
1316
1317 if (!skidBuffer[tid].empty()) {
1318 skidBuffer[tid].push_front(serial_inst);
1319 } else {
1320 insts[tid].push_front(serial_inst);
1321 }
1322
1323 DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename."
1324 " Adding to front of list.\n", tid);
1325
1326 serializeInst[tid] = NULL;
1327
1328 return true;
1329 }
1330
1331 // If we've reached this point, we have not gotten any signals that
1332 // cause rename to change its status. Rename remains the same as before.
1333 return false;
1334}
1335
1336template<class Impl>
1337void
1338DefaultRename<Impl>::serializeAfter(InstQueue &inst_list, ThreadID tid)
1339{
1340 if (inst_list.empty()) {
1341 // Mark a bit to say that I must serialize on the next instruction.
1342 serializeOnNextInst[tid] = true;
1343 return;
1344 }
1345
1346 // Set the next instruction as serializing.
1347 inst_list.front()->setSerializeBefore();
1348}
1349
1350template <class Impl>
1351inline void
1352DefaultRename<Impl>::incrFullStat(const FullSource &source)
1353{
1354 switch (source) {
1355 case ROB:
1356 ++renameROBFullEvents;
1357 break;
1358 case IQ:
1359 ++renameIQFullEvents;
1360 break;
1361 case LSQ:
1362 ++renameLSQFullEvents;
1363 break;
1364 default:
1365 panic("Rename full stall stat should be incremented for a reason!");
1366 break;
1367 }
1368}
1369
1370template <class Impl>
1371void
1372DefaultRename<Impl>::dumpHistory()
1373{
1374 typename std::list<RenameHistory>::iterator buf_it;
1375
1376 for (ThreadID tid = 0; tid < numThreads; tid++) {
1377
1378 buf_it = historyBuffer[tid].begin();
1379
1380 while (buf_it != historyBuffer[tid].end()) {
1381 cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys "
1382 "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg,
1383 (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg);
1384
1385 buf_it++;
1386 }
1387 }
1388}
|