1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 * Korey Sewell
42 */
43
44#include <list>
45
46#include "arch/isa_traits.hh"
47#include "arch/registers.hh"
48#include "config/the_isa.hh"
49#include "cpu/o3/rename.hh"
50#include "debug/Activity.hh"
51#include "debug/Rename.hh"
52#include "params/DerivO3CPU.hh"
53
54using namespace std;
55
56template <class Impl>
57DefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params)
58 : cpu(_cpu),
59 iewToRenameDelay(params->iewToRenameDelay),
60 decodeToRenameDelay(params->decodeToRenameDelay),
61 commitToRenameDelay(params->commitToRenameDelay),
62 renameWidth(params->renameWidth),
63 commitWidth(params->commitWidth),
64 resumeSerialize(false),
65 resumeUnblocking(false),
66 numThreads(params->numThreads),
67 maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs)
68{
69 _status = Inactive;
70
71 for (ThreadID tid = 0; tid < numThreads; tid++) {
72 renameStatus[tid] = Idle;
73
74 freeEntries[tid].iqEntries = 0;
75 freeEntries[tid].lsqEntries = 0;
76 freeEntries[tid].robEntries = 0;
77
78 stalls[tid].iew = false;
79 stalls[tid].commit = false;
80 serializeInst[tid] = NULL;
81
82 instsInProgress[tid] = 0;
83
84 emptyROB[tid] = true;
85
86 serializeOnNextInst[tid] = false;
87 }
88
89 // @todo: Make into a parameter.
90 skidBufferMax = (2 * (iewToRenameDelay * params->decodeWidth)) + renameWidth;
91}
92
93template <class Impl>
94std::string
95DefaultRename<Impl>::name() const
96{
97 return cpu->name() + ".rename";
98}
99
100template <class Impl>
101void
102DefaultRename<Impl>::regStats()
103{
104 renameSquashCycles
105 .name(name() + ".SquashCycles")
106 .desc("Number of cycles rename is squashing")
107 .prereq(renameSquashCycles);
108 renameIdleCycles
109 .name(name() + ".IdleCycles")
110 .desc("Number of cycles rename is idle")
111 .prereq(renameIdleCycles);
112 renameBlockCycles
113 .name(name() + ".BlockCycles")
114 .desc("Number of cycles rename is blocking")
115 .prereq(renameBlockCycles);
116 renameSerializeStallCycles
117 .name(name() + ".serializeStallCycles")
118 .desc("count of cycles rename stalled for serializing inst")
119 .flags(Stats::total);
120 renameRunCycles
121 .name(name() + ".RunCycles")
122 .desc("Number of cycles rename is running")
123 .prereq(renameIdleCycles);
124 renameUnblockCycles
125 .name(name() + ".UnblockCycles")
126 .desc("Number of cycles rename is unblocking")
127 .prereq(renameUnblockCycles);
128 renameRenamedInsts
129 .name(name() + ".RenamedInsts")
130 .desc("Number of instructions processed by rename")
131 .prereq(renameRenamedInsts);
132 renameSquashedInsts
133 .name(name() + ".SquashedInsts")
134 .desc("Number of squashed instructions processed by rename")
135 .prereq(renameSquashedInsts);
136 renameROBFullEvents
137 .name(name() + ".ROBFullEvents")
138 .desc("Number of times rename has blocked due to ROB full")
139 .prereq(renameROBFullEvents);
140 renameIQFullEvents
141 .name(name() + ".IQFullEvents")
142 .desc("Number of times rename has blocked due to IQ full")
143 .prereq(renameIQFullEvents);
144 renameLSQFullEvents
145 .name(name() + ".LSQFullEvents")
146 .desc("Number of times rename has blocked due to LSQ full")
147 .prereq(renameLSQFullEvents);
148 renameFullRegistersEvents
149 .name(name() + ".FullRegisterEvents")
150 .desc("Number of times there has been no free registers")
151 .prereq(renameFullRegistersEvents);
152 renameRenamedOperands
153 .name(name() + ".RenamedOperands")
154 .desc("Number of destination operands rename has renamed")
155 .prereq(renameRenamedOperands);
156 renameRenameLookups
157 .name(name() + ".RenameLookups")
158 .desc("Number of register rename lookups that rename has made")
159 .prereq(renameRenameLookups);
160 renameCommittedMaps
161 .name(name() + ".CommittedMaps")
162 .desc("Number of HB maps that are committed")
163 .prereq(renameCommittedMaps);
164 renameUndoneMaps
165 .name(name() + ".UndoneMaps")
166 .desc("Number of HB maps that are undone due to squashing")
167 .prereq(renameUndoneMaps);
168 renamedSerializing
169 .name(name() + ".serializingInsts")
170 .desc("count of serializing insts renamed")
171 .flags(Stats::total)
172 ;
173 renamedTempSerializing
174 .name(name() + ".tempSerializingInsts")
175 .desc("count of temporary serializing insts renamed")
176 .flags(Stats::total)
177 ;
178 renameSkidInsts
179 .name(name() + ".skidInsts")
180 .desc("count of insts added to the skid buffer")
181 .flags(Stats::total)
182 ;
183 intRenameLookups
184 .name(name() + ".int_rename_lookups")
185 .desc("Number of integer rename lookups")
186 .prereq(intRenameLookups);
187 fpRenameLookups
188 .name(name() + ".fp_rename_lookups")
189 .desc("Number of floating rename lookups")
190 .prereq(fpRenameLookups);
191}
192
193template <class Impl>
194void
195DefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
196{
197 timeBuffer = tb_ptr;
198
199 // Setup wire to read information from time buffer, from IEW stage.
200 fromIEW = timeBuffer->getWire(-iewToRenameDelay);
201
202 // Setup wire to read infromation from time buffer, from commit stage.
203 fromCommit = timeBuffer->getWire(-commitToRenameDelay);
204
205 // Setup wire to write information to previous stages.
206 toDecode = timeBuffer->getWire(0);
207}
208
209template <class Impl>
210void
211DefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
212{
213 renameQueue = rq_ptr;
214
215 // Setup wire to write information to future stages.
216 toIEW = renameQueue->getWire(0);
217}
218
219template <class Impl>
220void
221DefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
222{
223 decodeQueue = dq_ptr;
224
225 // Setup wire to get information from decode.
226 fromDecode = decodeQueue->getWire(-decodeToRenameDelay);
227}
228
229template <class Impl>
230void
231DefaultRename<Impl>::initStage()
232{
233 // Grab the number of free entries directly from the stages.
234 for (ThreadID tid = 0; tid < numThreads; tid++) {
235 freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid);
236 freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid);
237 freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid);
238 emptyROB[tid] = true;
239 }
240}
241
242template<class Impl>
243void
244DefaultRename<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
245{
246 activeThreads = at_ptr;
247}
248
249
250template <class Impl>
251void
252DefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[])
253{
254 for (ThreadID tid = 0; tid < numThreads; tid++)
255 renameMap[tid] = &rm_ptr[tid];
256}
257
258template <class Impl>
259void
260DefaultRename<Impl>::setFreeList(FreeList *fl_ptr)
261{
262 freeList = fl_ptr;
263}
264
265template<class Impl>
266void
267DefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard)
268{
269 scoreboard = _scoreboard;
270}
271
272template <class Impl>
273bool
274DefaultRename<Impl>::drain()
275{
276 // Rename is ready to switch out at any time.
277 cpu->signalDrained();
278 return true;
279}
280
281template <class Impl>
282void
283DefaultRename<Impl>::switchOut()
284{
285 // Clear any state, fix up the rename map.
286 for (ThreadID tid = 0; tid < numThreads; tid++) {
287 typename std::list<RenameHistory>::iterator hb_it =
288 historyBuffer[tid].begin();
289
290 while (!historyBuffer[tid].empty()) {
291 assert(hb_it != historyBuffer[tid].end());
292
293 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
294 "number %i.\n", tid, (*hb_it).instSeqNum);
295
296 // Tell the rename map to set the architected register to the
297 // previous physical register that it was renamed to.
298 renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
299
300 // Put the renamed physical register back on the free list.
301 freeList->addReg(hb_it->newPhysReg);
302
303 // Be sure to mark its register as ready if it's a misc register.
304 if (hb_it->newPhysReg >= maxPhysicalRegs) {
305 scoreboard->setReg(hb_it->newPhysReg);
306 }
307
308 historyBuffer[tid].erase(hb_it++);
309 }
310 insts[tid].clear();
311 skidBuffer[tid].clear();
312 }
313}
314
315template <class Impl>
316void
317DefaultRename<Impl>::takeOverFrom()
318{
319 _status = Inactive;
320 initStage();
321
322 // Reset all state prior to taking over from the other CPU.
323 for (ThreadID tid = 0; tid < numThreads; tid++) {
324 renameStatus[tid] = Idle;
325
326 stalls[tid].iew = false;
327 stalls[tid].commit = false;
328 serializeInst[tid] = NULL;
329
330 instsInProgress[tid] = 0;
331
332 emptyROB[tid] = true;
333
334 serializeOnNextInst[tid] = false;
335 }
336}
337
338template <class Impl>
339void
340DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, ThreadID tid)
341{
342 DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid);
343
344 // Clear the stall signal if rename was blocked or unblocking before.
345 // If it still needs to block, the blocking should happen the next
346 // cycle and there should be space to hold everything due to the squash.
347 if (renameStatus[tid] == Blocked ||
348 renameStatus[tid] == Unblocking) {
349 toDecode->renameUnblock[tid] = 1;
350
351 resumeSerialize = false;
352 serializeInst[tid] = NULL;
353 } else if (renameStatus[tid] == SerializeStall) {
354 if (serializeInst[tid]->seqNum <= squash_seq_num) {
355 DPRINTF(Rename, "Rename will resume serializing after squash\n");
356 resumeSerialize = true;
357 assert(serializeInst[tid]);
358 } else {
359 resumeSerialize = false;
360 toDecode->renameUnblock[tid] = 1;
361
362 serializeInst[tid] = NULL;
363 }
364 }
365
366 // Set the status to Squashing.
367 renameStatus[tid] = Squashing;
368
369 // Squash any instructions from decode.
370 unsigned squashCount = 0;
371
372 for (int i=0; i<fromDecode->size; i++) {
373 if (fromDecode->insts[i]->threadNumber == tid &&
374 fromDecode->insts[i]->seqNum > squash_seq_num) {
375 fromDecode->insts[i]->setSquashed();
376 wroteToTimeBuffer = true;
377 squashCount++;
378 }
379
380 }
381
382 // Clear the instruction list and skid buffer in case they have any
383 // insts in them.
384 insts[tid].clear();
385
386 // Clear the skid buffer in case it has any data in it.
387 skidBuffer[tid].clear();
388
389 doSquash(squash_seq_num, tid);
390}
391
392template <class Impl>
393void
394DefaultRename<Impl>::tick()
395{
396 wroteToTimeBuffer = false;
397
398 blockThisCycle = false;
399
400 bool status_change = false;
401
402 toIEWIndex = 0;
403
404 sortInsts();
405
406 list<ThreadID>::iterator threads = activeThreads->begin();
407 list<ThreadID>::iterator end = activeThreads->end();
408
409 // Check stall and squash signals.
410 while (threads != end) {
411 ThreadID tid = *threads++;
412
413 DPRINTF(Rename, "Processing [tid:%i]\n", tid);
414
415 status_change = checkSignalsAndUpdate(tid) || status_change;
416
417 rename(status_change, tid);
418 }
419
420 if (status_change) {
421 updateStatus();
422 }
423
424 if (wroteToTimeBuffer) {
425 DPRINTF(Activity, "Activity this cycle.\n");
426 cpu->activityThisCycle();
427 }
428
429 threads = activeThreads->begin();
430
431 while (threads != end) {
432 ThreadID tid = *threads++;
433
434 // If we committed this cycle then doneSeqNum will be > 0
435 if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
436 !fromCommit->commitInfo[tid].squash &&
437 renameStatus[tid] != Squashing) {
438
439 removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum,
440 tid);
441 }
442 }
443
444 // @todo: make into updateProgress function
445 for (ThreadID tid = 0; tid < numThreads; tid++) {
446 instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched;
447
448 assert(instsInProgress[tid] >=0);
449 }
450
451}
452
453template<class Impl>
454void
455DefaultRename<Impl>::rename(bool &status_change, ThreadID tid)
456{
457 // If status is Running or idle,
458 // call renameInsts()
459 // If status is Unblocking,
460 // buffer any instructions coming from decode
461 // continue trying to empty skid buffer
462 // check if stall conditions have passed
463
464 if (renameStatus[tid] == Blocked) {
465 ++renameBlockCycles;
466 } else if (renameStatus[tid] == Squashing) {
467 ++renameSquashCycles;
468 } else if (renameStatus[tid] == SerializeStall) {
469 ++renameSerializeStallCycles;
470 // If we are currently in SerializeStall and resumeSerialize
471 // was set, then that means that we are resuming serializing
472 // this cycle. Tell the previous stages to block.
473 if (resumeSerialize) {
474 resumeSerialize = false;
475 block(tid);
476 toDecode->renameUnblock[tid] = false;
477 }
478 } else if (renameStatus[tid] == Unblocking) {
479 if (resumeUnblocking) {
480 block(tid);
481 resumeUnblocking = false;
482 toDecode->renameUnblock[tid] = false;
483 }
484 }
485
486 if (renameStatus[tid] == Running ||
487 renameStatus[tid] == Idle) {
488 DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run "
489 "stage.\n", tid);
490
491 renameInsts(tid);
492 } else if (renameStatus[tid] == Unblocking) {
493 renameInsts(tid);
494
495 if (validInsts()) {
496 // Add the current inputs to the skid buffer so they can be
497 // reprocessed when this stage unblocks.
498 skidInsert(tid);
499 }
500
501 // If we switched over to blocking, then there's a potential for
502 // an overall status change.
503 status_change = unblock(tid) || status_change || blockThisCycle;
504 }
505}
506
507template <class Impl>
508void
509DefaultRename<Impl>::renameInsts(ThreadID tid)
510{
511 // Instructions can be either in the skid buffer or the queue of
512 // instructions coming from decode, depending on the status.
513 int insts_available = renameStatus[tid] == Unblocking ?
514 skidBuffer[tid].size() : insts[tid].size();
515
516 // Check the decode queue to see if instructions are available.
517 // If there are no available instructions to rename, then do nothing.
518 if (insts_available == 0) {
519 DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n",
520 tid);
521 // Should I change status to idle?
522 ++renameIdleCycles;
523 return;
524 } else if (renameStatus[tid] == Unblocking) {
525 ++renameUnblockCycles;
526 } else if (renameStatus[tid] == Running) {
527 ++renameRunCycles;
528 }
529
530 DynInstPtr inst;
531
532 // Will have to do a different calculation for the number of free
533 // entries.
534 int free_rob_entries = calcFreeROBEntries(tid);
535 int free_iq_entries = calcFreeIQEntries(tid);
536 int free_lsq_entries = calcFreeLSQEntries(tid);
537 int min_free_entries = free_rob_entries;
538
539 FullSource source = ROB;
540
541 if (free_iq_entries < min_free_entries) {
542 min_free_entries = free_iq_entries;
543 source = IQ;
544 }
545
546 if (free_lsq_entries < min_free_entries) {
547 min_free_entries = free_lsq_entries;
548 source = LSQ;
549 }
550
551 // Check if there's any space left.
552 if (min_free_entries <= 0) {
553 DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ "
554 "entries.\n"
555 "ROB has %i free entries.\n"
556 "IQ has %i free entries.\n"
557 "LSQ has %i free entries.\n",
558 tid,
559 free_rob_entries,
560 free_iq_entries,
561 free_lsq_entries);
562
563 blockThisCycle = true;
564
565 block(tid);
566
567 incrFullStat(source);
568
569 return;
570 } else if (min_free_entries < insts_available) {
571 DPRINTF(Rename, "[tid:%u]: Will have to block this cycle."
572 "%i insts available, but only %i insts can be "
573 "renamed due to ROB/IQ/LSQ limits.\n",
574 tid, insts_available, min_free_entries);
575
576 insts_available = min_free_entries;
577
578 blockThisCycle = true;
579
580 incrFullStat(source);
581 }
582
583 InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ?
584 skidBuffer[tid] : insts[tid];
585
586 DPRINTF(Rename, "[tid:%u]: %i available instructions to "
587 "send iew.\n", tid, insts_available);
588
589 DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts "
590 "dispatched to IQ last cycle.\n",
591 tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched);
592
593 // Handle serializing the next instruction if necessary.
594 if (serializeOnNextInst[tid]) {
595 if (emptyROB[tid] && instsInProgress[tid] == 0) {
596 // ROB already empty; no need to serialize.
597 serializeOnNextInst[tid] = false;
598 } else if (!insts_to_rename.empty()) {
599 insts_to_rename.front()->setSerializeBefore();
600 }
601 }
602
603 int renamed_insts = 0;
604
605 while (insts_available > 0 && toIEWIndex < renameWidth) {
606 DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid);
607
608 assert(!insts_to_rename.empty());
609
610 inst = insts_to_rename.front();
611
612 insts_to_rename.pop_front();
613
614 if (renameStatus[tid] == Unblocking) {
615 DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%s from rename "
616 "skidBuffer\n", tid, inst->seqNum, inst->pcState());
617 }
618
619 if (inst->isSquashed()) {
620 DPRINTF(Rename, "[tid:%u]: instruction %i with PC %s is "
621 "squashed, skipping.\n", tid, inst->seqNum,
622 inst->pcState());
623
624 ++renameSquashedInsts;
625
626 // Decrement how many instructions are available.
627 --insts_available;
628
629 continue;
630 }
631
632 DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with "
633 "PC %s.\n", tid, inst->seqNum, inst->pcState());
634
635 // Handle serializeAfter/serializeBefore instructions.
636 // serializeAfter marks the next instruction as serializeBefore.
637 // serializeBefore makes the instruction wait in rename until the ROB
638 // is empty.
639
640 // In this model, IPR accesses are serialize before
641 // instructions, and store conditionals are serialize after
642 // instructions. This is mainly due to lack of support for
643 // out-of-order operations of either of those classes of
644 // instructions.
645 if ((inst->isIprAccess() || inst->isSerializeBefore()) &&
646 !inst->isSerializeHandled()) {
647 DPRINTF(Rename, "Serialize before instruction encountered.\n");
648
649 if (!inst->isTempSerializeBefore()) {
650 renamedSerializing++;
651 inst->setSerializeHandled();
652 } else {
653 renamedTempSerializing++;
654 }
655
656 // Change status over to SerializeStall so that other stages know
657 // what this is blocked on.
658 renameStatus[tid] = SerializeStall;
659
660 serializeInst[tid] = inst;
661
662 blockThisCycle = true;
663
664 break;
665 } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) &&
666 !inst->isSerializeHandled()) {
667 DPRINTF(Rename, "Serialize after instruction encountered.\n");
668
669 renamedSerializing++;
670
671 inst->setSerializeHandled();
672
673 serializeAfter(insts_to_rename, tid);
674 }
675
676 // Check here to make sure there are enough destination registers
677 // to rename to. Otherwise block.
678 if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) {
679 DPRINTF(Rename, "Blocking due to lack of free "
680 "physical registers to rename to.\n");
681 blockThisCycle = true;
682 insts_to_rename.push_front(inst);
683 ++renameFullRegistersEvents;
684
685 break;
686 }
687
688 renameSrcRegs(inst, inst->threadNumber);
689
690 renameDestRegs(inst, inst->threadNumber);
691
692 ++renamed_insts;
693
694#if TRACING_ON
695 inst->renameTick = curTick();
696#endif
697
698 // Put instruction in rename queue.
699 toIEW->insts[toIEWIndex] = inst;
700 ++(toIEW->size);
701
702 // Increment which instruction we're on.
703 ++toIEWIndex;
704
705 // Decrement how many instructions are available.
706 --insts_available;
707 }
708
709 instsInProgress[tid] += renamed_insts;
710 renameRenamedInsts += renamed_insts;
711
712 // If we wrote to the time buffer, record this.
713 if (toIEWIndex) {
714 wroteToTimeBuffer = true;
715 }
716
717 // Check if there's any instructions left that haven't yet been renamed.
718 // If so then block.
719 if (insts_available) {
720 blockThisCycle = true;
721 }
722
723 if (blockThisCycle) {
724 block(tid);
725 toDecode->renameUnblock[tid] = false;
726 }
727}
728
729template<class Impl>
730void
731DefaultRename<Impl>::skidInsert(ThreadID tid)
732{
733 DynInstPtr inst = NULL;
734
735 while (!insts[tid].empty()) {
736 inst = insts[tid].front();
737
738 insts[tid].pop_front();
739
740 assert(tid == inst->threadNumber);
741
742 DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC: %s into Rename "
743 "skidBuffer\n", tid, inst->seqNum, inst->pcState());
744
745 ++renameSkidInsts;
746
747 skidBuffer[tid].push_back(inst);
748 }
749
750 if (skidBuffer[tid].size() > skidBufferMax)
751 {
752 typename InstQueue::iterator it;
753 warn("Skidbuffer contents:\n");
754 for(it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++)
755 {
756 warn("[tid:%u]: %s [sn:%i].\n", tid,
757 (*it)->staticInst->disassemble(inst->instAddr()),
758 (*it)->seqNum);
759 }
760 panic("Skidbuffer Exceeded Max Size");
761 }
762}
763
764template <class Impl>
765void
766DefaultRename<Impl>::sortInsts()
767{
768 int insts_from_decode = fromDecode->size;
769#ifdef DEBUG
770 for (ThreadID tid = 0; tid < numThreads; tid++)
771 assert(insts[tid].empty());
772#endif
773 for (int i = 0; i < insts_from_decode; ++i) {
774 DynInstPtr inst = fromDecode->insts[i];
775 insts[inst->threadNumber].push_back(inst);
776 }
777}
778
779template<class Impl>
780bool
781DefaultRename<Impl>::skidsEmpty()
782{
783 list<ThreadID>::iterator threads = activeThreads->begin();
784 list<ThreadID>::iterator end = activeThreads->end();
785
786 while (threads != end) {
787 ThreadID tid = *threads++;
788
789 if (!skidBuffer[tid].empty())
790 return false;
791 }
792
793 return true;
794}
795
796template<class Impl>
797void
798DefaultRename<Impl>::updateStatus()
799{
800 bool any_unblocking = false;
801
802 list<ThreadID>::iterator threads = activeThreads->begin();
803 list<ThreadID>::iterator end = activeThreads->end();
804
805 while (threads != end) {
806 ThreadID tid = *threads++;
807
808 if (renameStatus[tid] == Unblocking) {
809 any_unblocking = true;
810 break;
811 }
812 }
813
814 // Rename will have activity if it's unblocking.
815 if (any_unblocking) {
816 if (_status == Inactive) {
817 _status = Active;
818
819 DPRINTF(Activity, "Activating stage.\n");
820
821 cpu->activateStage(O3CPU::RenameIdx);
822 }
823 } else {
824 // If it's not unblocking, then rename will not have any internal
825 // activity. Switch it to inactive.
826 if (_status == Active) {
827 _status = Inactive;
828 DPRINTF(Activity, "Deactivating stage.\n");
829
830 cpu->deactivateStage(O3CPU::RenameIdx);
831 }
832 }
833}
834
835template <class Impl>
836bool
837DefaultRename<Impl>::block(ThreadID tid)
838{
839 DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid);
840
841 // Add the current inputs onto the skid buffer, so they can be
842 // reprocessed when this stage unblocks.
843 skidInsert(tid);
844
845 // Only signal backwards to block if the previous stages do not think
846 // rename is already blocked.
847 if (renameStatus[tid] != Blocked) {
848 // If resumeUnblocking is set, we unblocked during the squash,
849 // but now we're have unblocking status. We need to tell earlier
850 // stages to block.
851 if (resumeUnblocking || renameStatus[tid] != Unblocking) {
852 toDecode->renameBlock[tid] = true;
853 toDecode->renameUnblock[tid] = false;
854 wroteToTimeBuffer = true;
855 }
856
857 // Rename can not go from SerializeStall to Blocked, otherwise
858 // it would not know to complete the serialize stall.
859 if (renameStatus[tid] != SerializeStall) {
860 // Set status to Blocked.
861 renameStatus[tid] = Blocked;
862 return true;
863 }
864 }
865
866 return false;
867}
868
869template <class Impl>
870bool
871DefaultRename<Impl>::unblock(ThreadID tid)
872{
873 DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid);
874
875 // Rename is done unblocking if the skid buffer is empty.
876 if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) {
877
878 DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid);
879
880 toDecode->renameUnblock[tid] = true;
881 wroteToTimeBuffer = true;
882
883 renameStatus[tid] = Running;
884 return true;
885 }
886
887 return false;
888}
889
890template <class Impl>
891void
892DefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, ThreadID tid)
893{
894 typename std::list<RenameHistory>::iterator hb_it =
895 historyBuffer[tid].begin();
896
897 // After a syscall squashes everything, the history buffer may be empty
898 // but the ROB may still be squashing instructions.
899 if (historyBuffer[tid].empty()) {
900 return;
901 }
902
903 // Go through the most recent instructions, undoing the mappings
904 // they did and freeing up the registers.
905 while (!historyBuffer[tid].empty() &&
906 (*hb_it).instSeqNum > squashed_seq_num) {
907 assert(hb_it != historyBuffer[tid].end());
908
909 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
910 "number %i.\n", tid, (*hb_it).instSeqNum);
911
912 // Tell the rename map to set the architected register to the
913 // previous physical register that it was renamed to.
914 renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
915
916 // Put the renamed physical register back on the free list.
917 freeList->addReg(hb_it->newPhysReg);
918
919 // Be sure to mark its register as ready if it's a misc register.
920 if (hb_it->newPhysReg >= maxPhysicalRegs) {
921 scoreboard->setReg(hb_it->newPhysReg);
922 }
923
924 historyBuffer[tid].erase(hb_it++);
925
926 ++renameUndoneMaps;
927 }
928}
929
930template<class Impl>
931void
932DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid)
933{
934 DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the "
935 "history buffer %u (size=%i), until [sn:%lli].\n",
936 tid, tid, historyBuffer[tid].size(), inst_seq_num);
937
938 typename std::list<RenameHistory>::iterator hb_it =
939 historyBuffer[tid].end();
940
941 --hb_it;
942
943 if (historyBuffer[tid].empty()) {
944 DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid);
945 return;
946 } else if (hb_it->instSeqNum > inst_seq_num) {
947 DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure "
948 "that a syscall happened recently.\n", tid);
949 return;
950 }
951
952 // Commit all the renames up until (and including) the committed sequence
953 // number. Some or even all of the committed instructions may not have
954 // rename histories if they did not have destination registers that were
955 // renamed.
956 while (!historyBuffer[tid].empty() &&
957 hb_it != historyBuffer[tid].end() &&
958 (*hb_it).instSeqNum <= inst_seq_num) {
959
960 DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, "
961 "[sn:%lli].\n",
962 tid, (*hb_it).prevPhysReg, (*hb_it).instSeqNum);
963
964 freeList->addReg((*hb_it).prevPhysReg);
965 ++renameCommittedMaps;
966
967 historyBuffer[tid].erase(hb_it--);
968 }
969}
970
971template <class Impl>
972inline void
973DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid)
974{
975 assert(renameMap[tid] != 0);
976
977 unsigned num_src_regs = inst->numSrcRegs();
978
979 // Get the architectual register numbers from the source and
980 // destination operands, and redirect them to the right register.
981 // Will need to mark dependencies though.
982 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) {
983 RegIndex src_reg = inst->srcRegIdx(src_idx);
984 RegIndex flat_src_reg = src_reg;
985 if (src_reg < TheISA::FP_Base_DepTag) {
986 flat_src_reg = inst->tcBase()->flattenIntIndex(src_reg);
987 DPRINTF(Rename, "Flattening index %d to %d.\n",
988 (int)src_reg, (int)flat_src_reg);
989 } else if (src_reg < TheISA::Ctrl_Base_DepTag) {
990 src_reg = src_reg - TheISA::FP_Base_DepTag;
991 flat_src_reg = inst->tcBase()->flattenFloatIndex(src_reg);
992 DPRINTF(Rename, "Flattening index %d to %d.\n",
993 (int)src_reg, (int)flat_src_reg);
994 flat_src_reg += TheISA::NumIntRegs;
995 } else if (src_reg < TheISA::Max_DepTag) {
996 flat_src_reg = src_reg - TheISA::Ctrl_Base_DepTag +
997 TheISA::NumFloatRegs + TheISA::NumIntRegs;
998 DPRINTF(Rename, "Adjusting reg index from %d to %d.\n",
999 src_reg, flat_src_reg);
1000 } else {
1001 panic("Reg index is out of bound: %d.", src_reg);
1002 }
1003
1004 inst->flattenSrcReg(src_idx, flat_src_reg);
1005
1006 // Look up the source registers to get the phys. register they've
1007 // been renamed to, and set the sources to those registers.
1008 PhysRegIndex renamed_reg = renameMap[tid]->lookup(flat_src_reg);
1009
1010 DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got "
1011 "physical reg %i.\n", tid, (int)flat_src_reg,
1012 (int)renamed_reg);
1013
1014 inst->renameSrcReg(src_idx, renamed_reg);
1015
1016 // See if the register is ready or not.
1017 if (scoreboard->getReg(renamed_reg) == true) {
1018 DPRINTF(Rename, "[tid:%u]: Register %d is ready.\n",
1019 tid, renamed_reg);
1020
1021 inst->markSrcRegReady(src_idx);
1022 } else {
1023 DPRINTF(Rename, "[tid:%u]: Register %d is not ready.\n",
1024 tid, renamed_reg);
1025 }
1026
1027 ++renameRenameLookups;
1028 inst->isFloating() ? fpRenameLookups++ : intRenameLookups++;
1029 }
1030}
1031
1032template <class Impl>
1033inline void
1034DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid)
1035{
1036 typename RenameMap::RenameInfo rename_result;
1037
1038 unsigned num_dest_regs = inst->numDestRegs();
1039
1040 // Rename the destination registers.
1041 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) {
1042 RegIndex dest_reg = inst->destRegIdx(dest_idx);
1043 RegIndex flat_dest_reg = dest_reg;
1044 if (dest_reg < TheISA::FP_Base_DepTag) {
1045 // Integer registers are flattened.
1046 flat_dest_reg = inst->tcBase()->flattenIntIndex(dest_reg);
1047 DPRINTF(Rename, "Flattening index %d to %d.\n",
1048 (int)dest_reg, (int)flat_dest_reg);
1049 } else if (dest_reg < TheISA::Ctrl_Base_DepTag) {
1050 dest_reg = dest_reg - TheISA::FP_Base_DepTag;
1051 flat_dest_reg = inst->tcBase()->flattenFloatIndex(dest_reg);
1052 DPRINTF(Rename, "Flattening index %d to %d.\n",
1053 (int)dest_reg, (int)flat_dest_reg);
1054 flat_dest_reg += TheISA::NumIntRegs;
1055 } else if (dest_reg < TheISA::Max_DepTag) {
1056 // Floating point and Miscellaneous registers need their indexes
1057 // adjusted to account for the expanded number of flattened int regs.
1058 flat_dest_reg = dest_reg - TheISA::Ctrl_Base_DepTag +
1059 TheISA::NumIntRegs + TheISA::NumFloatRegs;
1060 DPRINTF(Rename, "Adjusting reg index from %d to %d.\n",
1061 dest_reg, flat_dest_reg);
1062 } else {
1063 panic("Reg index is out of bound: %d.", dest_reg);
1064 }
1065
1066 inst->flattenDestReg(dest_idx, flat_dest_reg);
1067
1068 // Get the physical register that the destination will be
1069 // renamed to.
1070 rename_result = renameMap[tid]->rename(flat_dest_reg);
1071
1072 //Mark Scoreboard entry as not ready
1073 if (dest_reg < TheISA::Ctrl_Base_DepTag)
1074 scoreboard->unsetReg(rename_result.first);
1075
1076 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical "
1077 "reg %i.\n", tid, (int)flat_dest_reg,
1078 (int)rename_result.first);
1079
1080 // Record the rename information so that a history can be kept.
1081 RenameHistory hb_entry(inst->seqNum, flat_dest_reg,
1082 rename_result.first,
1083 rename_result.second);
1084
1085 historyBuffer[tid].push_front(hb_entry);
1086
1087 DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer "
1088 "(size=%i), [sn:%lli].\n",tid,
1089 historyBuffer[tid].size(),
1090 (*historyBuffer[tid].begin()).instSeqNum);
1091
1092 // Tell the instruction to rename the appropriate destination
1093 // register (dest_idx) to the new physical register
1094 // (rename_result.first), and record the previous physical
1095 // register that the same logical register was renamed to
1096 // (rename_result.second).
1097 inst->renameDestReg(dest_idx,
1098 rename_result.first,
1099 rename_result.second);
1100
1101 ++renameRenamedOperands;
1102 }
1103}
1104
1105template <class Impl>
1106inline int
1107DefaultRename<Impl>::calcFreeROBEntries(ThreadID tid)
1108{
1109 int num_free = freeEntries[tid].robEntries -
1110 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1111
1112 //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free);
1113
1114 return num_free;
1115}
1116
1117template <class Impl>
1118inline int
1119DefaultRename<Impl>::calcFreeIQEntries(ThreadID tid)
1120{
1121 int num_free = freeEntries[tid].iqEntries -
1122 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1123
1124 //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free);
1125
1126 return num_free;
1127}
1128
1129template <class Impl>
1130inline int
1131DefaultRename<Impl>::calcFreeLSQEntries(ThreadID tid)
1132{
1133 int num_free = freeEntries[tid].lsqEntries -
1134 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ);
1135
1136 //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free);
1137
1138 return num_free;
1139}
1140
1141template <class Impl>
1142unsigned
1143DefaultRename<Impl>::validInsts()
1144{
1145 unsigned inst_count = 0;
1146
1147 for (int i=0; i<fromDecode->size; i++) {
1148 if (!fromDecode->insts[i]->isSquashed())
1149 inst_count++;
1150 }
1151
1152 return inst_count;
1153}
1154
1155template <class Impl>
1156void
1157DefaultRename<Impl>::readStallSignals(ThreadID tid)
1158{
1159 if (fromIEW->iewBlock[tid]) {
1160 stalls[tid].iew = true;
1161 }
1162
1163 if (fromIEW->iewUnblock[tid]) {
1164 assert(stalls[tid].iew);
1165 stalls[tid].iew = false;
1166 }
1167
1168 if (fromCommit->commitBlock[tid]) {
1169 stalls[tid].commit = true;
1170 }
1171
1172 if (fromCommit->commitUnblock[tid]) {
1173 assert(stalls[tid].commit);
1174 stalls[tid].commit = false;
1175 }
1176}
1177
1178template <class Impl>
1179bool
1180DefaultRename<Impl>::checkStall(ThreadID tid)
1181{
1182 bool ret_val = false;
1183
1184 if (stalls[tid].iew) {
1185 DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid);
1186 ret_val = true;
1187 } else if (stalls[tid].commit) {
1188 DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid);
1189 ret_val = true;
1190 } else if (calcFreeROBEntries(tid) <= 0) {
1191 DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid);
1192 ret_val = true;
1193 } else if (calcFreeIQEntries(tid) <= 0) {
1194 DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid);
1195 ret_val = true;
1196 } else if (calcFreeLSQEntries(tid) <= 0) {
1197 DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid);
1198 ret_val = true;
1199 } else if (renameMap[tid]->numFreeEntries() <= 0) {
1200 DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid);
1201 ret_val = true;
1202 } else if (renameStatus[tid] == SerializeStall &&
1203 (!emptyROB[tid] || instsInProgress[tid])) {
1204 DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not "
1205 "empty.\n",
1206 tid);
1207 ret_val = true;
1208 }
1209
1210 return ret_val;
1211}
1212
1213template <class Impl>
1214void
1215DefaultRename<Impl>::readFreeEntries(ThreadID tid)
1216{
| 1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 * Korey Sewell
42 */
43
44#include <list>
45
46#include "arch/isa_traits.hh"
47#include "arch/registers.hh"
48#include "config/the_isa.hh"
49#include "cpu/o3/rename.hh"
50#include "debug/Activity.hh"
51#include "debug/Rename.hh"
52#include "params/DerivO3CPU.hh"
53
54using namespace std;
55
56template <class Impl>
57DefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params)
58 : cpu(_cpu),
59 iewToRenameDelay(params->iewToRenameDelay),
60 decodeToRenameDelay(params->decodeToRenameDelay),
61 commitToRenameDelay(params->commitToRenameDelay),
62 renameWidth(params->renameWidth),
63 commitWidth(params->commitWidth),
64 resumeSerialize(false),
65 resumeUnblocking(false),
66 numThreads(params->numThreads),
67 maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs)
68{
69 _status = Inactive;
70
71 for (ThreadID tid = 0; tid < numThreads; tid++) {
72 renameStatus[tid] = Idle;
73
74 freeEntries[tid].iqEntries = 0;
75 freeEntries[tid].lsqEntries = 0;
76 freeEntries[tid].robEntries = 0;
77
78 stalls[tid].iew = false;
79 stalls[tid].commit = false;
80 serializeInst[tid] = NULL;
81
82 instsInProgress[tid] = 0;
83
84 emptyROB[tid] = true;
85
86 serializeOnNextInst[tid] = false;
87 }
88
89 // @todo: Make into a parameter.
90 skidBufferMax = (2 * (iewToRenameDelay * params->decodeWidth)) + renameWidth;
91}
92
93template <class Impl>
94std::string
95DefaultRename<Impl>::name() const
96{
97 return cpu->name() + ".rename";
98}
99
100template <class Impl>
101void
102DefaultRename<Impl>::regStats()
103{
104 renameSquashCycles
105 .name(name() + ".SquashCycles")
106 .desc("Number of cycles rename is squashing")
107 .prereq(renameSquashCycles);
108 renameIdleCycles
109 .name(name() + ".IdleCycles")
110 .desc("Number of cycles rename is idle")
111 .prereq(renameIdleCycles);
112 renameBlockCycles
113 .name(name() + ".BlockCycles")
114 .desc("Number of cycles rename is blocking")
115 .prereq(renameBlockCycles);
116 renameSerializeStallCycles
117 .name(name() + ".serializeStallCycles")
118 .desc("count of cycles rename stalled for serializing inst")
119 .flags(Stats::total);
120 renameRunCycles
121 .name(name() + ".RunCycles")
122 .desc("Number of cycles rename is running")
123 .prereq(renameIdleCycles);
124 renameUnblockCycles
125 .name(name() + ".UnblockCycles")
126 .desc("Number of cycles rename is unblocking")
127 .prereq(renameUnblockCycles);
128 renameRenamedInsts
129 .name(name() + ".RenamedInsts")
130 .desc("Number of instructions processed by rename")
131 .prereq(renameRenamedInsts);
132 renameSquashedInsts
133 .name(name() + ".SquashedInsts")
134 .desc("Number of squashed instructions processed by rename")
135 .prereq(renameSquashedInsts);
136 renameROBFullEvents
137 .name(name() + ".ROBFullEvents")
138 .desc("Number of times rename has blocked due to ROB full")
139 .prereq(renameROBFullEvents);
140 renameIQFullEvents
141 .name(name() + ".IQFullEvents")
142 .desc("Number of times rename has blocked due to IQ full")
143 .prereq(renameIQFullEvents);
144 renameLSQFullEvents
145 .name(name() + ".LSQFullEvents")
146 .desc("Number of times rename has blocked due to LSQ full")
147 .prereq(renameLSQFullEvents);
148 renameFullRegistersEvents
149 .name(name() + ".FullRegisterEvents")
150 .desc("Number of times there has been no free registers")
151 .prereq(renameFullRegistersEvents);
152 renameRenamedOperands
153 .name(name() + ".RenamedOperands")
154 .desc("Number of destination operands rename has renamed")
155 .prereq(renameRenamedOperands);
156 renameRenameLookups
157 .name(name() + ".RenameLookups")
158 .desc("Number of register rename lookups that rename has made")
159 .prereq(renameRenameLookups);
160 renameCommittedMaps
161 .name(name() + ".CommittedMaps")
162 .desc("Number of HB maps that are committed")
163 .prereq(renameCommittedMaps);
164 renameUndoneMaps
165 .name(name() + ".UndoneMaps")
166 .desc("Number of HB maps that are undone due to squashing")
167 .prereq(renameUndoneMaps);
168 renamedSerializing
169 .name(name() + ".serializingInsts")
170 .desc("count of serializing insts renamed")
171 .flags(Stats::total)
172 ;
173 renamedTempSerializing
174 .name(name() + ".tempSerializingInsts")
175 .desc("count of temporary serializing insts renamed")
176 .flags(Stats::total)
177 ;
178 renameSkidInsts
179 .name(name() + ".skidInsts")
180 .desc("count of insts added to the skid buffer")
181 .flags(Stats::total)
182 ;
183 intRenameLookups
184 .name(name() + ".int_rename_lookups")
185 .desc("Number of integer rename lookups")
186 .prereq(intRenameLookups);
187 fpRenameLookups
188 .name(name() + ".fp_rename_lookups")
189 .desc("Number of floating rename lookups")
190 .prereq(fpRenameLookups);
191}
192
193template <class Impl>
194void
195DefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
196{
197 timeBuffer = tb_ptr;
198
199 // Setup wire to read information from time buffer, from IEW stage.
200 fromIEW = timeBuffer->getWire(-iewToRenameDelay);
201
202 // Setup wire to read infromation from time buffer, from commit stage.
203 fromCommit = timeBuffer->getWire(-commitToRenameDelay);
204
205 // Setup wire to write information to previous stages.
206 toDecode = timeBuffer->getWire(0);
207}
208
209template <class Impl>
210void
211DefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
212{
213 renameQueue = rq_ptr;
214
215 // Setup wire to write information to future stages.
216 toIEW = renameQueue->getWire(0);
217}
218
219template <class Impl>
220void
221DefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
222{
223 decodeQueue = dq_ptr;
224
225 // Setup wire to get information from decode.
226 fromDecode = decodeQueue->getWire(-decodeToRenameDelay);
227}
228
229template <class Impl>
230void
231DefaultRename<Impl>::initStage()
232{
233 // Grab the number of free entries directly from the stages.
234 for (ThreadID tid = 0; tid < numThreads; tid++) {
235 freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid);
236 freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid);
237 freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid);
238 emptyROB[tid] = true;
239 }
240}
241
242template<class Impl>
243void
244DefaultRename<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
245{
246 activeThreads = at_ptr;
247}
248
249
250template <class Impl>
251void
252DefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[])
253{
254 for (ThreadID tid = 0; tid < numThreads; tid++)
255 renameMap[tid] = &rm_ptr[tid];
256}
257
258template <class Impl>
259void
260DefaultRename<Impl>::setFreeList(FreeList *fl_ptr)
261{
262 freeList = fl_ptr;
263}
264
265template<class Impl>
266void
267DefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard)
268{
269 scoreboard = _scoreboard;
270}
271
272template <class Impl>
273bool
274DefaultRename<Impl>::drain()
275{
276 // Rename is ready to switch out at any time.
277 cpu->signalDrained();
278 return true;
279}
280
281template <class Impl>
282void
283DefaultRename<Impl>::switchOut()
284{
285 // Clear any state, fix up the rename map.
286 for (ThreadID tid = 0; tid < numThreads; tid++) {
287 typename std::list<RenameHistory>::iterator hb_it =
288 historyBuffer[tid].begin();
289
290 while (!historyBuffer[tid].empty()) {
291 assert(hb_it != historyBuffer[tid].end());
292
293 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
294 "number %i.\n", tid, (*hb_it).instSeqNum);
295
296 // Tell the rename map to set the architected register to the
297 // previous physical register that it was renamed to.
298 renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
299
300 // Put the renamed physical register back on the free list.
301 freeList->addReg(hb_it->newPhysReg);
302
303 // Be sure to mark its register as ready if it's a misc register.
304 if (hb_it->newPhysReg >= maxPhysicalRegs) {
305 scoreboard->setReg(hb_it->newPhysReg);
306 }
307
308 historyBuffer[tid].erase(hb_it++);
309 }
310 insts[tid].clear();
311 skidBuffer[tid].clear();
312 }
313}
314
315template <class Impl>
316void
317DefaultRename<Impl>::takeOverFrom()
318{
319 _status = Inactive;
320 initStage();
321
322 // Reset all state prior to taking over from the other CPU.
323 for (ThreadID tid = 0; tid < numThreads; tid++) {
324 renameStatus[tid] = Idle;
325
326 stalls[tid].iew = false;
327 stalls[tid].commit = false;
328 serializeInst[tid] = NULL;
329
330 instsInProgress[tid] = 0;
331
332 emptyROB[tid] = true;
333
334 serializeOnNextInst[tid] = false;
335 }
336}
337
338template <class Impl>
339void
340DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, ThreadID tid)
341{
342 DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid);
343
344 // Clear the stall signal if rename was blocked or unblocking before.
345 // If it still needs to block, the blocking should happen the next
346 // cycle and there should be space to hold everything due to the squash.
347 if (renameStatus[tid] == Blocked ||
348 renameStatus[tid] == Unblocking) {
349 toDecode->renameUnblock[tid] = 1;
350
351 resumeSerialize = false;
352 serializeInst[tid] = NULL;
353 } else if (renameStatus[tid] == SerializeStall) {
354 if (serializeInst[tid]->seqNum <= squash_seq_num) {
355 DPRINTF(Rename, "Rename will resume serializing after squash\n");
356 resumeSerialize = true;
357 assert(serializeInst[tid]);
358 } else {
359 resumeSerialize = false;
360 toDecode->renameUnblock[tid] = 1;
361
362 serializeInst[tid] = NULL;
363 }
364 }
365
366 // Set the status to Squashing.
367 renameStatus[tid] = Squashing;
368
369 // Squash any instructions from decode.
370 unsigned squashCount = 0;
371
372 for (int i=0; i<fromDecode->size; i++) {
373 if (fromDecode->insts[i]->threadNumber == tid &&
374 fromDecode->insts[i]->seqNum > squash_seq_num) {
375 fromDecode->insts[i]->setSquashed();
376 wroteToTimeBuffer = true;
377 squashCount++;
378 }
379
380 }
381
382 // Clear the instruction list and skid buffer in case they have any
383 // insts in them.
384 insts[tid].clear();
385
386 // Clear the skid buffer in case it has any data in it.
387 skidBuffer[tid].clear();
388
389 doSquash(squash_seq_num, tid);
390}
391
392template <class Impl>
393void
394DefaultRename<Impl>::tick()
395{
396 wroteToTimeBuffer = false;
397
398 blockThisCycle = false;
399
400 bool status_change = false;
401
402 toIEWIndex = 0;
403
404 sortInsts();
405
406 list<ThreadID>::iterator threads = activeThreads->begin();
407 list<ThreadID>::iterator end = activeThreads->end();
408
409 // Check stall and squash signals.
410 while (threads != end) {
411 ThreadID tid = *threads++;
412
413 DPRINTF(Rename, "Processing [tid:%i]\n", tid);
414
415 status_change = checkSignalsAndUpdate(tid) || status_change;
416
417 rename(status_change, tid);
418 }
419
420 if (status_change) {
421 updateStatus();
422 }
423
424 if (wroteToTimeBuffer) {
425 DPRINTF(Activity, "Activity this cycle.\n");
426 cpu->activityThisCycle();
427 }
428
429 threads = activeThreads->begin();
430
431 while (threads != end) {
432 ThreadID tid = *threads++;
433
434 // If we committed this cycle then doneSeqNum will be > 0
435 if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
436 !fromCommit->commitInfo[tid].squash &&
437 renameStatus[tid] != Squashing) {
438
439 removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum,
440 tid);
441 }
442 }
443
444 // @todo: make into updateProgress function
445 for (ThreadID tid = 0; tid < numThreads; tid++) {
446 instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched;
447
448 assert(instsInProgress[tid] >=0);
449 }
450
451}
452
453template<class Impl>
454void
455DefaultRename<Impl>::rename(bool &status_change, ThreadID tid)
456{
457 // If status is Running or idle,
458 // call renameInsts()
459 // If status is Unblocking,
460 // buffer any instructions coming from decode
461 // continue trying to empty skid buffer
462 // check if stall conditions have passed
463
464 if (renameStatus[tid] == Blocked) {
465 ++renameBlockCycles;
466 } else if (renameStatus[tid] == Squashing) {
467 ++renameSquashCycles;
468 } else if (renameStatus[tid] == SerializeStall) {
469 ++renameSerializeStallCycles;
470 // If we are currently in SerializeStall and resumeSerialize
471 // was set, then that means that we are resuming serializing
472 // this cycle. Tell the previous stages to block.
473 if (resumeSerialize) {
474 resumeSerialize = false;
475 block(tid);
476 toDecode->renameUnblock[tid] = false;
477 }
478 } else if (renameStatus[tid] == Unblocking) {
479 if (resumeUnblocking) {
480 block(tid);
481 resumeUnblocking = false;
482 toDecode->renameUnblock[tid] = false;
483 }
484 }
485
486 if (renameStatus[tid] == Running ||
487 renameStatus[tid] == Idle) {
488 DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run "
489 "stage.\n", tid);
490
491 renameInsts(tid);
492 } else if (renameStatus[tid] == Unblocking) {
493 renameInsts(tid);
494
495 if (validInsts()) {
496 // Add the current inputs to the skid buffer so they can be
497 // reprocessed when this stage unblocks.
498 skidInsert(tid);
499 }
500
501 // If we switched over to blocking, then there's a potential for
502 // an overall status change.
503 status_change = unblock(tid) || status_change || blockThisCycle;
504 }
505}
506
507template <class Impl>
508void
509DefaultRename<Impl>::renameInsts(ThreadID tid)
510{
511 // Instructions can be either in the skid buffer or the queue of
512 // instructions coming from decode, depending on the status.
513 int insts_available = renameStatus[tid] == Unblocking ?
514 skidBuffer[tid].size() : insts[tid].size();
515
516 // Check the decode queue to see if instructions are available.
517 // If there are no available instructions to rename, then do nothing.
518 if (insts_available == 0) {
519 DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n",
520 tid);
521 // Should I change status to idle?
522 ++renameIdleCycles;
523 return;
524 } else if (renameStatus[tid] == Unblocking) {
525 ++renameUnblockCycles;
526 } else if (renameStatus[tid] == Running) {
527 ++renameRunCycles;
528 }
529
530 DynInstPtr inst;
531
532 // Will have to do a different calculation for the number of free
533 // entries.
534 int free_rob_entries = calcFreeROBEntries(tid);
535 int free_iq_entries = calcFreeIQEntries(tid);
536 int free_lsq_entries = calcFreeLSQEntries(tid);
537 int min_free_entries = free_rob_entries;
538
539 FullSource source = ROB;
540
541 if (free_iq_entries < min_free_entries) {
542 min_free_entries = free_iq_entries;
543 source = IQ;
544 }
545
546 if (free_lsq_entries < min_free_entries) {
547 min_free_entries = free_lsq_entries;
548 source = LSQ;
549 }
550
551 // Check if there's any space left.
552 if (min_free_entries <= 0) {
553 DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ "
554 "entries.\n"
555 "ROB has %i free entries.\n"
556 "IQ has %i free entries.\n"
557 "LSQ has %i free entries.\n",
558 tid,
559 free_rob_entries,
560 free_iq_entries,
561 free_lsq_entries);
562
563 blockThisCycle = true;
564
565 block(tid);
566
567 incrFullStat(source);
568
569 return;
570 } else if (min_free_entries < insts_available) {
571 DPRINTF(Rename, "[tid:%u]: Will have to block this cycle."
572 "%i insts available, but only %i insts can be "
573 "renamed due to ROB/IQ/LSQ limits.\n",
574 tid, insts_available, min_free_entries);
575
576 insts_available = min_free_entries;
577
578 blockThisCycle = true;
579
580 incrFullStat(source);
581 }
582
583 InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ?
584 skidBuffer[tid] : insts[tid];
585
586 DPRINTF(Rename, "[tid:%u]: %i available instructions to "
587 "send iew.\n", tid, insts_available);
588
589 DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts "
590 "dispatched to IQ last cycle.\n",
591 tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched);
592
593 // Handle serializing the next instruction if necessary.
594 if (serializeOnNextInst[tid]) {
595 if (emptyROB[tid] && instsInProgress[tid] == 0) {
596 // ROB already empty; no need to serialize.
597 serializeOnNextInst[tid] = false;
598 } else if (!insts_to_rename.empty()) {
599 insts_to_rename.front()->setSerializeBefore();
600 }
601 }
602
603 int renamed_insts = 0;
604
605 while (insts_available > 0 && toIEWIndex < renameWidth) {
606 DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid);
607
608 assert(!insts_to_rename.empty());
609
610 inst = insts_to_rename.front();
611
612 insts_to_rename.pop_front();
613
614 if (renameStatus[tid] == Unblocking) {
615 DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%s from rename "
616 "skidBuffer\n", tid, inst->seqNum, inst->pcState());
617 }
618
619 if (inst->isSquashed()) {
620 DPRINTF(Rename, "[tid:%u]: instruction %i with PC %s is "
621 "squashed, skipping.\n", tid, inst->seqNum,
622 inst->pcState());
623
624 ++renameSquashedInsts;
625
626 // Decrement how many instructions are available.
627 --insts_available;
628
629 continue;
630 }
631
632 DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with "
633 "PC %s.\n", tid, inst->seqNum, inst->pcState());
634
635 // Handle serializeAfter/serializeBefore instructions.
636 // serializeAfter marks the next instruction as serializeBefore.
637 // serializeBefore makes the instruction wait in rename until the ROB
638 // is empty.
639
640 // In this model, IPR accesses are serialize before
641 // instructions, and store conditionals are serialize after
642 // instructions. This is mainly due to lack of support for
643 // out-of-order operations of either of those classes of
644 // instructions.
645 if ((inst->isIprAccess() || inst->isSerializeBefore()) &&
646 !inst->isSerializeHandled()) {
647 DPRINTF(Rename, "Serialize before instruction encountered.\n");
648
649 if (!inst->isTempSerializeBefore()) {
650 renamedSerializing++;
651 inst->setSerializeHandled();
652 } else {
653 renamedTempSerializing++;
654 }
655
656 // Change status over to SerializeStall so that other stages know
657 // what this is blocked on.
658 renameStatus[tid] = SerializeStall;
659
660 serializeInst[tid] = inst;
661
662 blockThisCycle = true;
663
664 break;
665 } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) &&
666 !inst->isSerializeHandled()) {
667 DPRINTF(Rename, "Serialize after instruction encountered.\n");
668
669 renamedSerializing++;
670
671 inst->setSerializeHandled();
672
673 serializeAfter(insts_to_rename, tid);
674 }
675
676 // Check here to make sure there are enough destination registers
677 // to rename to. Otherwise block.
678 if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) {
679 DPRINTF(Rename, "Blocking due to lack of free "
680 "physical registers to rename to.\n");
681 blockThisCycle = true;
682 insts_to_rename.push_front(inst);
683 ++renameFullRegistersEvents;
684
685 break;
686 }
687
688 renameSrcRegs(inst, inst->threadNumber);
689
690 renameDestRegs(inst, inst->threadNumber);
691
692 ++renamed_insts;
693
694#if TRACING_ON
695 inst->renameTick = curTick();
696#endif
697
698 // Put instruction in rename queue.
699 toIEW->insts[toIEWIndex] = inst;
700 ++(toIEW->size);
701
702 // Increment which instruction we're on.
703 ++toIEWIndex;
704
705 // Decrement how many instructions are available.
706 --insts_available;
707 }
708
709 instsInProgress[tid] += renamed_insts;
710 renameRenamedInsts += renamed_insts;
711
712 // If we wrote to the time buffer, record this.
713 if (toIEWIndex) {
714 wroteToTimeBuffer = true;
715 }
716
717 // Check if there's any instructions left that haven't yet been renamed.
718 // If so then block.
719 if (insts_available) {
720 blockThisCycle = true;
721 }
722
723 if (blockThisCycle) {
724 block(tid);
725 toDecode->renameUnblock[tid] = false;
726 }
727}
728
729template<class Impl>
730void
731DefaultRename<Impl>::skidInsert(ThreadID tid)
732{
733 DynInstPtr inst = NULL;
734
735 while (!insts[tid].empty()) {
736 inst = insts[tid].front();
737
738 insts[tid].pop_front();
739
740 assert(tid == inst->threadNumber);
741
742 DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC: %s into Rename "
743 "skidBuffer\n", tid, inst->seqNum, inst->pcState());
744
745 ++renameSkidInsts;
746
747 skidBuffer[tid].push_back(inst);
748 }
749
750 if (skidBuffer[tid].size() > skidBufferMax)
751 {
752 typename InstQueue::iterator it;
753 warn("Skidbuffer contents:\n");
754 for(it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++)
755 {
756 warn("[tid:%u]: %s [sn:%i].\n", tid,
757 (*it)->staticInst->disassemble(inst->instAddr()),
758 (*it)->seqNum);
759 }
760 panic("Skidbuffer Exceeded Max Size");
761 }
762}
763
764template <class Impl>
765void
766DefaultRename<Impl>::sortInsts()
767{
768 int insts_from_decode = fromDecode->size;
769#ifdef DEBUG
770 for (ThreadID tid = 0; tid < numThreads; tid++)
771 assert(insts[tid].empty());
772#endif
773 for (int i = 0; i < insts_from_decode; ++i) {
774 DynInstPtr inst = fromDecode->insts[i];
775 insts[inst->threadNumber].push_back(inst);
776 }
777}
778
779template<class Impl>
780bool
781DefaultRename<Impl>::skidsEmpty()
782{
783 list<ThreadID>::iterator threads = activeThreads->begin();
784 list<ThreadID>::iterator end = activeThreads->end();
785
786 while (threads != end) {
787 ThreadID tid = *threads++;
788
789 if (!skidBuffer[tid].empty())
790 return false;
791 }
792
793 return true;
794}
795
796template<class Impl>
797void
798DefaultRename<Impl>::updateStatus()
799{
800 bool any_unblocking = false;
801
802 list<ThreadID>::iterator threads = activeThreads->begin();
803 list<ThreadID>::iterator end = activeThreads->end();
804
805 while (threads != end) {
806 ThreadID tid = *threads++;
807
808 if (renameStatus[tid] == Unblocking) {
809 any_unblocking = true;
810 break;
811 }
812 }
813
814 // Rename will have activity if it's unblocking.
815 if (any_unblocking) {
816 if (_status == Inactive) {
817 _status = Active;
818
819 DPRINTF(Activity, "Activating stage.\n");
820
821 cpu->activateStage(O3CPU::RenameIdx);
822 }
823 } else {
824 // If it's not unblocking, then rename will not have any internal
825 // activity. Switch it to inactive.
826 if (_status == Active) {
827 _status = Inactive;
828 DPRINTF(Activity, "Deactivating stage.\n");
829
830 cpu->deactivateStage(O3CPU::RenameIdx);
831 }
832 }
833}
834
835template <class Impl>
836bool
837DefaultRename<Impl>::block(ThreadID tid)
838{
839 DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid);
840
841 // Add the current inputs onto the skid buffer, so they can be
842 // reprocessed when this stage unblocks.
843 skidInsert(tid);
844
845 // Only signal backwards to block if the previous stages do not think
846 // rename is already blocked.
847 if (renameStatus[tid] != Blocked) {
848 // If resumeUnblocking is set, we unblocked during the squash,
849 // but now we're have unblocking status. We need to tell earlier
850 // stages to block.
851 if (resumeUnblocking || renameStatus[tid] != Unblocking) {
852 toDecode->renameBlock[tid] = true;
853 toDecode->renameUnblock[tid] = false;
854 wroteToTimeBuffer = true;
855 }
856
857 // Rename can not go from SerializeStall to Blocked, otherwise
858 // it would not know to complete the serialize stall.
859 if (renameStatus[tid] != SerializeStall) {
860 // Set status to Blocked.
861 renameStatus[tid] = Blocked;
862 return true;
863 }
864 }
865
866 return false;
867}
868
869template <class Impl>
870bool
871DefaultRename<Impl>::unblock(ThreadID tid)
872{
873 DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid);
874
875 // Rename is done unblocking if the skid buffer is empty.
876 if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) {
877
878 DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid);
879
880 toDecode->renameUnblock[tid] = true;
881 wroteToTimeBuffer = true;
882
883 renameStatus[tid] = Running;
884 return true;
885 }
886
887 return false;
888}
889
890template <class Impl>
891void
892DefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, ThreadID tid)
893{
894 typename std::list<RenameHistory>::iterator hb_it =
895 historyBuffer[tid].begin();
896
897 // After a syscall squashes everything, the history buffer may be empty
898 // but the ROB may still be squashing instructions.
899 if (historyBuffer[tid].empty()) {
900 return;
901 }
902
903 // Go through the most recent instructions, undoing the mappings
904 // they did and freeing up the registers.
905 while (!historyBuffer[tid].empty() &&
906 (*hb_it).instSeqNum > squashed_seq_num) {
907 assert(hb_it != historyBuffer[tid].end());
908
909 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
910 "number %i.\n", tid, (*hb_it).instSeqNum);
911
912 // Tell the rename map to set the architected register to the
913 // previous physical register that it was renamed to.
914 renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
915
916 // Put the renamed physical register back on the free list.
917 freeList->addReg(hb_it->newPhysReg);
918
919 // Be sure to mark its register as ready if it's a misc register.
920 if (hb_it->newPhysReg >= maxPhysicalRegs) {
921 scoreboard->setReg(hb_it->newPhysReg);
922 }
923
924 historyBuffer[tid].erase(hb_it++);
925
926 ++renameUndoneMaps;
927 }
928}
929
930template<class Impl>
931void
932DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid)
933{
934 DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the "
935 "history buffer %u (size=%i), until [sn:%lli].\n",
936 tid, tid, historyBuffer[tid].size(), inst_seq_num);
937
938 typename std::list<RenameHistory>::iterator hb_it =
939 historyBuffer[tid].end();
940
941 --hb_it;
942
943 if (historyBuffer[tid].empty()) {
944 DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid);
945 return;
946 } else if (hb_it->instSeqNum > inst_seq_num) {
947 DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure "
948 "that a syscall happened recently.\n", tid);
949 return;
950 }
951
952 // Commit all the renames up until (and including) the committed sequence
953 // number. Some or even all of the committed instructions may not have
954 // rename histories if they did not have destination registers that were
955 // renamed.
956 while (!historyBuffer[tid].empty() &&
957 hb_it != historyBuffer[tid].end() &&
958 (*hb_it).instSeqNum <= inst_seq_num) {
959
960 DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, "
961 "[sn:%lli].\n",
962 tid, (*hb_it).prevPhysReg, (*hb_it).instSeqNum);
963
964 freeList->addReg((*hb_it).prevPhysReg);
965 ++renameCommittedMaps;
966
967 historyBuffer[tid].erase(hb_it--);
968 }
969}
970
971template <class Impl>
972inline void
973DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid)
974{
975 assert(renameMap[tid] != 0);
976
977 unsigned num_src_regs = inst->numSrcRegs();
978
979 // Get the architectual register numbers from the source and
980 // destination operands, and redirect them to the right register.
981 // Will need to mark dependencies though.
982 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) {
983 RegIndex src_reg = inst->srcRegIdx(src_idx);
984 RegIndex flat_src_reg = src_reg;
985 if (src_reg < TheISA::FP_Base_DepTag) {
986 flat_src_reg = inst->tcBase()->flattenIntIndex(src_reg);
987 DPRINTF(Rename, "Flattening index %d to %d.\n",
988 (int)src_reg, (int)flat_src_reg);
989 } else if (src_reg < TheISA::Ctrl_Base_DepTag) {
990 src_reg = src_reg - TheISA::FP_Base_DepTag;
991 flat_src_reg = inst->tcBase()->flattenFloatIndex(src_reg);
992 DPRINTF(Rename, "Flattening index %d to %d.\n",
993 (int)src_reg, (int)flat_src_reg);
994 flat_src_reg += TheISA::NumIntRegs;
995 } else if (src_reg < TheISA::Max_DepTag) {
996 flat_src_reg = src_reg - TheISA::Ctrl_Base_DepTag +
997 TheISA::NumFloatRegs + TheISA::NumIntRegs;
998 DPRINTF(Rename, "Adjusting reg index from %d to %d.\n",
999 src_reg, flat_src_reg);
1000 } else {
1001 panic("Reg index is out of bound: %d.", src_reg);
1002 }
1003
1004 inst->flattenSrcReg(src_idx, flat_src_reg);
1005
1006 // Look up the source registers to get the phys. register they've
1007 // been renamed to, and set the sources to those registers.
1008 PhysRegIndex renamed_reg = renameMap[tid]->lookup(flat_src_reg);
1009
1010 DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got "
1011 "physical reg %i.\n", tid, (int)flat_src_reg,
1012 (int)renamed_reg);
1013
1014 inst->renameSrcReg(src_idx, renamed_reg);
1015
1016 // See if the register is ready or not.
1017 if (scoreboard->getReg(renamed_reg) == true) {
1018 DPRINTF(Rename, "[tid:%u]: Register %d is ready.\n",
1019 tid, renamed_reg);
1020
1021 inst->markSrcRegReady(src_idx);
1022 } else {
1023 DPRINTF(Rename, "[tid:%u]: Register %d is not ready.\n",
1024 tid, renamed_reg);
1025 }
1026
1027 ++renameRenameLookups;
1028 inst->isFloating() ? fpRenameLookups++ : intRenameLookups++;
1029 }
1030}
1031
1032template <class Impl>
1033inline void
1034DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid)
1035{
1036 typename RenameMap::RenameInfo rename_result;
1037
1038 unsigned num_dest_regs = inst->numDestRegs();
1039
1040 // Rename the destination registers.
1041 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) {
1042 RegIndex dest_reg = inst->destRegIdx(dest_idx);
1043 RegIndex flat_dest_reg = dest_reg;
1044 if (dest_reg < TheISA::FP_Base_DepTag) {
1045 // Integer registers are flattened.
1046 flat_dest_reg = inst->tcBase()->flattenIntIndex(dest_reg);
1047 DPRINTF(Rename, "Flattening index %d to %d.\n",
1048 (int)dest_reg, (int)flat_dest_reg);
1049 } else if (dest_reg < TheISA::Ctrl_Base_DepTag) {
1050 dest_reg = dest_reg - TheISA::FP_Base_DepTag;
1051 flat_dest_reg = inst->tcBase()->flattenFloatIndex(dest_reg);
1052 DPRINTF(Rename, "Flattening index %d to %d.\n",
1053 (int)dest_reg, (int)flat_dest_reg);
1054 flat_dest_reg += TheISA::NumIntRegs;
1055 } else if (dest_reg < TheISA::Max_DepTag) {
1056 // Floating point and Miscellaneous registers need their indexes
1057 // adjusted to account for the expanded number of flattened int regs.
1058 flat_dest_reg = dest_reg - TheISA::Ctrl_Base_DepTag +
1059 TheISA::NumIntRegs + TheISA::NumFloatRegs;
1060 DPRINTF(Rename, "Adjusting reg index from %d to %d.\n",
1061 dest_reg, flat_dest_reg);
1062 } else {
1063 panic("Reg index is out of bound: %d.", dest_reg);
1064 }
1065
1066 inst->flattenDestReg(dest_idx, flat_dest_reg);
1067
1068 // Get the physical register that the destination will be
1069 // renamed to.
1070 rename_result = renameMap[tid]->rename(flat_dest_reg);
1071
1072 //Mark Scoreboard entry as not ready
1073 if (dest_reg < TheISA::Ctrl_Base_DepTag)
1074 scoreboard->unsetReg(rename_result.first);
1075
1076 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical "
1077 "reg %i.\n", tid, (int)flat_dest_reg,
1078 (int)rename_result.first);
1079
1080 // Record the rename information so that a history can be kept.
1081 RenameHistory hb_entry(inst->seqNum, flat_dest_reg,
1082 rename_result.first,
1083 rename_result.second);
1084
1085 historyBuffer[tid].push_front(hb_entry);
1086
1087 DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer "
1088 "(size=%i), [sn:%lli].\n",tid,
1089 historyBuffer[tid].size(),
1090 (*historyBuffer[tid].begin()).instSeqNum);
1091
1092 // Tell the instruction to rename the appropriate destination
1093 // register (dest_idx) to the new physical register
1094 // (rename_result.first), and record the previous physical
1095 // register that the same logical register was renamed to
1096 // (rename_result.second).
1097 inst->renameDestReg(dest_idx,
1098 rename_result.first,
1099 rename_result.second);
1100
1101 ++renameRenamedOperands;
1102 }
1103}
1104
1105template <class Impl>
1106inline int
1107DefaultRename<Impl>::calcFreeROBEntries(ThreadID tid)
1108{
1109 int num_free = freeEntries[tid].robEntries -
1110 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1111
1112 //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free);
1113
1114 return num_free;
1115}
1116
1117template <class Impl>
1118inline int
1119DefaultRename<Impl>::calcFreeIQEntries(ThreadID tid)
1120{
1121 int num_free = freeEntries[tid].iqEntries -
1122 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1123
1124 //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free);
1125
1126 return num_free;
1127}
1128
1129template <class Impl>
1130inline int
1131DefaultRename<Impl>::calcFreeLSQEntries(ThreadID tid)
1132{
1133 int num_free = freeEntries[tid].lsqEntries -
1134 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ);
1135
1136 //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free);
1137
1138 return num_free;
1139}
1140
1141template <class Impl>
1142unsigned
1143DefaultRename<Impl>::validInsts()
1144{
1145 unsigned inst_count = 0;
1146
1147 for (int i=0; i<fromDecode->size; i++) {
1148 if (!fromDecode->insts[i]->isSquashed())
1149 inst_count++;
1150 }
1151
1152 return inst_count;
1153}
1154
1155template <class Impl>
1156void
1157DefaultRename<Impl>::readStallSignals(ThreadID tid)
1158{
1159 if (fromIEW->iewBlock[tid]) {
1160 stalls[tid].iew = true;
1161 }
1162
1163 if (fromIEW->iewUnblock[tid]) {
1164 assert(stalls[tid].iew);
1165 stalls[tid].iew = false;
1166 }
1167
1168 if (fromCommit->commitBlock[tid]) {
1169 stalls[tid].commit = true;
1170 }
1171
1172 if (fromCommit->commitUnblock[tid]) {
1173 assert(stalls[tid].commit);
1174 stalls[tid].commit = false;
1175 }
1176}
1177
1178template <class Impl>
1179bool
1180DefaultRename<Impl>::checkStall(ThreadID tid)
1181{
1182 bool ret_val = false;
1183
1184 if (stalls[tid].iew) {
1185 DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid);
1186 ret_val = true;
1187 } else if (stalls[tid].commit) {
1188 DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid);
1189 ret_val = true;
1190 } else if (calcFreeROBEntries(tid) <= 0) {
1191 DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid);
1192 ret_val = true;
1193 } else if (calcFreeIQEntries(tid) <= 0) {
1194 DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid);
1195 ret_val = true;
1196 } else if (calcFreeLSQEntries(tid) <= 0) {
1197 DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid);
1198 ret_val = true;
1199 } else if (renameMap[tid]->numFreeEntries() <= 0) {
1200 DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid);
1201 ret_val = true;
1202 } else if (renameStatus[tid] == SerializeStall &&
1203 (!emptyROB[tid] || instsInProgress[tid])) {
1204 DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not "
1205 "empty.\n",
1206 tid);
1207 ret_val = true;
1208 }
1209
1210 return ret_val;
1211}
1212
1213template <class Impl>
1214void
1215DefaultRename<Impl>::readFreeEntries(ThreadID tid)
1216{
|
1235 }
1236
1237 DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n",
1238 tid,
1239 freeEntries[tid].iqEntries,
1240 freeEntries[tid].robEntries,
1241 freeEntries[tid].lsqEntries);
1242
1243 DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n",
1244 tid, instsInProgress[tid]);
1245}
1246
1247template <class Impl>
1248bool
1249DefaultRename<Impl>::checkSignalsAndUpdate(ThreadID tid)
1250{
1251 // Check if there's a squash signal, squash if there is
1252 // Check stall signals, block if necessary.
1253 // If status was blocked
1254 // check if stall conditions have passed
1255 // if so then go to unblocking
1256 // If status was Squashing
1257 // check if squashing is not high. Switch to running this cycle.
1258 // If status was serialize stall
1259 // check if ROB is empty and no insts are in flight to the ROB
1260
1261 readFreeEntries(tid);
1262 readStallSignals(tid);
1263
1264 if (fromCommit->commitInfo[tid].squash) {
1265 DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from "
1266 "commit.\n", tid);
1267
1268 squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
1269
1270 return true;
1271 }
1272
1273 if (fromCommit->commitInfo[tid].robSquashing) {
1274 DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid);
1275
1276 renameStatus[tid] = Squashing;
1277
1278 return true;
1279 }
1280
1281 if (checkStall(tid)) {
1282 return block(tid);
1283 }
1284
1285 if (renameStatus[tid] == Blocked) {
1286 DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n",
1287 tid);
1288
1289 renameStatus[tid] = Unblocking;
1290
1291 unblock(tid);
1292
1293 return true;
1294 }
1295
1296 if (renameStatus[tid] == Squashing) {
1297 // Switch status to running if rename isn't being told to block or
1298 // squash this cycle.
1299 if (resumeSerialize) {
1300 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n",
1301 tid);
1302
1303 renameStatus[tid] = SerializeStall;
1304 return true;
1305 } else if (resumeUnblocking) {
1306 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n",
1307 tid);
1308 renameStatus[tid] = Unblocking;
1309 return true;
1310 } else {
1311 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n",
1312 tid);
1313
1314 renameStatus[tid] = Running;
1315 return false;
1316 }
1317 }
1318
1319 if (renameStatus[tid] == SerializeStall) {
1320 // Stall ends once the ROB is free.
1321 DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to "
1322 "unblocking.\n", tid);
1323
1324 DynInstPtr serial_inst = serializeInst[tid];
1325
1326 renameStatus[tid] = Unblocking;
1327
1328 unblock(tid);
1329
1330 DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with "
1331 "PC %s.\n", tid, serial_inst->seqNum, serial_inst->pcState());
1332
1333 // Put instruction into queue here.
1334 serial_inst->clearSerializeBefore();
1335
1336 if (!skidBuffer[tid].empty()) {
1337 skidBuffer[tid].push_front(serial_inst);
1338 } else {
1339 insts[tid].push_front(serial_inst);
1340 }
1341
1342 DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename."
1343 " Adding to front of list.\n", tid);
1344
1345 serializeInst[tid] = NULL;
1346
1347 return true;
1348 }
1349
1350 // If we've reached this point, we have not gotten any signals that
1351 // cause rename to change its status. Rename remains the same as before.
1352 return false;
1353}
1354
1355template<class Impl>
1356void
1357DefaultRename<Impl>::serializeAfter(InstQueue &inst_list, ThreadID tid)
1358{
1359 if (inst_list.empty()) {
1360 // Mark a bit to say that I must serialize on the next instruction.
1361 serializeOnNextInst[tid] = true;
1362 return;
1363 }
1364
1365 // Set the next instruction as serializing.
1366 inst_list.front()->setSerializeBefore();
1367}
1368
1369template <class Impl>
1370inline void
1371DefaultRename<Impl>::incrFullStat(const FullSource &source)
1372{
1373 switch (source) {
1374 case ROB:
1375 ++renameROBFullEvents;
1376 break;
1377 case IQ:
1378 ++renameIQFullEvents;
1379 break;
1380 case LSQ:
1381 ++renameLSQFullEvents;
1382 break;
1383 default:
1384 panic("Rename full stall stat should be incremented for a reason!");
1385 break;
1386 }
1387}
1388
1389template <class Impl>
1390void
1391DefaultRename<Impl>::dumpHistory()
1392{
1393 typename std::list<RenameHistory>::iterator buf_it;
1394
1395 for (ThreadID tid = 0; tid < numThreads; tid++) {
1396
1397 buf_it = historyBuffer[tid].begin();
1398
1399 while (buf_it != historyBuffer[tid].end()) {
1400 cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys "
1401 "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg,
1402 (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg);
1403
1404 buf_it++;
1405 }
1406 }
1407}
| 1227 }
1228
1229 DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n",
1230 tid,
1231 freeEntries[tid].iqEntries,
1232 freeEntries[tid].robEntries,
1233 freeEntries[tid].lsqEntries);
1234
1235 DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n",
1236 tid, instsInProgress[tid]);
1237}
1238
1239template <class Impl>
1240bool
1241DefaultRename<Impl>::checkSignalsAndUpdate(ThreadID tid)
1242{
1243 // Check if there's a squash signal, squash if there is
1244 // Check stall signals, block if necessary.
1245 // If status was blocked
1246 // check if stall conditions have passed
1247 // if so then go to unblocking
1248 // If status was Squashing
1249 // check if squashing is not high. Switch to running this cycle.
1250 // If status was serialize stall
1251 // check if ROB is empty and no insts are in flight to the ROB
1252
1253 readFreeEntries(tid);
1254 readStallSignals(tid);
1255
1256 if (fromCommit->commitInfo[tid].squash) {
1257 DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from "
1258 "commit.\n", tid);
1259
1260 squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
1261
1262 return true;
1263 }
1264
1265 if (fromCommit->commitInfo[tid].robSquashing) {
1266 DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid);
1267
1268 renameStatus[tid] = Squashing;
1269
1270 return true;
1271 }
1272
1273 if (checkStall(tid)) {
1274 return block(tid);
1275 }
1276
1277 if (renameStatus[tid] == Blocked) {
1278 DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n",
1279 tid);
1280
1281 renameStatus[tid] = Unblocking;
1282
1283 unblock(tid);
1284
1285 return true;
1286 }
1287
1288 if (renameStatus[tid] == Squashing) {
1289 // Switch status to running if rename isn't being told to block or
1290 // squash this cycle.
1291 if (resumeSerialize) {
1292 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n",
1293 tid);
1294
1295 renameStatus[tid] = SerializeStall;
1296 return true;
1297 } else if (resumeUnblocking) {
1298 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n",
1299 tid);
1300 renameStatus[tid] = Unblocking;
1301 return true;
1302 } else {
1303 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n",
1304 tid);
1305
1306 renameStatus[tid] = Running;
1307 return false;
1308 }
1309 }
1310
1311 if (renameStatus[tid] == SerializeStall) {
1312 // Stall ends once the ROB is free.
1313 DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to "
1314 "unblocking.\n", tid);
1315
1316 DynInstPtr serial_inst = serializeInst[tid];
1317
1318 renameStatus[tid] = Unblocking;
1319
1320 unblock(tid);
1321
1322 DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with "
1323 "PC %s.\n", tid, serial_inst->seqNum, serial_inst->pcState());
1324
1325 // Put instruction into queue here.
1326 serial_inst->clearSerializeBefore();
1327
1328 if (!skidBuffer[tid].empty()) {
1329 skidBuffer[tid].push_front(serial_inst);
1330 } else {
1331 insts[tid].push_front(serial_inst);
1332 }
1333
1334 DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename."
1335 " Adding to front of list.\n", tid);
1336
1337 serializeInst[tid] = NULL;
1338
1339 return true;
1340 }
1341
1342 // If we've reached this point, we have not gotten any signals that
1343 // cause rename to change its status. Rename remains the same as before.
1344 return false;
1345}
1346
1347template<class Impl>
1348void
1349DefaultRename<Impl>::serializeAfter(InstQueue &inst_list, ThreadID tid)
1350{
1351 if (inst_list.empty()) {
1352 // Mark a bit to say that I must serialize on the next instruction.
1353 serializeOnNextInst[tid] = true;
1354 return;
1355 }
1356
1357 // Set the next instruction as serializing.
1358 inst_list.front()->setSerializeBefore();
1359}
1360
1361template <class Impl>
1362inline void
1363DefaultRename<Impl>::incrFullStat(const FullSource &source)
1364{
1365 switch (source) {
1366 case ROB:
1367 ++renameROBFullEvents;
1368 break;
1369 case IQ:
1370 ++renameIQFullEvents;
1371 break;
1372 case LSQ:
1373 ++renameLSQFullEvents;
1374 break;
1375 default:
1376 panic("Rename full stall stat should be incremented for a reason!");
1377 break;
1378 }
1379}
1380
1381template <class Impl>
1382void
1383DefaultRename<Impl>::dumpHistory()
1384{
1385 typename std::list<RenameHistory>::iterator buf_it;
1386
1387 for (ThreadID tid = 0; tid < numThreads; tid++) {
1388
1389 buf_it = historyBuffer[tid].begin();
1390
1391 while (buf_it != historyBuffer[tid].end()) {
1392 cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys "
1393 "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg,
1394 (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg);
1395
1396 buf_it++;
1397 }
1398 }
1399}
|