1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 * Korey Sewell
42 */
43
44#include <list>
45
46#include "arch/isa_traits.hh"
47#include "arch/registers.hh"
48#include "config/full_system.hh"
49#include "config/the_isa.hh"
50#include "cpu/o3/rename.hh"
51#include "debug/Activity.hh"
52#include "debug/Rename.hh"
53#include "params/DerivO3CPU.hh"
54
55using namespace std;
56
57template <class Impl>
58DefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params)
59 : cpu(_cpu),
60 iewToRenameDelay(params->iewToRenameDelay),
61 decodeToRenameDelay(params->decodeToRenameDelay),
62 commitToRenameDelay(params->commitToRenameDelay),
63 renameWidth(params->renameWidth),
64 commitWidth(params->commitWidth),
65 resumeSerialize(false),
66 resumeUnblocking(false),
67 numThreads(params->numThreads),
68 maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs)
69{
70 _status = Inactive;
71
72 for (ThreadID tid = 0; tid < numThreads; tid++) {
73 renameStatus[tid] = Idle;
74
75 freeEntries[tid].iqEntries = 0;
76 freeEntries[tid].lsqEntries = 0;
77 freeEntries[tid].robEntries = 0;
78
79 stalls[tid].iew = false;
80 stalls[tid].commit = false;
81 serializeInst[tid] = NULL;
82
83 instsInProgress[tid] = 0;
84
85 emptyROB[tid] = true;
86
87 serializeOnNextInst[tid] = false;
88 }
89
90 // @todo: Make into a parameter.
91 skidBufferMax = (2 * (iewToRenameDelay * params->decodeWidth)) + renameWidth;
92}
93
94template <class Impl>
95std::string
96DefaultRename<Impl>::name() const
97{
98 return cpu->name() + ".rename";
99}
100
101template <class Impl>
102void
103DefaultRename<Impl>::regStats()
104{
105 renameSquashCycles
106 .name(name() + ".SquashCycles")
107 .desc("Number of cycles rename is squashing")
108 .prereq(renameSquashCycles);
109 renameIdleCycles
110 .name(name() + ".IdleCycles")
111 .desc("Number of cycles rename is idle")
112 .prereq(renameIdleCycles);
113 renameBlockCycles
114 .name(name() + ".BlockCycles")
115 .desc("Number of cycles rename is blocking")
116 .prereq(renameBlockCycles);
117 renameSerializeStallCycles
118 .name(name() + ".serializeStallCycles")
119 .desc("count of cycles rename stalled for serializing inst")
120 .flags(Stats::total);
121 renameRunCycles
122 .name(name() + ".RunCycles")
123 .desc("Number of cycles rename is running")
124 .prereq(renameIdleCycles);
125 renameUnblockCycles
126 .name(name() + ".UnblockCycles")
127 .desc("Number of cycles rename is unblocking")
128 .prereq(renameUnblockCycles);
129 renameRenamedInsts
130 .name(name() + ".RenamedInsts")
131 .desc("Number of instructions processed by rename")
132 .prereq(renameRenamedInsts);
133 renameSquashedInsts
134 .name(name() + ".SquashedInsts")
135 .desc("Number of squashed instructions processed by rename")
136 .prereq(renameSquashedInsts);
137 renameROBFullEvents
138 .name(name() + ".ROBFullEvents")
139 .desc("Number of times rename has blocked due to ROB full")
140 .prereq(renameROBFullEvents);
141 renameIQFullEvents
142 .name(name() + ".IQFullEvents")
143 .desc("Number of times rename has blocked due to IQ full")
144 .prereq(renameIQFullEvents);
145 renameLSQFullEvents
146 .name(name() + ".LSQFullEvents")
147 .desc("Number of times rename has blocked due to LSQ full")
148 .prereq(renameLSQFullEvents);
149 renameFullRegistersEvents
150 .name(name() + ".FullRegisterEvents")
151 .desc("Number of times there has been no free registers")
152 .prereq(renameFullRegistersEvents);
153 renameRenamedOperands
154 .name(name() + ".RenamedOperands")
155 .desc("Number of destination operands rename has renamed")
156 .prereq(renameRenamedOperands);
157 renameRenameLookups
158 .name(name() + ".RenameLookups")
159 .desc("Number of register rename lookups that rename has made")
160 .prereq(renameRenameLookups);
161 renameCommittedMaps
162 .name(name() + ".CommittedMaps")
163 .desc("Number of HB maps that are committed")
164 .prereq(renameCommittedMaps);
165 renameUndoneMaps
166 .name(name() + ".UndoneMaps")
167 .desc("Number of HB maps that are undone due to squashing")
168 .prereq(renameUndoneMaps);
169 renamedSerializing
170 .name(name() + ".serializingInsts")
171 .desc("count of serializing insts renamed")
172 .flags(Stats::total)
173 ;
174 renamedTempSerializing
175 .name(name() + ".tempSerializingInsts")
176 .desc("count of temporary serializing insts renamed")
177 .flags(Stats::total)
178 ;
179 renameSkidInsts
180 .name(name() + ".skidInsts")
181 .desc("count of insts added to the skid buffer")
182 .flags(Stats::total)
183 ;
184 intRenameLookups
185 .name(name() + ".int_rename_lookups")
186 .desc("Number of integer rename lookups")
187 .prereq(intRenameLookups);
188 fpRenameLookups
189 .name(name() + ".fp_rename_lookups")
190 .desc("Number of floating rename lookups")
191 .prereq(fpRenameLookups);
192}
193
194template <class Impl>
195void
196DefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
197{
198 timeBuffer = tb_ptr;
199
200 // Setup wire to read information from time buffer, from IEW stage.
201 fromIEW = timeBuffer->getWire(-iewToRenameDelay);
202
203 // Setup wire to read infromation from time buffer, from commit stage.
204 fromCommit = timeBuffer->getWire(-commitToRenameDelay);
205
206 // Setup wire to write information to previous stages.
207 toDecode = timeBuffer->getWire(0);
208}
209
210template <class Impl>
211void
212DefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
213{
214 renameQueue = rq_ptr;
215
216 // Setup wire to write information to future stages.
217 toIEW = renameQueue->getWire(0);
218}
219
220template <class Impl>
221void
222DefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
223{
224 decodeQueue = dq_ptr;
225
226 // Setup wire to get information from decode.
227 fromDecode = decodeQueue->getWire(-decodeToRenameDelay);
228}
229
230template <class Impl>
231void
232DefaultRename<Impl>::initStage()
233{
234 // Grab the number of free entries directly from the stages.
235 for (ThreadID tid = 0; tid < numThreads; tid++) {
236 freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid);
237 freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid);
238 freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid);
239 emptyROB[tid] = true;
240 }
241}
242
243template<class Impl>
244void
245DefaultRename<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
246{
247 activeThreads = at_ptr;
248}
249
250
251template <class Impl>
252void
253DefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[])
254{
255 for (ThreadID tid = 0; tid < numThreads; tid++)
256 renameMap[tid] = &rm_ptr[tid];
257}
258
259template <class Impl>
260void
261DefaultRename<Impl>::setFreeList(FreeList *fl_ptr)
262{
263 freeList = fl_ptr;
264}
265
266template<class Impl>
267void
268DefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard)
269{
270 scoreboard = _scoreboard;
271}
272
273template <class Impl>
274bool
275DefaultRename<Impl>::drain()
276{
277 // Rename is ready to switch out at any time.
278 cpu->signalDrained();
279 return true;
280}
281
282template <class Impl>
283void
284DefaultRename<Impl>::switchOut()
285{
286 // Clear any state, fix up the rename map.
287 for (ThreadID tid = 0; tid < numThreads; tid++) {
288 typename std::list<RenameHistory>::iterator hb_it =
289 historyBuffer[tid].begin();
290
291 while (!historyBuffer[tid].empty()) {
292 assert(hb_it != historyBuffer[tid].end());
293
294 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
295 "number %i.\n", tid, (*hb_it).instSeqNum);
296
297 // Tell the rename map to set the architected register to the
298 // previous physical register that it was renamed to.
299 renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
300
301 // Put the renamed physical register back on the free list.
302 freeList->addReg(hb_it->newPhysReg);
303
304 // Be sure to mark its register as ready if it's a misc register.
305 if (hb_it->newPhysReg >= maxPhysicalRegs) {
306 scoreboard->setReg(hb_it->newPhysReg);
307 }
308
309 historyBuffer[tid].erase(hb_it++);
310 }
311 insts[tid].clear();
312 skidBuffer[tid].clear();
313 }
314}
315
316template <class Impl>
317void
318DefaultRename<Impl>::takeOverFrom()
319{
320 _status = Inactive;
321 initStage();
322
323 // Reset all state prior to taking over from the other CPU.
324 for (ThreadID tid = 0; tid < numThreads; tid++) {
325 renameStatus[tid] = Idle;
326
327 stalls[tid].iew = false;
328 stalls[tid].commit = false;
329 serializeInst[tid] = NULL;
330
331 instsInProgress[tid] = 0;
332
333 emptyROB[tid] = true;
334
335 serializeOnNextInst[tid] = false;
336 }
337}
338
339template <class Impl>
340void
341DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, ThreadID tid)
342{
343 DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid);
344
345 // Clear the stall signal if rename was blocked or unblocking before.
346 // If it still needs to block, the blocking should happen the next
347 // cycle and there should be space to hold everything due to the squash.
348 if (renameStatus[tid] == Blocked ||
349 renameStatus[tid] == Unblocking) {
350 toDecode->renameUnblock[tid] = 1;
351
352 resumeSerialize = false;
353 serializeInst[tid] = NULL;
354 } else if (renameStatus[tid] == SerializeStall) {
355 if (serializeInst[tid]->seqNum <= squash_seq_num) {
356 DPRINTF(Rename, "Rename will resume serializing after squash\n");
357 resumeSerialize = true;
358 assert(serializeInst[tid]);
359 } else {
360 resumeSerialize = false;
361 toDecode->renameUnblock[tid] = 1;
362
363 serializeInst[tid] = NULL;
364 }
365 }
366
367 // Set the status to Squashing.
368 renameStatus[tid] = Squashing;
369
370 // Squash any instructions from decode.
371 unsigned squashCount = 0;
372
373 for (int i=0; i<fromDecode->size; i++) {
374 if (fromDecode->insts[i]->threadNumber == tid &&
375 fromDecode->insts[i]->seqNum > squash_seq_num) {
376 fromDecode->insts[i]->setSquashed();
377 wroteToTimeBuffer = true;
378 squashCount++;
379 }
380
381 }
382
383 // Clear the instruction list and skid buffer in case they have any
384 // insts in them.
385 insts[tid].clear();
386
387 // Clear the skid buffer in case it has any data in it.
388 skidBuffer[tid].clear();
389
390 doSquash(squash_seq_num, tid);
391}
392
393template <class Impl>
394void
395DefaultRename<Impl>::tick()
396{
397 wroteToTimeBuffer = false;
398
399 blockThisCycle = false;
400
401 bool status_change = false;
402
403 toIEWIndex = 0;
404
405 sortInsts();
406
407 list<ThreadID>::iterator threads = activeThreads->begin();
408 list<ThreadID>::iterator end = activeThreads->end();
409
410 // Check stall and squash signals.
411 while (threads != end) {
412 ThreadID tid = *threads++;
413
414 DPRINTF(Rename, "Processing [tid:%i]\n", tid);
415
416 status_change = checkSignalsAndUpdate(tid) || status_change;
417
418 rename(status_change, tid);
419 }
420
421 if (status_change) {
422 updateStatus();
423 }
424
425 if (wroteToTimeBuffer) {
426 DPRINTF(Activity, "Activity this cycle.\n");
427 cpu->activityThisCycle();
428 }
429
430 threads = activeThreads->begin();
431
432 while (threads != end) {
433 ThreadID tid = *threads++;
434
435 // If we committed this cycle then doneSeqNum will be > 0
436 if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
437 !fromCommit->commitInfo[tid].squash &&
438 renameStatus[tid] != Squashing) {
439
440 removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum,
441 tid);
442 }
443 }
444
445 // @todo: make into updateProgress function
446 for (ThreadID tid = 0; tid < numThreads; tid++) {
447 instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched;
448
449 assert(instsInProgress[tid] >=0);
450 }
451
452}
453
454template<class Impl>
455void
456DefaultRename<Impl>::rename(bool &status_change, ThreadID tid)
457{
458 // If status is Running or idle,
459 // call renameInsts()
460 // If status is Unblocking,
461 // buffer any instructions coming from decode
462 // continue trying to empty skid buffer
463 // check if stall conditions have passed
464
465 if (renameStatus[tid] == Blocked) {
466 ++renameBlockCycles;
467 } else if (renameStatus[tid] == Squashing) {
468 ++renameSquashCycles;
469 } else if (renameStatus[tid] == SerializeStall) {
470 ++renameSerializeStallCycles;
471 // If we are currently in SerializeStall and resumeSerialize
472 // was set, then that means that we are resuming serializing
473 // this cycle. Tell the previous stages to block.
474 if (resumeSerialize) {
475 resumeSerialize = false;
476 block(tid);
477 toDecode->renameUnblock[tid] = false;
478 }
479 } else if (renameStatus[tid] == Unblocking) {
480 if (resumeUnblocking) {
481 block(tid);
482 resumeUnblocking = false;
483 toDecode->renameUnblock[tid] = false;
484 }
485 }
486
487 if (renameStatus[tid] == Running ||
488 renameStatus[tid] == Idle) {
489 DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run "
490 "stage.\n", tid);
491
492 renameInsts(tid);
493 } else if (renameStatus[tid] == Unblocking) {
494 renameInsts(tid);
495
496 if (validInsts()) {
497 // Add the current inputs to the skid buffer so they can be
498 // reprocessed when this stage unblocks.
499 skidInsert(tid);
500 }
501
502 // If we switched over to blocking, then there's a potential for
503 // an overall status change.
504 status_change = unblock(tid) || status_change || blockThisCycle;
505 }
506}
507
508template <class Impl>
509void
510DefaultRename<Impl>::renameInsts(ThreadID tid)
511{
512 // Instructions can be either in the skid buffer or the queue of
513 // instructions coming from decode, depending on the status.
514 int insts_available = renameStatus[tid] == Unblocking ?
515 skidBuffer[tid].size() : insts[tid].size();
516
517 // Check the decode queue to see if instructions are available.
518 // If there are no available instructions to rename, then do nothing.
519 if (insts_available == 0) {
520 DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n",
521 tid);
522 // Should I change status to idle?
523 ++renameIdleCycles;
524 return;
525 } else if (renameStatus[tid] == Unblocking) {
526 ++renameUnblockCycles;
527 } else if (renameStatus[tid] == Running) {
528 ++renameRunCycles;
529 }
530
531 DynInstPtr inst;
532
533 // Will have to do a different calculation for the number of free
534 // entries.
535 int free_rob_entries = calcFreeROBEntries(tid);
536 int free_iq_entries = calcFreeIQEntries(tid);
537 int free_lsq_entries = calcFreeLSQEntries(tid);
538 int min_free_entries = free_rob_entries;
539
540 FullSource source = ROB;
541
542 if (free_iq_entries < min_free_entries) {
543 min_free_entries = free_iq_entries;
544 source = IQ;
545 }
546
547 if (free_lsq_entries < min_free_entries) {
548 min_free_entries = free_lsq_entries;
549 source = LSQ;
550 }
551
552 // Check if there's any space left.
553 if (min_free_entries <= 0) {
554 DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ "
555 "entries.\n"
556 "ROB has %i free entries.\n"
557 "IQ has %i free entries.\n"
558 "LSQ has %i free entries.\n",
559 tid,
560 free_rob_entries,
561 free_iq_entries,
562 free_lsq_entries);
563
564 blockThisCycle = true;
565
566 block(tid);
567
568 incrFullStat(source);
569
570 return;
571 } else if (min_free_entries < insts_available) {
572 DPRINTF(Rename, "[tid:%u]: Will have to block this cycle."
573 "%i insts available, but only %i insts can be "
574 "renamed due to ROB/IQ/LSQ limits.\n",
575 tid, insts_available, min_free_entries);
576
577 insts_available = min_free_entries;
578
579 blockThisCycle = true;
580
581 incrFullStat(source);
582 }
583
584 InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ?
585 skidBuffer[tid] : insts[tid];
586
587 DPRINTF(Rename, "[tid:%u]: %i available instructions to "
588 "send iew.\n", tid, insts_available);
589
590 DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts "
591 "dispatched to IQ last cycle.\n",
592 tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched);
593
594 // Handle serializing the next instruction if necessary.
595 if (serializeOnNextInst[tid]) {
596 if (emptyROB[tid] && instsInProgress[tid] == 0) {
597 // ROB already empty; no need to serialize.
598 serializeOnNextInst[tid] = false;
599 } else if (!insts_to_rename.empty()) {
600 insts_to_rename.front()->setSerializeBefore();
601 }
602 }
603
604 int renamed_insts = 0;
605
606 while (insts_available > 0 && toIEWIndex < renameWidth) {
607 DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid);
608
609 assert(!insts_to_rename.empty());
610
611 inst = insts_to_rename.front();
612
613 insts_to_rename.pop_front();
614
615 if (renameStatus[tid] == Unblocking) {
616 DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%s from rename "
617 "skidBuffer\n", tid, inst->seqNum, inst->pcState());
618 }
619
620 if (inst->isSquashed()) {
621 DPRINTF(Rename, "[tid:%u]: instruction %i with PC %s is "
622 "squashed, skipping.\n", tid, inst->seqNum,
623 inst->pcState());
624
625 ++renameSquashedInsts;
626
627 // Decrement how many instructions are available.
628 --insts_available;
629
630 continue;
631 }
632
633 DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with "
634 "PC %s.\n", tid, inst->seqNum, inst->pcState());
635
636 // Handle serializeAfter/serializeBefore instructions.
637 // serializeAfter marks the next instruction as serializeBefore.
638 // serializeBefore makes the instruction wait in rename until the ROB
639 // is empty.
640
641 // In this model, IPR accesses are serialize before
642 // instructions, and store conditionals are serialize after
643 // instructions. This is mainly due to lack of support for
644 // out-of-order operations of either of those classes of
645 // instructions.
646 if ((inst->isIprAccess() || inst->isSerializeBefore()) &&
647 !inst->isSerializeHandled()) {
648 DPRINTF(Rename, "Serialize before instruction encountered.\n");
649
650 if (!inst->isTempSerializeBefore()) {
651 renamedSerializing++;
652 inst->setSerializeHandled();
653 } else {
654 renamedTempSerializing++;
655 }
656
657 // Change status over to SerializeStall so that other stages know
658 // what this is blocked on.
659 renameStatus[tid] = SerializeStall;
660
661 serializeInst[tid] = inst;
662
663 blockThisCycle = true;
664
665 break;
666 } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) &&
667 !inst->isSerializeHandled()) {
668 DPRINTF(Rename, "Serialize after instruction encountered.\n");
669
670 renamedSerializing++;
671
672 inst->setSerializeHandled();
673
674 serializeAfter(insts_to_rename, tid);
675 }
676
677 // Check here to make sure there are enough destination registers
678 // to rename to. Otherwise block.
679 if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) {
680 DPRINTF(Rename, "Blocking due to lack of free "
681 "physical registers to rename to.\n");
682 blockThisCycle = true;
683 insts_to_rename.push_front(inst);
684 ++renameFullRegistersEvents;
685
686 break;
687 }
688
689 renameSrcRegs(inst, inst->threadNumber);
690
691 renameDestRegs(inst, inst->threadNumber);
692
693 ++renamed_insts;
694
695#if TRACING_ON
696 inst->renameTick = curTick();
697#endif
698
699 // Put instruction in rename queue.
700 toIEW->insts[toIEWIndex] = inst;
701 ++(toIEW->size);
702
703 // Increment which instruction we're on.
704 ++toIEWIndex;
705
706 // Decrement how many instructions are available.
707 --insts_available;
708 }
709
710 instsInProgress[tid] += renamed_insts;
711 renameRenamedInsts += renamed_insts;
712
713 // If we wrote to the time buffer, record this.
714 if (toIEWIndex) {
715 wroteToTimeBuffer = true;
716 }
717
718 // Check if there's any instructions left that haven't yet been renamed.
719 // If so then block.
720 if (insts_available) {
721 blockThisCycle = true;
722 }
723
724 if (blockThisCycle) {
725 block(tid);
726 toDecode->renameUnblock[tid] = false;
727 }
728}
729
730template<class Impl>
731void
732DefaultRename<Impl>::skidInsert(ThreadID tid)
733{
734 DynInstPtr inst = NULL;
735
736 while (!insts[tid].empty()) {
737 inst = insts[tid].front();
738
739 insts[tid].pop_front();
740
741 assert(tid == inst->threadNumber);
742
743 DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC: %s into Rename "
744 "skidBuffer\n", tid, inst->seqNum, inst->pcState());
745
746 ++renameSkidInsts;
747
748 skidBuffer[tid].push_back(inst);
749 }
750
751 if (skidBuffer[tid].size() > skidBufferMax)
752 {
753 typename InstQueue::iterator it;
754 warn("Skidbuffer contents:\n");
755 for(it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++)
756 {
757 warn("[tid:%u]: %s [sn:%i].\n", tid,
758 (*it)->staticInst->disassemble(inst->instAddr()),
759 (*it)->seqNum);
760 }
761 panic("Skidbuffer Exceeded Max Size");
762 }
763}
764
765template <class Impl>
766void
767DefaultRename<Impl>::sortInsts()
768{
769 int insts_from_decode = fromDecode->size;
770#ifdef DEBUG
771 for (ThreadID tid = 0; tid < numThreads; tid++)
772 assert(insts[tid].empty());
773#endif
774 for (int i = 0; i < insts_from_decode; ++i) {
775 DynInstPtr inst = fromDecode->insts[i];
776 insts[inst->threadNumber].push_back(inst);
777 }
778}
779
780template<class Impl>
781bool
782DefaultRename<Impl>::skidsEmpty()
783{
784 list<ThreadID>::iterator threads = activeThreads->begin();
785 list<ThreadID>::iterator end = activeThreads->end();
786
787 while (threads != end) {
788 ThreadID tid = *threads++;
789
790 if (!skidBuffer[tid].empty())
791 return false;
792 }
793
794 return true;
795}
796
797template<class Impl>
798void
799DefaultRename<Impl>::updateStatus()
800{
801 bool any_unblocking = false;
802
803 list<ThreadID>::iterator threads = activeThreads->begin();
804 list<ThreadID>::iterator end = activeThreads->end();
805
806 while (threads != end) {
807 ThreadID tid = *threads++;
808
809 if (renameStatus[tid] == Unblocking) {
810 any_unblocking = true;
811 break;
812 }
813 }
814
815 // Rename will have activity if it's unblocking.
816 if (any_unblocking) {
817 if (_status == Inactive) {
818 _status = Active;
819
820 DPRINTF(Activity, "Activating stage.\n");
821
822 cpu->activateStage(O3CPU::RenameIdx);
823 }
824 } else {
825 // If it's not unblocking, then rename will not have any internal
826 // activity. Switch it to inactive.
827 if (_status == Active) {
828 _status = Inactive;
829 DPRINTF(Activity, "Deactivating stage.\n");
830
831 cpu->deactivateStage(O3CPU::RenameIdx);
832 }
833 }
834}
835
836template <class Impl>
837bool
838DefaultRename<Impl>::block(ThreadID tid)
839{
840 DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid);
841
842 // Add the current inputs onto the skid buffer, so they can be
843 // reprocessed when this stage unblocks.
844 skidInsert(tid);
845
846 // Only signal backwards to block if the previous stages do not think
847 // rename is already blocked.
848 if (renameStatus[tid] != Blocked) {
849 // If resumeUnblocking is set, we unblocked during the squash,
850 // but now we're have unblocking status. We need to tell earlier
851 // stages to block.
852 if (resumeUnblocking || renameStatus[tid] != Unblocking) {
853 toDecode->renameBlock[tid] = true;
854 toDecode->renameUnblock[tid] = false;
855 wroteToTimeBuffer = true;
856 }
857
858 // Rename can not go from SerializeStall to Blocked, otherwise
859 // it would not know to complete the serialize stall.
860 if (renameStatus[tid] != SerializeStall) {
861 // Set status to Blocked.
862 renameStatus[tid] = Blocked;
863 return true;
864 }
865 }
866
867 return false;
868}
869
870template <class Impl>
871bool
872DefaultRename<Impl>::unblock(ThreadID tid)
873{
874 DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid);
875
876 // Rename is done unblocking if the skid buffer is empty.
877 if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) {
878
879 DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid);
880
881 toDecode->renameUnblock[tid] = true;
882 wroteToTimeBuffer = true;
883
884 renameStatus[tid] = Running;
885 return true;
886 }
887
888 return false;
889}
890
891template <class Impl>
892void
893DefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, ThreadID tid)
894{
895 typename std::list<RenameHistory>::iterator hb_it =
896 historyBuffer[tid].begin();
897
898 // After a syscall squashes everything, the history buffer may be empty
899 // but the ROB may still be squashing instructions.
900 if (historyBuffer[tid].empty()) {
901 return;
902 }
903
904 // Go through the most recent instructions, undoing the mappings
905 // they did and freeing up the registers.
906 while (!historyBuffer[tid].empty() &&
907 (*hb_it).instSeqNum > squashed_seq_num) {
908 assert(hb_it != historyBuffer[tid].end());
909
910 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
911 "number %i.\n", tid, (*hb_it).instSeqNum);
912
913 // Tell the rename map to set the architected register to the
914 // previous physical register that it was renamed to.
915 renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
916
917 // Put the renamed physical register back on the free list.
918 freeList->addReg(hb_it->newPhysReg);
919
920 // Be sure to mark its register as ready if it's a misc register.
921 if (hb_it->newPhysReg >= maxPhysicalRegs) {
922 scoreboard->setReg(hb_it->newPhysReg);
923 }
924
925 historyBuffer[tid].erase(hb_it++);
926
927 ++renameUndoneMaps;
928 }
929}
930
931template<class Impl>
932void
933DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid)
934{
935 DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the "
936 "history buffer %u (size=%i), until [sn:%lli].\n",
937 tid, tid, historyBuffer[tid].size(), inst_seq_num);
938
939 typename std::list<RenameHistory>::iterator hb_it =
940 historyBuffer[tid].end();
941
942 --hb_it;
943
944 if (historyBuffer[tid].empty()) {
945 DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid);
946 return;
947 } else if (hb_it->instSeqNum > inst_seq_num) {
948 DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure "
949 "that a syscall happened recently.\n", tid);
950 return;
951 }
952
953 // Commit all the renames up until (and including) the committed sequence
954 // number. Some or even all of the committed instructions may not have
955 // rename histories if they did not have destination registers that were
956 // renamed.
957 while (!historyBuffer[tid].empty() &&
958 hb_it != historyBuffer[tid].end() &&
959 (*hb_it).instSeqNum <= inst_seq_num) {
960
961 DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, "
962 "[sn:%lli].\n",
963 tid, (*hb_it).prevPhysReg, (*hb_it).instSeqNum);
964
965 freeList->addReg((*hb_it).prevPhysReg);
966 ++renameCommittedMaps;
967
968 historyBuffer[tid].erase(hb_it--);
969 }
970}
971
972template <class Impl>
973inline void
974DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid)
975{
976 assert(renameMap[tid] != 0);
977
978 unsigned num_src_regs = inst->numSrcRegs();
979
980 // Get the architectual register numbers from the source and
981 // destination operands, and redirect them to the right register.
982 // Will need to mark dependencies though.
983 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) {
984 RegIndex src_reg = inst->srcRegIdx(src_idx);
985 RegIndex flat_src_reg = src_reg;
986 if (src_reg < TheISA::FP_Base_DepTag) {
987 flat_src_reg = inst->tcBase()->flattenIntIndex(src_reg);
988 DPRINTF(Rename, "Flattening index %d to %d.\n",
989 (int)src_reg, (int)flat_src_reg);
990 } else if (src_reg < TheISA::Ctrl_Base_DepTag) {
991 src_reg = src_reg - TheISA::FP_Base_DepTag;
992 flat_src_reg = inst->tcBase()->flattenFloatIndex(src_reg);
993 DPRINTF(Rename, "Flattening index %d to %d.\n",
994 (int)src_reg, (int)flat_src_reg);
995 flat_src_reg += TheISA::NumIntRegs;
996 } else if (src_reg < TheISA::Max_DepTag) {
997 flat_src_reg = src_reg - TheISA::Ctrl_Base_DepTag +
998 TheISA::NumFloatRegs + TheISA::NumIntRegs;
999 DPRINTF(Rename, "Adjusting reg index from %d to %d.\n",
1000 src_reg, flat_src_reg);
1001 } else {
1002 panic("Reg index is out of bound: %d.", src_reg);
1003 }
1004
1005 inst->flattenSrcReg(src_idx, flat_src_reg);
1006
1007 // Look up the source registers to get the phys. register they've
1008 // been renamed to, and set the sources to those registers.
1009 PhysRegIndex renamed_reg = renameMap[tid]->lookup(flat_src_reg);
1010
1011 DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got "
1012 "physical reg %i.\n", tid, (int)flat_src_reg,
1013 (int)renamed_reg);
1014
1015 inst->renameSrcReg(src_idx, renamed_reg);
1016
1017 // See if the register is ready or not.
1018 if (scoreboard->getReg(renamed_reg) == true) {
1019 DPRINTF(Rename, "[tid:%u]: Register %d is ready.\n",
1020 tid, renamed_reg);
1021
1022 inst->markSrcRegReady(src_idx);
1023 } else {
1024 DPRINTF(Rename, "[tid:%u]: Register %d is not ready.\n",
1025 tid, renamed_reg);
1026 }
1027
1028 ++renameRenameLookups;
1029 inst->isFloating() ? fpRenameLookups++ : intRenameLookups++;
1030 }
1031}
1032
1033template <class Impl>
1034inline void
1035DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid)
1036{
1037 typename RenameMap::RenameInfo rename_result;
1038
1039 unsigned num_dest_regs = inst->numDestRegs();
1040
1041 // Rename the destination registers.
1042 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) {
1043 RegIndex dest_reg = inst->destRegIdx(dest_idx);
1044 RegIndex flat_dest_reg = dest_reg;
1045 if (dest_reg < TheISA::FP_Base_DepTag) {
1046 // Integer registers are flattened.
1047 flat_dest_reg = inst->tcBase()->flattenIntIndex(dest_reg);
1048 DPRINTF(Rename, "Flattening index %d to %d.\n",
1049 (int)dest_reg, (int)flat_dest_reg);
1050 } else if (dest_reg < TheISA::Ctrl_Base_DepTag) {
1051 dest_reg = dest_reg - TheISA::FP_Base_DepTag;
1052 flat_dest_reg = inst->tcBase()->flattenFloatIndex(dest_reg);
1053 DPRINTF(Rename, "Flattening index %d to %d.\n",
1054 (int)dest_reg, (int)flat_dest_reg);
1055 flat_dest_reg += TheISA::NumIntRegs;
1056 } else if (dest_reg < TheISA::Max_DepTag) {
1057 // Floating point and Miscellaneous registers need their indexes
1058 // adjusted to account for the expanded number of flattened int regs.
1059 flat_dest_reg = dest_reg - TheISA::Ctrl_Base_DepTag +
1060 TheISA::NumIntRegs + TheISA::NumFloatRegs;
1061 DPRINTF(Rename, "Adjusting reg index from %d to %d.\n",
1062 dest_reg, flat_dest_reg);
1063 } else {
1064 panic("Reg index is out of bound: %d.", dest_reg);
1065 }
1066
1067 inst->flattenDestReg(dest_idx, flat_dest_reg);
1068
1069 // Get the physical register that the destination will be
1070 // renamed to.
1071 rename_result = renameMap[tid]->rename(flat_dest_reg);
1072
1073 //Mark Scoreboard entry as not ready
1074 if (dest_reg < TheISA::Ctrl_Base_DepTag)
1075 scoreboard->unsetReg(rename_result.first);
1076
1077 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical "
1078 "reg %i.\n", tid, (int)flat_dest_reg,
1079 (int)rename_result.first);
1080
1081 // Record the rename information so that a history can be kept.
1082 RenameHistory hb_entry(inst->seqNum, flat_dest_reg,
1083 rename_result.first,
1084 rename_result.second);
1085
1086 historyBuffer[tid].push_front(hb_entry);
1087
1088 DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer "
1089 "(size=%i), [sn:%lli].\n",tid,
1090 historyBuffer[tid].size(),
1091 (*historyBuffer[tid].begin()).instSeqNum);
1092
1093 // Tell the instruction to rename the appropriate destination
1094 // register (dest_idx) to the new physical register
1095 // (rename_result.first), and record the previous physical
1096 // register that the same logical register was renamed to
1097 // (rename_result.second).
1098 inst->renameDestReg(dest_idx,
1099 rename_result.first,
1100 rename_result.second);
1101
1102 ++renameRenamedOperands;
1103 }
1104}
1105
1106template <class Impl>
1107inline int
1108DefaultRename<Impl>::calcFreeROBEntries(ThreadID tid)
1109{
1110 int num_free = freeEntries[tid].robEntries -
1111 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1112
1113 //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free);
1114
1115 return num_free;
1116}
1117
1118template <class Impl>
1119inline int
1120DefaultRename<Impl>::calcFreeIQEntries(ThreadID tid)
1121{
1122 int num_free = freeEntries[tid].iqEntries -
1123 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1124
1125 //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free);
1126
1127 return num_free;
1128}
1129
1130template <class Impl>
1131inline int
1132DefaultRename<Impl>::calcFreeLSQEntries(ThreadID tid)
1133{
1134 int num_free = freeEntries[tid].lsqEntries -
1135 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ);
1136
1137 //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free);
1138
1139 return num_free;
1140}
1141
1142template <class Impl>
1143unsigned
1144DefaultRename<Impl>::validInsts()
1145{
1146 unsigned inst_count = 0;
1147
1148 for (int i=0; i<fromDecode->size; i++) {
1149 if (!fromDecode->insts[i]->isSquashed())
1150 inst_count++;
1151 }
1152
1153 return inst_count;
1154}
1155
1156template <class Impl>
1157void
1158DefaultRename<Impl>::readStallSignals(ThreadID tid)
1159{
1160 if (fromIEW->iewBlock[tid]) {
1161 stalls[tid].iew = true;
1162 }
1163
1164 if (fromIEW->iewUnblock[tid]) {
1165 assert(stalls[tid].iew);
1166 stalls[tid].iew = false;
1167 }
1168
1169 if (fromCommit->commitBlock[tid]) {
1170 stalls[tid].commit = true;
1171 }
1172
1173 if (fromCommit->commitUnblock[tid]) {
1174 assert(stalls[tid].commit);
1175 stalls[tid].commit = false;
1176 }
1177}
1178
1179template <class Impl>
1180bool
1181DefaultRename<Impl>::checkStall(ThreadID tid)
1182{
1183 bool ret_val = false;
1184
1185 if (stalls[tid].iew) {
1186 DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid);
1187 ret_val = true;
1188 } else if (stalls[tid].commit) {
1189 DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid);
1190 ret_val = true;
1191 } else if (calcFreeROBEntries(tid) <= 0) {
1192 DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid);
1193 ret_val = true;
1194 } else if (calcFreeIQEntries(tid) <= 0) {
1195 DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid);
1196 ret_val = true;
1197 } else if (calcFreeLSQEntries(tid) <= 0) {
1198 DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid);
1199 ret_val = true;
1200 } else if (renameMap[tid]->numFreeEntries() <= 0) {
1201 DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid);
1202 ret_val = true;
1203 } else if (renameStatus[tid] == SerializeStall &&
1204 (!emptyROB[tid] || instsInProgress[tid])) {
1205 DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not "
1206 "empty.\n",
1207 tid);
1208 ret_val = true;
1209 }
1210
1211 return ret_val;
1212}
1213
1214template <class Impl>
1215void
1216DefaultRename<Impl>::readFreeEntries(ThreadID tid)
1217{
| 1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 * Korey Sewell
42 */
43
44#include <list>
45
46#include "arch/isa_traits.hh"
47#include "arch/registers.hh"
48#include "config/full_system.hh"
49#include "config/the_isa.hh"
50#include "cpu/o3/rename.hh"
51#include "debug/Activity.hh"
52#include "debug/Rename.hh"
53#include "params/DerivO3CPU.hh"
54
55using namespace std;
56
57template <class Impl>
58DefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params)
59 : cpu(_cpu),
60 iewToRenameDelay(params->iewToRenameDelay),
61 decodeToRenameDelay(params->decodeToRenameDelay),
62 commitToRenameDelay(params->commitToRenameDelay),
63 renameWidth(params->renameWidth),
64 commitWidth(params->commitWidth),
65 resumeSerialize(false),
66 resumeUnblocking(false),
67 numThreads(params->numThreads),
68 maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs)
69{
70 _status = Inactive;
71
72 for (ThreadID tid = 0; tid < numThreads; tid++) {
73 renameStatus[tid] = Idle;
74
75 freeEntries[tid].iqEntries = 0;
76 freeEntries[tid].lsqEntries = 0;
77 freeEntries[tid].robEntries = 0;
78
79 stalls[tid].iew = false;
80 stalls[tid].commit = false;
81 serializeInst[tid] = NULL;
82
83 instsInProgress[tid] = 0;
84
85 emptyROB[tid] = true;
86
87 serializeOnNextInst[tid] = false;
88 }
89
90 // @todo: Make into a parameter.
91 skidBufferMax = (2 * (iewToRenameDelay * params->decodeWidth)) + renameWidth;
92}
93
94template <class Impl>
95std::string
96DefaultRename<Impl>::name() const
97{
98 return cpu->name() + ".rename";
99}
100
101template <class Impl>
102void
103DefaultRename<Impl>::regStats()
104{
105 renameSquashCycles
106 .name(name() + ".SquashCycles")
107 .desc("Number of cycles rename is squashing")
108 .prereq(renameSquashCycles);
109 renameIdleCycles
110 .name(name() + ".IdleCycles")
111 .desc("Number of cycles rename is idle")
112 .prereq(renameIdleCycles);
113 renameBlockCycles
114 .name(name() + ".BlockCycles")
115 .desc("Number of cycles rename is blocking")
116 .prereq(renameBlockCycles);
117 renameSerializeStallCycles
118 .name(name() + ".serializeStallCycles")
119 .desc("count of cycles rename stalled for serializing inst")
120 .flags(Stats::total);
121 renameRunCycles
122 .name(name() + ".RunCycles")
123 .desc("Number of cycles rename is running")
124 .prereq(renameIdleCycles);
125 renameUnblockCycles
126 .name(name() + ".UnblockCycles")
127 .desc("Number of cycles rename is unblocking")
128 .prereq(renameUnblockCycles);
129 renameRenamedInsts
130 .name(name() + ".RenamedInsts")
131 .desc("Number of instructions processed by rename")
132 .prereq(renameRenamedInsts);
133 renameSquashedInsts
134 .name(name() + ".SquashedInsts")
135 .desc("Number of squashed instructions processed by rename")
136 .prereq(renameSquashedInsts);
137 renameROBFullEvents
138 .name(name() + ".ROBFullEvents")
139 .desc("Number of times rename has blocked due to ROB full")
140 .prereq(renameROBFullEvents);
141 renameIQFullEvents
142 .name(name() + ".IQFullEvents")
143 .desc("Number of times rename has blocked due to IQ full")
144 .prereq(renameIQFullEvents);
145 renameLSQFullEvents
146 .name(name() + ".LSQFullEvents")
147 .desc("Number of times rename has blocked due to LSQ full")
148 .prereq(renameLSQFullEvents);
149 renameFullRegistersEvents
150 .name(name() + ".FullRegisterEvents")
151 .desc("Number of times there has been no free registers")
152 .prereq(renameFullRegistersEvents);
153 renameRenamedOperands
154 .name(name() + ".RenamedOperands")
155 .desc("Number of destination operands rename has renamed")
156 .prereq(renameRenamedOperands);
157 renameRenameLookups
158 .name(name() + ".RenameLookups")
159 .desc("Number of register rename lookups that rename has made")
160 .prereq(renameRenameLookups);
161 renameCommittedMaps
162 .name(name() + ".CommittedMaps")
163 .desc("Number of HB maps that are committed")
164 .prereq(renameCommittedMaps);
165 renameUndoneMaps
166 .name(name() + ".UndoneMaps")
167 .desc("Number of HB maps that are undone due to squashing")
168 .prereq(renameUndoneMaps);
169 renamedSerializing
170 .name(name() + ".serializingInsts")
171 .desc("count of serializing insts renamed")
172 .flags(Stats::total)
173 ;
174 renamedTempSerializing
175 .name(name() + ".tempSerializingInsts")
176 .desc("count of temporary serializing insts renamed")
177 .flags(Stats::total)
178 ;
179 renameSkidInsts
180 .name(name() + ".skidInsts")
181 .desc("count of insts added to the skid buffer")
182 .flags(Stats::total)
183 ;
184 intRenameLookups
185 .name(name() + ".int_rename_lookups")
186 .desc("Number of integer rename lookups")
187 .prereq(intRenameLookups);
188 fpRenameLookups
189 .name(name() + ".fp_rename_lookups")
190 .desc("Number of floating rename lookups")
191 .prereq(fpRenameLookups);
192}
193
194template <class Impl>
195void
196DefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
197{
198 timeBuffer = tb_ptr;
199
200 // Setup wire to read information from time buffer, from IEW stage.
201 fromIEW = timeBuffer->getWire(-iewToRenameDelay);
202
203 // Setup wire to read infromation from time buffer, from commit stage.
204 fromCommit = timeBuffer->getWire(-commitToRenameDelay);
205
206 // Setup wire to write information to previous stages.
207 toDecode = timeBuffer->getWire(0);
208}
209
210template <class Impl>
211void
212DefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
213{
214 renameQueue = rq_ptr;
215
216 // Setup wire to write information to future stages.
217 toIEW = renameQueue->getWire(0);
218}
219
220template <class Impl>
221void
222DefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
223{
224 decodeQueue = dq_ptr;
225
226 // Setup wire to get information from decode.
227 fromDecode = decodeQueue->getWire(-decodeToRenameDelay);
228}
229
230template <class Impl>
231void
232DefaultRename<Impl>::initStage()
233{
234 // Grab the number of free entries directly from the stages.
235 for (ThreadID tid = 0; tid < numThreads; tid++) {
236 freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid);
237 freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid);
238 freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid);
239 emptyROB[tid] = true;
240 }
241}
242
243template<class Impl>
244void
245DefaultRename<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
246{
247 activeThreads = at_ptr;
248}
249
250
251template <class Impl>
252void
253DefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[])
254{
255 for (ThreadID tid = 0; tid < numThreads; tid++)
256 renameMap[tid] = &rm_ptr[tid];
257}
258
259template <class Impl>
260void
261DefaultRename<Impl>::setFreeList(FreeList *fl_ptr)
262{
263 freeList = fl_ptr;
264}
265
266template<class Impl>
267void
268DefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard)
269{
270 scoreboard = _scoreboard;
271}
272
273template <class Impl>
274bool
275DefaultRename<Impl>::drain()
276{
277 // Rename is ready to switch out at any time.
278 cpu->signalDrained();
279 return true;
280}
281
282template <class Impl>
283void
284DefaultRename<Impl>::switchOut()
285{
286 // Clear any state, fix up the rename map.
287 for (ThreadID tid = 0; tid < numThreads; tid++) {
288 typename std::list<RenameHistory>::iterator hb_it =
289 historyBuffer[tid].begin();
290
291 while (!historyBuffer[tid].empty()) {
292 assert(hb_it != historyBuffer[tid].end());
293
294 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
295 "number %i.\n", tid, (*hb_it).instSeqNum);
296
297 // Tell the rename map to set the architected register to the
298 // previous physical register that it was renamed to.
299 renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
300
301 // Put the renamed physical register back on the free list.
302 freeList->addReg(hb_it->newPhysReg);
303
304 // Be sure to mark its register as ready if it's a misc register.
305 if (hb_it->newPhysReg >= maxPhysicalRegs) {
306 scoreboard->setReg(hb_it->newPhysReg);
307 }
308
309 historyBuffer[tid].erase(hb_it++);
310 }
311 insts[tid].clear();
312 skidBuffer[tid].clear();
313 }
314}
315
316template <class Impl>
317void
318DefaultRename<Impl>::takeOverFrom()
319{
320 _status = Inactive;
321 initStage();
322
323 // Reset all state prior to taking over from the other CPU.
324 for (ThreadID tid = 0; tid < numThreads; tid++) {
325 renameStatus[tid] = Idle;
326
327 stalls[tid].iew = false;
328 stalls[tid].commit = false;
329 serializeInst[tid] = NULL;
330
331 instsInProgress[tid] = 0;
332
333 emptyROB[tid] = true;
334
335 serializeOnNextInst[tid] = false;
336 }
337}
338
339template <class Impl>
340void
341DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, ThreadID tid)
342{
343 DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid);
344
345 // Clear the stall signal if rename was blocked or unblocking before.
346 // If it still needs to block, the blocking should happen the next
347 // cycle and there should be space to hold everything due to the squash.
348 if (renameStatus[tid] == Blocked ||
349 renameStatus[tid] == Unblocking) {
350 toDecode->renameUnblock[tid] = 1;
351
352 resumeSerialize = false;
353 serializeInst[tid] = NULL;
354 } else if (renameStatus[tid] == SerializeStall) {
355 if (serializeInst[tid]->seqNum <= squash_seq_num) {
356 DPRINTF(Rename, "Rename will resume serializing after squash\n");
357 resumeSerialize = true;
358 assert(serializeInst[tid]);
359 } else {
360 resumeSerialize = false;
361 toDecode->renameUnblock[tid] = 1;
362
363 serializeInst[tid] = NULL;
364 }
365 }
366
367 // Set the status to Squashing.
368 renameStatus[tid] = Squashing;
369
370 // Squash any instructions from decode.
371 unsigned squashCount = 0;
372
373 for (int i=0; i<fromDecode->size; i++) {
374 if (fromDecode->insts[i]->threadNumber == tid &&
375 fromDecode->insts[i]->seqNum > squash_seq_num) {
376 fromDecode->insts[i]->setSquashed();
377 wroteToTimeBuffer = true;
378 squashCount++;
379 }
380
381 }
382
383 // Clear the instruction list and skid buffer in case they have any
384 // insts in them.
385 insts[tid].clear();
386
387 // Clear the skid buffer in case it has any data in it.
388 skidBuffer[tid].clear();
389
390 doSquash(squash_seq_num, tid);
391}
392
393template <class Impl>
394void
395DefaultRename<Impl>::tick()
396{
397 wroteToTimeBuffer = false;
398
399 blockThisCycle = false;
400
401 bool status_change = false;
402
403 toIEWIndex = 0;
404
405 sortInsts();
406
407 list<ThreadID>::iterator threads = activeThreads->begin();
408 list<ThreadID>::iterator end = activeThreads->end();
409
410 // Check stall and squash signals.
411 while (threads != end) {
412 ThreadID tid = *threads++;
413
414 DPRINTF(Rename, "Processing [tid:%i]\n", tid);
415
416 status_change = checkSignalsAndUpdate(tid) || status_change;
417
418 rename(status_change, tid);
419 }
420
421 if (status_change) {
422 updateStatus();
423 }
424
425 if (wroteToTimeBuffer) {
426 DPRINTF(Activity, "Activity this cycle.\n");
427 cpu->activityThisCycle();
428 }
429
430 threads = activeThreads->begin();
431
432 while (threads != end) {
433 ThreadID tid = *threads++;
434
435 // If we committed this cycle then doneSeqNum will be > 0
436 if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
437 !fromCommit->commitInfo[tid].squash &&
438 renameStatus[tid] != Squashing) {
439
440 removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum,
441 tid);
442 }
443 }
444
445 // @todo: make into updateProgress function
446 for (ThreadID tid = 0; tid < numThreads; tid++) {
447 instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched;
448
449 assert(instsInProgress[tid] >=0);
450 }
451
452}
453
454template<class Impl>
455void
456DefaultRename<Impl>::rename(bool &status_change, ThreadID tid)
457{
458 // If status is Running or idle,
459 // call renameInsts()
460 // If status is Unblocking,
461 // buffer any instructions coming from decode
462 // continue trying to empty skid buffer
463 // check if stall conditions have passed
464
465 if (renameStatus[tid] == Blocked) {
466 ++renameBlockCycles;
467 } else if (renameStatus[tid] == Squashing) {
468 ++renameSquashCycles;
469 } else if (renameStatus[tid] == SerializeStall) {
470 ++renameSerializeStallCycles;
471 // If we are currently in SerializeStall and resumeSerialize
472 // was set, then that means that we are resuming serializing
473 // this cycle. Tell the previous stages to block.
474 if (resumeSerialize) {
475 resumeSerialize = false;
476 block(tid);
477 toDecode->renameUnblock[tid] = false;
478 }
479 } else if (renameStatus[tid] == Unblocking) {
480 if (resumeUnblocking) {
481 block(tid);
482 resumeUnblocking = false;
483 toDecode->renameUnblock[tid] = false;
484 }
485 }
486
487 if (renameStatus[tid] == Running ||
488 renameStatus[tid] == Idle) {
489 DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run "
490 "stage.\n", tid);
491
492 renameInsts(tid);
493 } else if (renameStatus[tid] == Unblocking) {
494 renameInsts(tid);
495
496 if (validInsts()) {
497 // Add the current inputs to the skid buffer so they can be
498 // reprocessed when this stage unblocks.
499 skidInsert(tid);
500 }
501
502 // If we switched over to blocking, then there's a potential for
503 // an overall status change.
504 status_change = unblock(tid) || status_change || blockThisCycle;
505 }
506}
507
508template <class Impl>
509void
510DefaultRename<Impl>::renameInsts(ThreadID tid)
511{
512 // Instructions can be either in the skid buffer or the queue of
513 // instructions coming from decode, depending on the status.
514 int insts_available = renameStatus[tid] == Unblocking ?
515 skidBuffer[tid].size() : insts[tid].size();
516
517 // Check the decode queue to see if instructions are available.
518 // If there are no available instructions to rename, then do nothing.
519 if (insts_available == 0) {
520 DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n",
521 tid);
522 // Should I change status to idle?
523 ++renameIdleCycles;
524 return;
525 } else if (renameStatus[tid] == Unblocking) {
526 ++renameUnblockCycles;
527 } else if (renameStatus[tid] == Running) {
528 ++renameRunCycles;
529 }
530
531 DynInstPtr inst;
532
533 // Will have to do a different calculation for the number of free
534 // entries.
535 int free_rob_entries = calcFreeROBEntries(tid);
536 int free_iq_entries = calcFreeIQEntries(tid);
537 int free_lsq_entries = calcFreeLSQEntries(tid);
538 int min_free_entries = free_rob_entries;
539
540 FullSource source = ROB;
541
542 if (free_iq_entries < min_free_entries) {
543 min_free_entries = free_iq_entries;
544 source = IQ;
545 }
546
547 if (free_lsq_entries < min_free_entries) {
548 min_free_entries = free_lsq_entries;
549 source = LSQ;
550 }
551
552 // Check if there's any space left.
553 if (min_free_entries <= 0) {
554 DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ "
555 "entries.\n"
556 "ROB has %i free entries.\n"
557 "IQ has %i free entries.\n"
558 "LSQ has %i free entries.\n",
559 tid,
560 free_rob_entries,
561 free_iq_entries,
562 free_lsq_entries);
563
564 blockThisCycle = true;
565
566 block(tid);
567
568 incrFullStat(source);
569
570 return;
571 } else if (min_free_entries < insts_available) {
572 DPRINTF(Rename, "[tid:%u]: Will have to block this cycle."
573 "%i insts available, but only %i insts can be "
574 "renamed due to ROB/IQ/LSQ limits.\n",
575 tid, insts_available, min_free_entries);
576
577 insts_available = min_free_entries;
578
579 blockThisCycle = true;
580
581 incrFullStat(source);
582 }
583
584 InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ?
585 skidBuffer[tid] : insts[tid];
586
587 DPRINTF(Rename, "[tid:%u]: %i available instructions to "
588 "send iew.\n", tid, insts_available);
589
590 DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts "
591 "dispatched to IQ last cycle.\n",
592 tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched);
593
594 // Handle serializing the next instruction if necessary.
595 if (serializeOnNextInst[tid]) {
596 if (emptyROB[tid] && instsInProgress[tid] == 0) {
597 // ROB already empty; no need to serialize.
598 serializeOnNextInst[tid] = false;
599 } else if (!insts_to_rename.empty()) {
600 insts_to_rename.front()->setSerializeBefore();
601 }
602 }
603
604 int renamed_insts = 0;
605
606 while (insts_available > 0 && toIEWIndex < renameWidth) {
607 DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid);
608
609 assert(!insts_to_rename.empty());
610
611 inst = insts_to_rename.front();
612
613 insts_to_rename.pop_front();
614
615 if (renameStatus[tid] == Unblocking) {
616 DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%s from rename "
617 "skidBuffer\n", tid, inst->seqNum, inst->pcState());
618 }
619
620 if (inst->isSquashed()) {
621 DPRINTF(Rename, "[tid:%u]: instruction %i with PC %s is "
622 "squashed, skipping.\n", tid, inst->seqNum,
623 inst->pcState());
624
625 ++renameSquashedInsts;
626
627 // Decrement how many instructions are available.
628 --insts_available;
629
630 continue;
631 }
632
633 DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with "
634 "PC %s.\n", tid, inst->seqNum, inst->pcState());
635
636 // Handle serializeAfter/serializeBefore instructions.
637 // serializeAfter marks the next instruction as serializeBefore.
638 // serializeBefore makes the instruction wait in rename until the ROB
639 // is empty.
640
641 // In this model, IPR accesses are serialize before
642 // instructions, and store conditionals are serialize after
643 // instructions. This is mainly due to lack of support for
644 // out-of-order operations of either of those classes of
645 // instructions.
646 if ((inst->isIprAccess() || inst->isSerializeBefore()) &&
647 !inst->isSerializeHandled()) {
648 DPRINTF(Rename, "Serialize before instruction encountered.\n");
649
650 if (!inst->isTempSerializeBefore()) {
651 renamedSerializing++;
652 inst->setSerializeHandled();
653 } else {
654 renamedTempSerializing++;
655 }
656
657 // Change status over to SerializeStall so that other stages know
658 // what this is blocked on.
659 renameStatus[tid] = SerializeStall;
660
661 serializeInst[tid] = inst;
662
663 blockThisCycle = true;
664
665 break;
666 } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) &&
667 !inst->isSerializeHandled()) {
668 DPRINTF(Rename, "Serialize after instruction encountered.\n");
669
670 renamedSerializing++;
671
672 inst->setSerializeHandled();
673
674 serializeAfter(insts_to_rename, tid);
675 }
676
677 // Check here to make sure there are enough destination registers
678 // to rename to. Otherwise block.
679 if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) {
680 DPRINTF(Rename, "Blocking due to lack of free "
681 "physical registers to rename to.\n");
682 blockThisCycle = true;
683 insts_to_rename.push_front(inst);
684 ++renameFullRegistersEvents;
685
686 break;
687 }
688
689 renameSrcRegs(inst, inst->threadNumber);
690
691 renameDestRegs(inst, inst->threadNumber);
692
693 ++renamed_insts;
694
695#if TRACING_ON
696 inst->renameTick = curTick();
697#endif
698
699 // Put instruction in rename queue.
700 toIEW->insts[toIEWIndex] = inst;
701 ++(toIEW->size);
702
703 // Increment which instruction we're on.
704 ++toIEWIndex;
705
706 // Decrement how many instructions are available.
707 --insts_available;
708 }
709
710 instsInProgress[tid] += renamed_insts;
711 renameRenamedInsts += renamed_insts;
712
713 // If we wrote to the time buffer, record this.
714 if (toIEWIndex) {
715 wroteToTimeBuffer = true;
716 }
717
718 // Check if there's any instructions left that haven't yet been renamed.
719 // If so then block.
720 if (insts_available) {
721 blockThisCycle = true;
722 }
723
724 if (blockThisCycle) {
725 block(tid);
726 toDecode->renameUnblock[tid] = false;
727 }
728}
729
730template<class Impl>
731void
732DefaultRename<Impl>::skidInsert(ThreadID tid)
733{
734 DynInstPtr inst = NULL;
735
736 while (!insts[tid].empty()) {
737 inst = insts[tid].front();
738
739 insts[tid].pop_front();
740
741 assert(tid == inst->threadNumber);
742
743 DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC: %s into Rename "
744 "skidBuffer\n", tid, inst->seqNum, inst->pcState());
745
746 ++renameSkidInsts;
747
748 skidBuffer[tid].push_back(inst);
749 }
750
751 if (skidBuffer[tid].size() > skidBufferMax)
752 {
753 typename InstQueue::iterator it;
754 warn("Skidbuffer contents:\n");
755 for(it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++)
756 {
757 warn("[tid:%u]: %s [sn:%i].\n", tid,
758 (*it)->staticInst->disassemble(inst->instAddr()),
759 (*it)->seqNum);
760 }
761 panic("Skidbuffer Exceeded Max Size");
762 }
763}
764
765template <class Impl>
766void
767DefaultRename<Impl>::sortInsts()
768{
769 int insts_from_decode = fromDecode->size;
770#ifdef DEBUG
771 for (ThreadID tid = 0; tid < numThreads; tid++)
772 assert(insts[tid].empty());
773#endif
774 for (int i = 0; i < insts_from_decode; ++i) {
775 DynInstPtr inst = fromDecode->insts[i];
776 insts[inst->threadNumber].push_back(inst);
777 }
778}
779
780template<class Impl>
781bool
782DefaultRename<Impl>::skidsEmpty()
783{
784 list<ThreadID>::iterator threads = activeThreads->begin();
785 list<ThreadID>::iterator end = activeThreads->end();
786
787 while (threads != end) {
788 ThreadID tid = *threads++;
789
790 if (!skidBuffer[tid].empty())
791 return false;
792 }
793
794 return true;
795}
796
797template<class Impl>
798void
799DefaultRename<Impl>::updateStatus()
800{
801 bool any_unblocking = false;
802
803 list<ThreadID>::iterator threads = activeThreads->begin();
804 list<ThreadID>::iterator end = activeThreads->end();
805
806 while (threads != end) {
807 ThreadID tid = *threads++;
808
809 if (renameStatus[tid] == Unblocking) {
810 any_unblocking = true;
811 break;
812 }
813 }
814
815 // Rename will have activity if it's unblocking.
816 if (any_unblocking) {
817 if (_status == Inactive) {
818 _status = Active;
819
820 DPRINTF(Activity, "Activating stage.\n");
821
822 cpu->activateStage(O3CPU::RenameIdx);
823 }
824 } else {
825 // If it's not unblocking, then rename will not have any internal
826 // activity. Switch it to inactive.
827 if (_status == Active) {
828 _status = Inactive;
829 DPRINTF(Activity, "Deactivating stage.\n");
830
831 cpu->deactivateStage(O3CPU::RenameIdx);
832 }
833 }
834}
835
836template <class Impl>
837bool
838DefaultRename<Impl>::block(ThreadID tid)
839{
840 DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid);
841
842 // Add the current inputs onto the skid buffer, so they can be
843 // reprocessed when this stage unblocks.
844 skidInsert(tid);
845
846 // Only signal backwards to block if the previous stages do not think
847 // rename is already blocked.
848 if (renameStatus[tid] != Blocked) {
849 // If resumeUnblocking is set, we unblocked during the squash,
850 // but now we're have unblocking status. We need to tell earlier
851 // stages to block.
852 if (resumeUnblocking || renameStatus[tid] != Unblocking) {
853 toDecode->renameBlock[tid] = true;
854 toDecode->renameUnblock[tid] = false;
855 wroteToTimeBuffer = true;
856 }
857
858 // Rename can not go from SerializeStall to Blocked, otherwise
859 // it would not know to complete the serialize stall.
860 if (renameStatus[tid] != SerializeStall) {
861 // Set status to Blocked.
862 renameStatus[tid] = Blocked;
863 return true;
864 }
865 }
866
867 return false;
868}
869
870template <class Impl>
871bool
872DefaultRename<Impl>::unblock(ThreadID tid)
873{
874 DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid);
875
876 // Rename is done unblocking if the skid buffer is empty.
877 if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) {
878
879 DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid);
880
881 toDecode->renameUnblock[tid] = true;
882 wroteToTimeBuffer = true;
883
884 renameStatus[tid] = Running;
885 return true;
886 }
887
888 return false;
889}
890
891template <class Impl>
892void
893DefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, ThreadID tid)
894{
895 typename std::list<RenameHistory>::iterator hb_it =
896 historyBuffer[tid].begin();
897
898 // After a syscall squashes everything, the history buffer may be empty
899 // but the ROB may still be squashing instructions.
900 if (historyBuffer[tid].empty()) {
901 return;
902 }
903
904 // Go through the most recent instructions, undoing the mappings
905 // they did and freeing up the registers.
906 while (!historyBuffer[tid].empty() &&
907 (*hb_it).instSeqNum > squashed_seq_num) {
908 assert(hb_it != historyBuffer[tid].end());
909
910 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
911 "number %i.\n", tid, (*hb_it).instSeqNum);
912
913 // Tell the rename map to set the architected register to the
914 // previous physical register that it was renamed to.
915 renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
916
917 // Put the renamed physical register back on the free list.
918 freeList->addReg(hb_it->newPhysReg);
919
920 // Be sure to mark its register as ready if it's a misc register.
921 if (hb_it->newPhysReg >= maxPhysicalRegs) {
922 scoreboard->setReg(hb_it->newPhysReg);
923 }
924
925 historyBuffer[tid].erase(hb_it++);
926
927 ++renameUndoneMaps;
928 }
929}
930
931template<class Impl>
932void
933DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid)
934{
935 DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the "
936 "history buffer %u (size=%i), until [sn:%lli].\n",
937 tid, tid, historyBuffer[tid].size(), inst_seq_num);
938
939 typename std::list<RenameHistory>::iterator hb_it =
940 historyBuffer[tid].end();
941
942 --hb_it;
943
944 if (historyBuffer[tid].empty()) {
945 DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid);
946 return;
947 } else if (hb_it->instSeqNum > inst_seq_num) {
948 DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure "
949 "that a syscall happened recently.\n", tid);
950 return;
951 }
952
953 // Commit all the renames up until (and including) the committed sequence
954 // number. Some or even all of the committed instructions may not have
955 // rename histories if they did not have destination registers that were
956 // renamed.
957 while (!historyBuffer[tid].empty() &&
958 hb_it != historyBuffer[tid].end() &&
959 (*hb_it).instSeqNum <= inst_seq_num) {
960
961 DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, "
962 "[sn:%lli].\n",
963 tid, (*hb_it).prevPhysReg, (*hb_it).instSeqNum);
964
965 freeList->addReg((*hb_it).prevPhysReg);
966 ++renameCommittedMaps;
967
968 historyBuffer[tid].erase(hb_it--);
969 }
970}
971
972template <class Impl>
973inline void
974DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid)
975{
976 assert(renameMap[tid] != 0);
977
978 unsigned num_src_regs = inst->numSrcRegs();
979
980 // Get the architectual register numbers from the source and
981 // destination operands, and redirect them to the right register.
982 // Will need to mark dependencies though.
983 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) {
984 RegIndex src_reg = inst->srcRegIdx(src_idx);
985 RegIndex flat_src_reg = src_reg;
986 if (src_reg < TheISA::FP_Base_DepTag) {
987 flat_src_reg = inst->tcBase()->flattenIntIndex(src_reg);
988 DPRINTF(Rename, "Flattening index %d to %d.\n",
989 (int)src_reg, (int)flat_src_reg);
990 } else if (src_reg < TheISA::Ctrl_Base_DepTag) {
991 src_reg = src_reg - TheISA::FP_Base_DepTag;
992 flat_src_reg = inst->tcBase()->flattenFloatIndex(src_reg);
993 DPRINTF(Rename, "Flattening index %d to %d.\n",
994 (int)src_reg, (int)flat_src_reg);
995 flat_src_reg += TheISA::NumIntRegs;
996 } else if (src_reg < TheISA::Max_DepTag) {
997 flat_src_reg = src_reg - TheISA::Ctrl_Base_DepTag +
998 TheISA::NumFloatRegs + TheISA::NumIntRegs;
999 DPRINTF(Rename, "Adjusting reg index from %d to %d.\n",
1000 src_reg, flat_src_reg);
1001 } else {
1002 panic("Reg index is out of bound: %d.", src_reg);
1003 }
1004
1005 inst->flattenSrcReg(src_idx, flat_src_reg);
1006
1007 // Look up the source registers to get the phys. register they've
1008 // been renamed to, and set the sources to those registers.
1009 PhysRegIndex renamed_reg = renameMap[tid]->lookup(flat_src_reg);
1010
1011 DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got "
1012 "physical reg %i.\n", tid, (int)flat_src_reg,
1013 (int)renamed_reg);
1014
1015 inst->renameSrcReg(src_idx, renamed_reg);
1016
1017 // See if the register is ready or not.
1018 if (scoreboard->getReg(renamed_reg) == true) {
1019 DPRINTF(Rename, "[tid:%u]: Register %d is ready.\n",
1020 tid, renamed_reg);
1021
1022 inst->markSrcRegReady(src_idx);
1023 } else {
1024 DPRINTF(Rename, "[tid:%u]: Register %d is not ready.\n",
1025 tid, renamed_reg);
1026 }
1027
1028 ++renameRenameLookups;
1029 inst->isFloating() ? fpRenameLookups++ : intRenameLookups++;
1030 }
1031}
1032
1033template <class Impl>
1034inline void
1035DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid)
1036{
1037 typename RenameMap::RenameInfo rename_result;
1038
1039 unsigned num_dest_regs = inst->numDestRegs();
1040
1041 // Rename the destination registers.
1042 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) {
1043 RegIndex dest_reg = inst->destRegIdx(dest_idx);
1044 RegIndex flat_dest_reg = dest_reg;
1045 if (dest_reg < TheISA::FP_Base_DepTag) {
1046 // Integer registers are flattened.
1047 flat_dest_reg = inst->tcBase()->flattenIntIndex(dest_reg);
1048 DPRINTF(Rename, "Flattening index %d to %d.\n",
1049 (int)dest_reg, (int)flat_dest_reg);
1050 } else if (dest_reg < TheISA::Ctrl_Base_DepTag) {
1051 dest_reg = dest_reg - TheISA::FP_Base_DepTag;
1052 flat_dest_reg = inst->tcBase()->flattenFloatIndex(dest_reg);
1053 DPRINTF(Rename, "Flattening index %d to %d.\n",
1054 (int)dest_reg, (int)flat_dest_reg);
1055 flat_dest_reg += TheISA::NumIntRegs;
1056 } else if (dest_reg < TheISA::Max_DepTag) {
1057 // Floating point and Miscellaneous registers need their indexes
1058 // adjusted to account for the expanded number of flattened int regs.
1059 flat_dest_reg = dest_reg - TheISA::Ctrl_Base_DepTag +
1060 TheISA::NumIntRegs + TheISA::NumFloatRegs;
1061 DPRINTF(Rename, "Adjusting reg index from %d to %d.\n",
1062 dest_reg, flat_dest_reg);
1063 } else {
1064 panic("Reg index is out of bound: %d.", dest_reg);
1065 }
1066
1067 inst->flattenDestReg(dest_idx, flat_dest_reg);
1068
1069 // Get the physical register that the destination will be
1070 // renamed to.
1071 rename_result = renameMap[tid]->rename(flat_dest_reg);
1072
1073 //Mark Scoreboard entry as not ready
1074 if (dest_reg < TheISA::Ctrl_Base_DepTag)
1075 scoreboard->unsetReg(rename_result.first);
1076
1077 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical "
1078 "reg %i.\n", tid, (int)flat_dest_reg,
1079 (int)rename_result.first);
1080
1081 // Record the rename information so that a history can be kept.
1082 RenameHistory hb_entry(inst->seqNum, flat_dest_reg,
1083 rename_result.first,
1084 rename_result.second);
1085
1086 historyBuffer[tid].push_front(hb_entry);
1087
1088 DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer "
1089 "(size=%i), [sn:%lli].\n",tid,
1090 historyBuffer[tid].size(),
1091 (*historyBuffer[tid].begin()).instSeqNum);
1092
1093 // Tell the instruction to rename the appropriate destination
1094 // register (dest_idx) to the new physical register
1095 // (rename_result.first), and record the previous physical
1096 // register that the same logical register was renamed to
1097 // (rename_result.second).
1098 inst->renameDestReg(dest_idx,
1099 rename_result.first,
1100 rename_result.second);
1101
1102 ++renameRenamedOperands;
1103 }
1104}
1105
1106template <class Impl>
1107inline int
1108DefaultRename<Impl>::calcFreeROBEntries(ThreadID tid)
1109{
1110 int num_free = freeEntries[tid].robEntries -
1111 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1112
1113 //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free);
1114
1115 return num_free;
1116}
1117
1118template <class Impl>
1119inline int
1120DefaultRename<Impl>::calcFreeIQEntries(ThreadID tid)
1121{
1122 int num_free = freeEntries[tid].iqEntries -
1123 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1124
1125 //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free);
1126
1127 return num_free;
1128}
1129
1130template <class Impl>
1131inline int
1132DefaultRename<Impl>::calcFreeLSQEntries(ThreadID tid)
1133{
1134 int num_free = freeEntries[tid].lsqEntries -
1135 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ);
1136
1137 //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free);
1138
1139 return num_free;
1140}
1141
1142template <class Impl>
1143unsigned
1144DefaultRename<Impl>::validInsts()
1145{
1146 unsigned inst_count = 0;
1147
1148 for (int i=0; i<fromDecode->size; i++) {
1149 if (!fromDecode->insts[i]->isSquashed())
1150 inst_count++;
1151 }
1152
1153 return inst_count;
1154}
1155
1156template <class Impl>
1157void
1158DefaultRename<Impl>::readStallSignals(ThreadID tid)
1159{
1160 if (fromIEW->iewBlock[tid]) {
1161 stalls[tid].iew = true;
1162 }
1163
1164 if (fromIEW->iewUnblock[tid]) {
1165 assert(stalls[tid].iew);
1166 stalls[tid].iew = false;
1167 }
1168
1169 if (fromCommit->commitBlock[tid]) {
1170 stalls[tid].commit = true;
1171 }
1172
1173 if (fromCommit->commitUnblock[tid]) {
1174 assert(stalls[tid].commit);
1175 stalls[tid].commit = false;
1176 }
1177}
1178
1179template <class Impl>
1180bool
1181DefaultRename<Impl>::checkStall(ThreadID tid)
1182{
1183 bool ret_val = false;
1184
1185 if (stalls[tid].iew) {
1186 DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid);
1187 ret_val = true;
1188 } else if (stalls[tid].commit) {
1189 DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid);
1190 ret_val = true;
1191 } else if (calcFreeROBEntries(tid) <= 0) {
1192 DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid);
1193 ret_val = true;
1194 } else if (calcFreeIQEntries(tid) <= 0) {
1195 DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid);
1196 ret_val = true;
1197 } else if (calcFreeLSQEntries(tid) <= 0) {
1198 DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid);
1199 ret_val = true;
1200 } else if (renameMap[tid]->numFreeEntries() <= 0) {
1201 DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid);
1202 ret_val = true;
1203 } else if (renameStatus[tid] == SerializeStall &&
1204 (!emptyROB[tid] || instsInProgress[tid])) {
1205 DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not "
1206 "empty.\n",
1207 tid);
1208 ret_val = true;
1209 }
1210
1211 return ret_val;
1212}
1213
1214template <class Impl>
1215void
1216DefaultRename<Impl>::readFreeEntries(ThreadID tid)
1217{
|
1236 }
1237
1238 DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n",
1239 tid,
1240 freeEntries[tid].iqEntries,
1241 freeEntries[tid].robEntries,
1242 freeEntries[tid].lsqEntries);
1243
1244 DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n",
1245 tid, instsInProgress[tid]);
1246}
1247
1248template <class Impl>
1249bool
1250DefaultRename<Impl>::checkSignalsAndUpdate(ThreadID tid)
1251{
1252 // Check if there's a squash signal, squash if there is
1253 // Check stall signals, block if necessary.
1254 // If status was blocked
1255 // check if stall conditions have passed
1256 // if so then go to unblocking
1257 // If status was Squashing
1258 // check if squashing is not high. Switch to running this cycle.
1259 // If status was serialize stall
1260 // check if ROB is empty and no insts are in flight to the ROB
1261
1262 readFreeEntries(tid);
1263 readStallSignals(tid);
1264
1265 if (fromCommit->commitInfo[tid].squash) {
1266 DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from "
1267 "commit.\n", tid);
1268
1269 squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
1270
1271 return true;
1272 }
1273
1274 if (fromCommit->commitInfo[tid].robSquashing) {
1275 DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid);
1276
1277 renameStatus[tid] = Squashing;
1278
1279 return true;
1280 }
1281
1282 if (checkStall(tid)) {
1283 return block(tid);
1284 }
1285
1286 if (renameStatus[tid] == Blocked) {
1287 DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n",
1288 tid);
1289
1290 renameStatus[tid] = Unblocking;
1291
1292 unblock(tid);
1293
1294 return true;
1295 }
1296
1297 if (renameStatus[tid] == Squashing) {
1298 // Switch status to running if rename isn't being told to block or
1299 // squash this cycle.
1300 if (resumeSerialize) {
1301 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n",
1302 tid);
1303
1304 renameStatus[tid] = SerializeStall;
1305 return true;
1306 } else if (resumeUnblocking) {
1307 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n",
1308 tid);
1309 renameStatus[tid] = Unblocking;
1310 return true;
1311 } else {
1312 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n",
1313 tid);
1314
1315 renameStatus[tid] = Running;
1316 return false;
1317 }
1318 }
1319
1320 if (renameStatus[tid] == SerializeStall) {
1321 // Stall ends once the ROB is free.
1322 DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to "
1323 "unblocking.\n", tid);
1324
1325 DynInstPtr serial_inst = serializeInst[tid];
1326
1327 renameStatus[tid] = Unblocking;
1328
1329 unblock(tid);
1330
1331 DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with "
1332 "PC %s.\n", tid, serial_inst->seqNum, serial_inst->pcState());
1333
1334 // Put instruction into queue here.
1335 serial_inst->clearSerializeBefore();
1336
1337 if (!skidBuffer[tid].empty()) {
1338 skidBuffer[tid].push_front(serial_inst);
1339 } else {
1340 insts[tid].push_front(serial_inst);
1341 }
1342
1343 DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename."
1344 " Adding to front of list.\n", tid);
1345
1346 serializeInst[tid] = NULL;
1347
1348 return true;
1349 }
1350
1351 // If we've reached this point, we have not gotten any signals that
1352 // cause rename to change its status. Rename remains the same as before.
1353 return false;
1354}
1355
1356template<class Impl>
1357void
1358DefaultRename<Impl>::serializeAfter(InstQueue &inst_list, ThreadID tid)
1359{
1360 if (inst_list.empty()) {
1361 // Mark a bit to say that I must serialize on the next instruction.
1362 serializeOnNextInst[tid] = true;
1363 return;
1364 }
1365
1366 // Set the next instruction as serializing.
1367 inst_list.front()->setSerializeBefore();
1368}
1369
1370template <class Impl>
1371inline void
1372DefaultRename<Impl>::incrFullStat(const FullSource &source)
1373{
1374 switch (source) {
1375 case ROB:
1376 ++renameROBFullEvents;
1377 break;
1378 case IQ:
1379 ++renameIQFullEvents;
1380 break;
1381 case LSQ:
1382 ++renameLSQFullEvents;
1383 break;
1384 default:
1385 panic("Rename full stall stat should be incremented for a reason!");
1386 break;
1387 }
1388}
1389
1390template <class Impl>
1391void
1392DefaultRename<Impl>::dumpHistory()
1393{
1394 typename std::list<RenameHistory>::iterator buf_it;
1395
1396 for (ThreadID tid = 0; tid < numThreads; tid++) {
1397
1398 buf_it = historyBuffer[tid].begin();
1399
1400 while (buf_it != historyBuffer[tid].end()) {
1401 cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys "
1402 "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg,
1403 (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg);
1404
1405 buf_it++;
1406 }
1407 }
1408}
| 1228 }
1229
1230 DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n",
1231 tid,
1232 freeEntries[tid].iqEntries,
1233 freeEntries[tid].robEntries,
1234 freeEntries[tid].lsqEntries);
1235
1236 DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n",
1237 tid, instsInProgress[tid]);
1238}
1239
1240template <class Impl>
1241bool
1242DefaultRename<Impl>::checkSignalsAndUpdate(ThreadID tid)
1243{
1244 // Check if there's a squash signal, squash if there is
1245 // Check stall signals, block if necessary.
1246 // If status was blocked
1247 // check if stall conditions have passed
1248 // if so then go to unblocking
1249 // If status was Squashing
1250 // check if squashing is not high. Switch to running this cycle.
1251 // If status was serialize stall
1252 // check if ROB is empty and no insts are in flight to the ROB
1253
1254 readFreeEntries(tid);
1255 readStallSignals(tid);
1256
1257 if (fromCommit->commitInfo[tid].squash) {
1258 DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from "
1259 "commit.\n", tid);
1260
1261 squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
1262
1263 return true;
1264 }
1265
1266 if (fromCommit->commitInfo[tid].robSquashing) {
1267 DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid);
1268
1269 renameStatus[tid] = Squashing;
1270
1271 return true;
1272 }
1273
1274 if (checkStall(tid)) {
1275 return block(tid);
1276 }
1277
1278 if (renameStatus[tid] == Blocked) {
1279 DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n",
1280 tid);
1281
1282 renameStatus[tid] = Unblocking;
1283
1284 unblock(tid);
1285
1286 return true;
1287 }
1288
1289 if (renameStatus[tid] == Squashing) {
1290 // Switch status to running if rename isn't being told to block or
1291 // squash this cycle.
1292 if (resumeSerialize) {
1293 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n",
1294 tid);
1295
1296 renameStatus[tid] = SerializeStall;
1297 return true;
1298 } else if (resumeUnblocking) {
1299 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n",
1300 tid);
1301 renameStatus[tid] = Unblocking;
1302 return true;
1303 } else {
1304 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n",
1305 tid);
1306
1307 renameStatus[tid] = Running;
1308 return false;
1309 }
1310 }
1311
1312 if (renameStatus[tid] == SerializeStall) {
1313 // Stall ends once the ROB is free.
1314 DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to "
1315 "unblocking.\n", tid);
1316
1317 DynInstPtr serial_inst = serializeInst[tid];
1318
1319 renameStatus[tid] = Unblocking;
1320
1321 unblock(tid);
1322
1323 DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with "
1324 "PC %s.\n", tid, serial_inst->seqNum, serial_inst->pcState());
1325
1326 // Put instruction into queue here.
1327 serial_inst->clearSerializeBefore();
1328
1329 if (!skidBuffer[tid].empty()) {
1330 skidBuffer[tid].push_front(serial_inst);
1331 } else {
1332 insts[tid].push_front(serial_inst);
1333 }
1334
1335 DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename."
1336 " Adding to front of list.\n", tid);
1337
1338 serializeInst[tid] = NULL;
1339
1340 return true;
1341 }
1342
1343 // If we've reached this point, we have not gotten any signals that
1344 // cause rename to change its status. Rename remains the same as before.
1345 return false;
1346}
1347
1348template<class Impl>
1349void
1350DefaultRename<Impl>::serializeAfter(InstQueue &inst_list, ThreadID tid)
1351{
1352 if (inst_list.empty()) {
1353 // Mark a bit to say that I must serialize on the next instruction.
1354 serializeOnNextInst[tid] = true;
1355 return;
1356 }
1357
1358 // Set the next instruction as serializing.
1359 inst_list.front()->setSerializeBefore();
1360}
1361
1362template <class Impl>
1363inline void
1364DefaultRename<Impl>::incrFullStat(const FullSource &source)
1365{
1366 switch (source) {
1367 case ROB:
1368 ++renameROBFullEvents;
1369 break;
1370 case IQ:
1371 ++renameIQFullEvents;
1372 break;
1373 case LSQ:
1374 ++renameLSQFullEvents;
1375 break;
1376 default:
1377 panic("Rename full stall stat should be incremented for a reason!");
1378 break;
1379 }
1380}
1381
1382template <class Impl>
1383void
1384DefaultRename<Impl>::dumpHistory()
1385{
1386 typename std::list<RenameHistory>::iterator buf_it;
1387
1388 for (ThreadID tid = 0; tid < numThreads; tid++) {
1389
1390 buf_it = historyBuffer[tid].begin();
1391
1392 while (buf_it != historyBuffer[tid].end()) {
1393 cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys "
1394 "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg,
1395 (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg);
1396
1397 buf_it++;
1398 }
1399 }
1400}
|