1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#include <list>
33
34#include "arch/isa_traits.hh"
35#include "arch/registers.hh"
36#include "config/full_system.hh"
37#include "config/the_isa.hh"
38#include "cpu/o3/rename.hh"
39#include "params/DerivO3CPU.hh"
40
41using namespace std;
42
43template <class Impl>
44DefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params)
45 : cpu(_cpu),
46 iewToRenameDelay(params->iewToRenameDelay),
47 decodeToRenameDelay(params->decodeToRenameDelay),
48 commitToRenameDelay(params->commitToRenameDelay),
49 renameWidth(params->renameWidth),
50 commitWidth(params->commitWidth),
51 resumeSerialize(false),
52 resumeUnblocking(false),
53 numThreads(params->numThreads),
54 maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs)
55{
56 _status = Inactive;
57
58 for (ThreadID tid = 0; tid < numThreads; tid++) {
59 renameStatus[tid] = Idle;
60
61 freeEntries[tid].iqEntries = 0;
62 freeEntries[tid].lsqEntries = 0;
63 freeEntries[tid].robEntries = 0;
64
65 stalls[tid].iew = false;
66 stalls[tid].commit = false;
67 serializeInst[tid] = NULL;
68
69 instsInProgress[tid] = 0;
70
71 emptyROB[tid] = true;
72
73 serializeOnNextInst[tid] = false;
74 }
75
76 // @todo: Make into a parameter.
77 skidBufferMax = (2 * (iewToRenameDelay * params->decodeWidth)) + renameWidth;
78}
79
80template <class Impl>
81std::string
82DefaultRename<Impl>::name() const
83{
84 return cpu->name() + ".rename";
85}
86
87template <class Impl>
88void
89DefaultRename<Impl>::regStats()
90{
91 renameSquashCycles
92 .name(name() + ".RENAME:SquashCycles")
93 .desc("Number of cycles rename is squashing")
94 .prereq(renameSquashCycles);
95 renameIdleCycles
96 .name(name() + ".RENAME:IdleCycles")
97 .desc("Number of cycles rename is idle")
98 .prereq(renameIdleCycles);
99 renameBlockCycles
100 .name(name() + ".RENAME:BlockCycles")
101 .desc("Number of cycles rename is blocking")
102 .prereq(renameBlockCycles);
103 renameSerializeStallCycles
104 .name(name() + ".RENAME:serializeStallCycles")
105 .desc("count of cycles rename stalled for serializing inst")
106 .flags(Stats::total);
107 renameRunCycles
108 .name(name() + ".RENAME:RunCycles")
109 .desc("Number of cycles rename is running")
110 .prereq(renameIdleCycles);
111 renameUnblockCycles
112 .name(name() + ".RENAME:UnblockCycles")
113 .desc("Number of cycles rename is unblocking")
114 .prereq(renameUnblockCycles);
115 renameRenamedInsts
116 .name(name() + ".RENAME:RenamedInsts")
117 .desc("Number of instructions processed by rename")
118 .prereq(renameRenamedInsts);
119 renameSquashedInsts
120 .name(name() + ".RENAME:SquashedInsts")
121 .desc("Number of squashed instructions processed by rename")
122 .prereq(renameSquashedInsts);
123 renameROBFullEvents
124 .name(name() + ".RENAME:ROBFullEvents")
125 .desc("Number of times rename has blocked due to ROB full")
126 .prereq(renameROBFullEvents);
127 renameIQFullEvents
128 .name(name() + ".RENAME:IQFullEvents")
129 .desc("Number of times rename has blocked due to IQ full")
130 .prereq(renameIQFullEvents);
131 renameLSQFullEvents
132 .name(name() + ".RENAME:LSQFullEvents")
133 .desc("Number of times rename has blocked due to LSQ full")
134 .prereq(renameLSQFullEvents);
135 renameFullRegistersEvents
136 .name(name() + ".RENAME:FullRegisterEvents")
137 .desc("Number of times there has been no free registers")
138 .prereq(renameFullRegistersEvents);
139 renameRenamedOperands
140 .name(name() + ".RENAME:RenamedOperands")
141 .desc("Number of destination operands rename has renamed")
142 .prereq(renameRenamedOperands);
143 renameRenameLookups
144 .name(name() + ".RENAME:RenameLookups")
145 .desc("Number of register rename lookups that rename has made")
146 .prereq(renameRenameLookups);
147 renameCommittedMaps
148 .name(name() + ".RENAME:CommittedMaps")
149 .desc("Number of HB maps that are committed")
150 .prereq(renameCommittedMaps);
151 renameUndoneMaps
152 .name(name() + ".RENAME:UndoneMaps")
153 .desc("Number of HB maps that are undone due to squashing")
154 .prereq(renameUndoneMaps);
155 renamedSerializing
156 .name(name() + ".RENAME:serializingInsts")
157 .desc("count of serializing insts renamed")
158 .flags(Stats::total)
159 ;
160 renamedTempSerializing
161 .name(name() + ".RENAME:tempSerializingInsts")
162 .desc("count of temporary serializing insts renamed")
163 .flags(Stats::total)
164 ;
165 renameSkidInsts
166 .name(name() + ".RENAME:skidInsts")
167 .desc("count of insts added to the skid buffer")
168 .flags(Stats::total)
169 ;
170}
171
172template <class Impl>
173void
174DefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
175{
176 timeBuffer = tb_ptr;
177
178 // Setup wire to read information from time buffer, from IEW stage.
179 fromIEW = timeBuffer->getWire(-iewToRenameDelay);
180
181 // Setup wire to read infromation from time buffer, from commit stage.
182 fromCommit = timeBuffer->getWire(-commitToRenameDelay);
183
184 // Setup wire to write information to previous stages.
185 toDecode = timeBuffer->getWire(0);
186}
187
188template <class Impl>
189void
190DefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
191{
192 renameQueue = rq_ptr;
193
194 // Setup wire to write information to future stages.
195 toIEW = renameQueue->getWire(0);
196}
197
198template <class Impl>
199void
200DefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
201{
202 decodeQueue = dq_ptr;
203
204 // Setup wire to get information from decode.
205 fromDecode = decodeQueue->getWire(-decodeToRenameDelay);
206}
207
208template <class Impl>
209void
210DefaultRename<Impl>::initStage()
211{
212 // Grab the number of free entries directly from the stages.
213 for (ThreadID tid = 0; tid < numThreads; tid++) {
214 freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid);
215 freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid);
216 freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid);
217 emptyROB[tid] = true;
218 }
219}
220
221template<class Impl>
222void
223DefaultRename<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
224{
225 activeThreads = at_ptr;
226}
227
228
229template <class Impl>
230void
231DefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[])
232{
233 for (ThreadID tid = 0; tid < numThreads; tid++)
234 renameMap[tid] = &rm_ptr[tid];
235}
236
237template <class Impl>
238void
239DefaultRename<Impl>::setFreeList(FreeList *fl_ptr)
240{
241 freeList = fl_ptr;
242}
243
244template<class Impl>
245void
246DefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard)
247{
248 scoreboard = _scoreboard;
249}
250
251template <class Impl>
252bool
253DefaultRename<Impl>::drain()
254{
255 // Rename is ready to switch out at any time.
256 cpu->signalDrained();
257 return true;
258}
259
260template <class Impl>
261void
262DefaultRename<Impl>::switchOut()
263{
264 // Clear any state, fix up the rename map.
265 for (ThreadID tid = 0; tid < numThreads; tid++) {
266 typename std::list<RenameHistory>::iterator hb_it =
267 historyBuffer[tid].begin();
268
269 while (!historyBuffer[tid].empty()) {
270 assert(hb_it != historyBuffer[tid].end());
271
272 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
273 "number %i.\n", tid, (*hb_it).instSeqNum);
274
275 // Tell the rename map to set the architected register to the
276 // previous physical register that it was renamed to.
277 renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
278
279 // Put the renamed physical register back on the free list.
280 freeList->addReg(hb_it->newPhysReg);
281
282 // Be sure to mark its register as ready if it's a misc register.
283 if (hb_it->newPhysReg >= maxPhysicalRegs) {
284 scoreboard->setReg(hb_it->newPhysReg);
285 }
286
287 historyBuffer[tid].erase(hb_it++);
288 }
289 insts[tid].clear();
290 skidBuffer[tid].clear();
291 }
292}
293
294template <class Impl>
295void
296DefaultRename<Impl>::takeOverFrom()
297{
298 _status = Inactive;
299 initStage();
300
301 // Reset all state prior to taking over from the other CPU.
302 for (ThreadID tid = 0; tid < numThreads; tid++) {
303 renameStatus[tid] = Idle;
304
305 stalls[tid].iew = false;
306 stalls[tid].commit = false;
307 serializeInst[tid] = NULL;
308
309 instsInProgress[tid] = 0;
310
311 emptyROB[tid] = true;
312
313 serializeOnNextInst[tid] = false;
314 }
315}
316
317template <class Impl>
318void
319DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, ThreadID tid)
320{
321 DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid);
322
323 // Clear the stall signal if rename was blocked or unblocking before.
324 // If it still needs to block, the blocking should happen the next
325 // cycle and there should be space to hold everything due to the squash.
326 if (renameStatus[tid] == Blocked ||
327 renameStatus[tid] == Unblocking) {
328 toDecode->renameUnblock[tid] = 1;
329
330 resumeSerialize = false;
331 serializeInst[tid] = NULL;
332 } else if (renameStatus[tid] == SerializeStall) {
333 if (serializeInst[tid]->seqNum <= squash_seq_num) {
334 DPRINTF(Rename, "Rename will resume serializing after squash\n");
335 resumeSerialize = true;
336 assert(serializeInst[tid]);
337 } else {
338 resumeSerialize = false;
339 toDecode->renameUnblock[tid] = 1;
340
341 serializeInst[tid] = NULL;
342 }
343 }
344
345 // Set the status to Squashing.
346 renameStatus[tid] = Squashing;
347
348 // Squash any instructions from decode.
349 unsigned squashCount = 0;
350
351 for (int i=0; i<fromDecode->size; i++) {
352 if (fromDecode->insts[i]->threadNumber == tid &&
353 fromDecode->insts[i]->seqNum > squash_seq_num) {
354 fromDecode->insts[i]->setSquashed();
355 wroteToTimeBuffer = true;
356 squashCount++;
357 }
358
359 }
360
361 // Clear the instruction list and skid buffer in case they have any
362 // insts in them.
363 insts[tid].clear();
364
365 // Clear the skid buffer in case it has any data in it.
366 skidBuffer[tid].clear();
367
368 doSquash(squash_seq_num, tid);
369}
370
371template <class Impl>
372void
373DefaultRename<Impl>::tick()
374{
375 wroteToTimeBuffer = false;
376
377 blockThisCycle = false;
378
379 bool status_change = false;
380
381 toIEWIndex = 0;
382
383 sortInsts();
384
385 list<ThreadID>::iterator threads = activeThreads->begin();
386 list<ThreadID>::iterator end = activeThreads->end();
387
388 // Check stall and squash signals.
389 while (threads != end) {
390 ThreadID tid = *threads++;
391
392 DPRINTF(Rename, "Processing [tid:%i]\n", tid);
393
394 status_change = checkSignalsAndUpdate(tid) || status_change;
395
396 rename(status_change, tid);
397 }
398
399 if (status_change) {
400 updateStatus();
401 }
402
403 if (wroteToTimeBuffer) {
404 DPRINTF(Activity, "Activity this cycle.\n");
405 cpu->activityThisCycle();
406 }
407
408 threads = activeThreads->begin();
409
410 while (threads != end) {
411 ThreadID tid = *threads++;
412
413 // If we committed this cycle then doneSeqNum will be > 0
414 if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
415 !fromCommit->commitInfo[tid].squash &&
416 renameStatus[tid] != Squashing) {
417
418 removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum,
419 tid);
420 }
421 }
422
423 // @todo: make into updateProgress function
424 for (ThreadID tid = 0; tid < numThreads; tid++) {
425 instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched;
426
427 assert(instsInProgress[tid] >=0);
428 }
429
430}
431
432template<class Impl>
433void
434DefaultRename<Impl>::rename(bool &status_change, ThreadID tid)
435{
436 // If status is Running or idle,
437 // call renameInsts()
438 // If status is Unblocking,
439 // buffer any instructions coming from decode
440 // continue trying to empty skid buffer
441 // check if stall conditions have passed
442
443 if (renameStatus[tid] == Blocked) {
444 ++renameBlockCycles;
445 } else if (renameStatus[tid] == Squashing) {
446 ++renameSquashCycles;
447 } else if (renameStatus[tid] == SerializeStall) {
448 ++renameSerializeStallCycles;
449 // If we are currently in SerializeStall and resumeSerialize
450 // was set, then that means that we are resuming serializing
451 // this cycle. Tell the previous stages to block.
452 if (resumeSerialize) {
453 resumeSerialize = false;
454 block(tid);
455 toDecode->renameUnblock[tid] = false;
456 }
457 } else if (renameStatus[tid] == Unblocking) {
458 if (resumeUnblocking) {
459 block(tid);
460 resumeUnblocking = false;
461 toDecode->renameUnblock[tid] = false;
462 }
463 }
464
465 if (renameStatus[tid] == Running ||
466 renameStatus[tid] == Idle) {
467 DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run "
468 "stage.\n", tid);
469
470 renameInsts(tid);
471 } else if (renameStatus[tid] == Unblocking) {
472 renameInsts(tid);
473
474 if (validInsts()) {
475 // Add the current inputs to the skid buffer so they can be
476 // reprocessed when this stage unblocks.
477 skidInsert(tid);
478 }
479
480 // If we switched over to blocking, then there's a potential for
481 // an overall status change.
482 status_change = unblock(tid) || status_change || blockThisCycle;
483 }
484}
485
486template <class Impl>
487void
488DefaultRename<Impl>::renameInsts(ThreadID tid)
489{
490 // Instructions can be either in the skid buffer or the queue of
491 // instructions coming from decode, depending on the status.
492 int insts_available = renameStatus[tid] == Unblocking ?
493 skidBuffer[tid].size() : insts[tid].size();
494
495 // Check the decode queue to see if instructions are available.
496 // If there are no available instructions to rename, then do nothing.
497 if (insts_available == 0) {
498 DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n",
499 tid);
500 // Should I change status to idle?
501 ++renameIdleCycles;
502 return;
503 } else if (renameStatus[tid] == Unblocking) {
504 ++renameUnblockCycles;
505 } else if (renameStatus[tid] == Running) {
506 ++renameRunCycles;
507 }
508
509 DynInstPtr inst;
510
511 // Will have to do a different calculation for the number of free
512 // entries.
513 int free_rob_entries = calcFreeROBEntries(tid);
514 int free_iq_entries = calcFreeIQEntries(tid);
515 int free_lsq_entries = calcFreeLSQEntries(tid);
516 int min_free_entries = free_rob_entries;
517
518 FullSource source = ROB;
519
520 if (free_iq_entries < min_free_entries) {
521 min_free_entries = free_iq_entries;
522 source = IQ;
523 }
524
525 if (free_lsq_entries < min_free_entries) {
526 min_free_entries = free_lsq_entries;
527 source = LSQ;
528 }
529
530 // Check if there's any space left.
531 if (min_free_entries <= 0) {
532 DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ "
533 "entries.\n"
534 "ROB has %i free entries.\n"
535 "IQ has %i free entries.\n"
536 "LSQ has %i free entries.\n",
537 tid,
538 free_rob_entries,
539 free_iq_entries,
540 free_lsq_entries);
541
542 blockThisCycle = true;
543
544 block(tid);
545
546 incrFullStat(source);
547
548 return;
549 } else if (min_free_entries < insts_available) {
550 DPRINTF(Rename, "[tid:%u]: Will have to block this cycle."
551 "%i insts available, but only %i insts can be "
552 "renamed due to ROB/IQ/LSQ limits.\n",
553 tid, insts_available, min_free_entries);
554
555 insts_available = min_free_entries;
556
557 blockThisCycle = true;
558
559 incrFullStat(source);
560 }
561
562 InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ?
563 skidBuffer[tid] : insts[tid];
564
565 DPRINTF(Rename, "[tid:%u]: %i available instructions to "
566 "send iew.\n", tid, insts_available);
567
568 DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts "
569 "dispatched to IQ last cycle.\n",
570 tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched);
571
572 // Handle serializing the next instruction if necessary.
573 if (serializeOnNextInst[tid]) {
574 if (emptyROB[tid] && instsInProgress[tid] == 0) {
575 // ROB already empty; no need to serialize.
576 serializeOnNextInst[tid] = false;
577 } else if (!insts_to_rename.empty()) {
578 insts_to_rename.front()->setSerializeBefore();
579 }
580 }
581
582 int renamed_insts = 0;
583
584 while (insts_available > 0 && toIEWIndex < renameWidth) {
585 DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid);
586
587 assert(!insts_to_rename.empty());
588
589 inst = insts_to_rename.front();
590
591 insts_to_rename.pop_front();
592
593 if (renameStatus[tid] == Unblocking) {
594 DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%#x from rename "
595 "skidBuffer\n",
596 tid, inst->seqNum, inst->readPC());
597 }
598
599 if (inst->isSquashed()) {
600 DPRINTF(Rename, "[tid:%u]: instruction %i with PC %#x is "
601 "squashed, skipping.\n",
602 tid, inst->seqNum, inst->readPC());
603
604 ++renameSquashedInsts;
605
606 // Decrement how many instructions are available.
607 --insts_available;
608
609 continue;
610 }
611
612 DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with "
613 "PC %#x.\n",
614 tid, inst->seqNum, inst->readPC());
615
616 // Handle serializeAfter/serializeBefore instructions.
617 // serializeAfter marks the next instruction as serializeBefore.
618 // serializeBefore makes the instruction wait in rename until the ROB
619 // is empty.
620
621 // In this model, IPR accesses are serialize before
622 // instructions, and store conditionals are serialize after
623 // instructions. This is mainly due to lack of support for
624 // out-of-order operations of either of those classes of
625 // instructions.
626 if ((inst->isIprAccess() || inst->isSerializeBefore()) &&
627 !inst->isSerializeHandled()) {
628 DPRINTF(Rename, "Serialize before instruction encountered.\n");
629
630 if (!inst->isTempSerializeBefore()) {
631 renamedSerializing++;
632 inst->setSerializeHandled();
633 } else {
634 renamedTempSerializing++;
635 }
636
637 // Change status over to SerializeStall so that other stages know
638 // what this is blocked on.
639 renameStatus[tid] = SerializeStall;
640
641 serializeInst[tid] = inst;
642
643 blockThisCycle = true;
644
645 break;
646 } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) &&
647 !inst->isSerializeHandled()) {
648 DPRINTF(Rename, "Serialize after instruction encountered.\n");
649
650 renamedSerializing++;
651
652 inst->setSerializeHandled();
653
654 serializeAfter(insts_to_rename, tid);
655 }
656
657 // Check here to make sure there are enough destination registers
658 // to rename to. Otherwise block.
659 if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) {
660 DPRINTF(Rename, "Blocking due to lack of free "
661 "physical registers to rename to.\n");
662 blockThisCycle = true;
663 insts_to_rename.push_front(inst);
664 ++renameFullRegistersEvents;
665
666 break;
667 }
668
669 renameSrcRegs(inst, inst->threadNumber);
670
671 renameDestRegs(inst, inst->threadNumber);
672
673 ++renamed_insts;
674
675 // Put instruction in rename queue.
676 toIEW->insts[toIEWIndex] = inst;
677 ++(toIEW->size);
678
679 // Increment which instruction we're on.
680 ++toIEWIndex;
681
682 // Decrement how many instructions are available.
683 --insts_available;
684 }
685
686 instsInProgress[tid] += renamed_insts;
687 renameRenamedInsts += renamed_insts;
688
689 // If we wrote to the time buffer, record this.
690 if (toIEWIndex) {
691 wroteToTimeBuffer = true;
692 }
693
694 // Check if there's any instructions left that haven't yet been renamed.
695 // If so then block.
696 if (insts_available) {
697 blockThisCycle = true;
698 }
699
700 if (blockThisCycle) {
701 block(tid);
702 toDecode->renameUnblock[tid] = false;
703 }
704}
705
706template<class Impl>
707void
708DefaultRename<Impl>::skidInsert(ThreadID tid)
709{
710 DynInstPtr inst = NULL;
711
712 while (!insts[tid].empty()) {
713 inst = insts[tid].front();
714
715 insts[tid].pop_front();
716
717 assert(tid == inst->threadNumber);
718
719 DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC:%#x into Rename "
720 "skidBuffer\n", tid, inst->seqNum, inst->readPC());
721
722 ++renameSkidInsts;
723
724 skidBuffer[tid].push_back(inst);
725 }
726
727 if (skidBuffer[tid].size() > skidBufferMax)
728 {
729 typename InstQueue::iterator it;
730 warn("Skidbuffer contents:\n");
731 for(it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++)
732 {
733 warn("[tid:%u]: %s [sn:%i].\n", tid,
734 (*it)->staticInst->disassemble(inst->readPC()),
735 (*it)->seqNum);
736 }
737 panic("Skidbuffer Exceeded Max Size");
738 }
739}
740
741template <class Impl>
742void
743DefaultRename<Impl>::sortInsts()
744{
745 int insts_from_decode = fromDecode->size;
746#ifdef DEBUG
747 for (ThreadID tid = 0; tid < numThreads; tid++)
748 assert(insts[tid].empty());
749#endif
750 for (int i = 0; i < insts_from_decode; ++i) {
751 DynInstPtr inst = fromDecode->insts[i];
752 insts[inst->threadNumber].push_back(inst);
753 }
754}
755
756template<class Impl>
757bool
758DefaultRename<Impl>::skidsEmpty()
759{
760 list<ThreadID>::iterator threads = activeThreads->begin();
761 list<ThreadID>::iterator end = activeThreads->end();
762
763 while (threads != end) {
764 ThreadID tid = *threads++;
765
766 if (!skidBuffer[tid].empty())
767 return false;
768 }
769
770 return true;
771}
772
773template<class Impl>
774void
775DefaultRename<Impl>::updateStatus()
776{
777 bool any_unblocking = false;
778
779 list<ThreadID>::iterator threads = activeThreads->begin();
780 list<ThreadID>::iterator end = activeThreads->end();
781
782 while (threads != end) {
783 ThreadID tid = *threads++;
784
785 if (renameStatus[tid] == Unblocking) {
786 any_unblocking = true;
787 break;
788 }
789 }
790
791 // Rename will have activity if it's unblocking.
792 if (any_unblocking) {
793 if (_status == Inactive) {
794 _status = Active;
795
796 DPRINTF(Activity, "Activating stage.\n");
797
798 cpu->activateStage(O3CPU::RenameIdx);
799 }
800 } else {
801 // If it's not unblocking, then rename will not have any internal
802 // activity. Switch it to inactive.
803 if (_status == Active) {
804 _status = Inactive;
805 DPRINTF(Activity, "Deactivating stage.\n");
806
807 cpu->deactivateStage(O3CPU::RenameIdx);
808 }
809 }
810}
811
812template <class Impl>
813bool
814DefaultRename<Impl>::block(ThreadID tid)
815{
816 DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid);
817
818 // Add the current inputs onto the skid buffer, so they can be
819 // reprocessed when this stage unblocks.
820 skidInsert(tid);
821
822 // Only signal backwards to block if the previous stages do not think
823 // rename is already blocked.
824 if (renameStatus[tid] != Blocked) {
825 // If resumeUnblocking is set, we unblocked during the squash,
826 // but now we're have unblocking status. We need to tell earlier
827 // stages to block.
828 if (resumeUnblocking || renameStatus[tid] != Unblocking) {
829 toDecode->renameBlock[tid] = true;
830 toDecode->renameUnblock[tid] = false;
831 wroteToTimeBuffer = true;
832 }
833
834 // Rename can not go from SerializeStall to Blocked, otherwise
835 // it would not know to complete the serialize stall.
836 if (renameStatus[tid] != SerializeStall) {
837 // Set status to Blocked.
838 renameStatus[tid] = Blocked;
839 return true;
840 }
841 }
842
843 return false;
844}
845
846template <class Impl>
847bool
848DefaultRename<Impl>::unblock(ThreadID tid)
849{
850 DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid);
851
852 // Rename is done unblocking if the skid buffer is empty.
853 if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) {
854
855 DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid);
856
857 toDecode->renameUnblock[tid] = true;
858 wroteToTimeBuffer = true;
859
860 renameStatus[tid] = Running;
861 return true;
862 }
863
864 return false;
865}
866
867template <class Impl>
868void
869DefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, ThreadID tid)
870{
871 typename std::list<RenameHistory>::iterator hb_it =
872 historyBuffer[tid].begin();
873
874 // After a syscall squashes everything, the history buffer may be empty
875 // but the ROB may still be squashing instructions.
876 if (historyBuffer[tid].empty()) {
877 return;
878 }
879
880 // Go through the most recent instructions, undoing the mappings
881 // they did and freeing up the registers.
882 while (!historyBuffer[tid].empty() &&
883 (*hb_it).instSeqNum > squashed_seq_num) {
884 assert(hb_it != historyBuffer[tid].end());
885
886 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
887 "number %i.\n", tid, (*hb_it).instSeqNum);
888
889 // Tell the rename map to set the architected register to the
890 // previous physical register that it was renamed to.
891 renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
892
893 // Put the renamed physical register back on the free list.
894 freeList->addReg(hb_it->newPhysReg);
895
896 // Be sure to mark its register as ready if it's a misc register.
897 if (hb_it->newPhysReg >= maxPhysicalRegs) {
898 scoreboard->setReg(hb_it->newPhysReg);
899 }
900
901 historyBuffer[tid].erase(hb_it++);
902
903 ++renameUndoneMaps;
904 }
905}
906
907template<class Impl>
908void
909DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid)
910{
911 DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the "
912 "history buffer %u (size=%i), until [sn:%lli].\n",
913 tid, tid, historyBuffer[tid].size(), inst_seq_num);
914
915 typename std::list<RenameHistory>::iterator hb_it =
916 historyBuffer[tid].end();
917
918 --hb_it;
919
920 if (historyBuffer[tid].empty()) {
921 DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid);
922 return;
923 } else if (hb_it->instSeqNum > inst_seq_num) {
924 DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure "
925 "that a syscall happened recently.\n", tid);
926 return;
927 }
928
929 // Commit all the renames up until (and including) the committed sequence
930 // number. Some or even all of the committed instructions may not have
931 // rename histories if they did not have destination registers that were
932 // renamed.
933 while (!historyBuffer[tid].empty() &&
934 hb_it != historyBuffer[tid].end() &&
935 (*hb_it).instSeqNum <= inst_seq_num) {
936
937 DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, "
938 "[sn:%lli].\n",
939 tid, (*hb_it).prevPhysReg, (*hb_it).instSeqNum);
940
941 freeList->addReg((*hb_it).prevPhysReg);
942 ++renameCommittedMaps;
943
944 historyBuffer[tid].erase(hb_it--);
945 }
946}
947
948template <class Impl>
949inline void
950DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid)
951{
952 assert(renameMap[tid] != 0);
953
954 unsigned num_src_regs = inst->numSrcRegs();
955
956 // Get the architectual register numbers from the source and
957 // destination operands, and redirect them to the right register.
958 // Will need to mark dependencies though.
959 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) {
960 RegIndex src_reg = inst->srcRegIdx(src_idx);
961 RegIndex flat_src_reg = src_reg;
962 if (src_reg < TheISA::FP_Base_DepTag) {
963 flat_src_reg = inst->tcBase()->flattenIntIndex(src_reg);
964 DPRINTF(Rename, "Flattening index %d to %d.\n", (int)src_reg, (int)flat_src_reg);
965 } else if (src_reg < TheISA::Ctrl_Base_DepTag) {
966 src_reg = src_reg - TheISA::FP_Base_DepTag;
967 flat_src_reg = inst->tcBase()->flattenFloatIndex(src_reg);
968 flat_src_reg += TheISA::NumIntRegs;
| 1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#include <list>
33
34#include "arch/isa_traits.hh"
35#include "arch/registers.hh"
36#include "config/full_system.hh"
37#include "config/the_isa.hh"
38#include "cpu/o3/rename.hh"
39#include "params/DerivO3CPU.hh"
40
41using namespace std;
42
43template <class Impl>
44DefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params)
45 : cpu(_cpu),
46 iewToRenameDelay(params->iewToRenameDelay),
47 decodeToRenameDelay(params->decodeToRenameDelay),
48 commitToRenameDelay(params->commitToRenameDelay),
49 renameWidth(params->renameWidth),
50 commitWidth(params->commitWidth),
51 resumeSerialize(false),
52 resumeUnblocking(false),
53 numThreads(params->numThreads),
54 maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs)
55{
56 _status = Inactive;
57
58 for (ThreadID tid = 0; tid < numThreads; tid++) {
59 renameStatus[tid] = Idle;
60
61 freeEntries[tid].iqEntries = 0;
62 freeEntries[tid].lsqEntries = 0;
63 freeEntries[tid].robEntries = 0;
64
65 stalls[tid].iew = false;
66 stalls[tid].commit = false;
67 serializeInst[tid] = NULL;
68
69 instsInProgress[tid] = 0;
70
71 emptyROB[tid] = true;
72
73 serializeOnNextInst[tid] = false;
74 }
75
76 // @todo: Make into a parameter.
77 skidBufferMax = (2 * (iewToRenameDelay * params->decodeWidth)) + renameWidth;
78}
79
80template <class Impl>
81std::string
82DefaultRename<Impl>::name() const
83{
84 return cpu->name() + ".rename";
85}
86
87template <class Impl>
88void
89DefaultRename<Impl>::regStats()
90{
91 renameSquashCycles
92 .name(name() + ".RENAME:SquashCycles")
93 .desc("Number of cycles rename is squashing")
94 .prereq(renameSquashCycles);
95 renameIdleCycles
96 .name(name() + ".RENAME:IdleCycles")
97 .desc("Number of cycles rename is idle")
98 .prereq(renameIdleCycles);
99 renameBlockCycles
100 .name(name() + ".RENAME:BlockCycles")
101 .desc("Number of cycles rename is blocking")
102 .prereq(renameBlockCycles);
103 renameSerializeStallCycles
104 .name(name() + ".RENAME:serializeStallCycles")
105 .desc("count of cycles rename stalled for serializing inst")
106 .flags(Stats::total);
107 renameRunCycles
108 .name(name() + ".RENAME:RunCycles")
109 .desc("Number of cycles rename is running")
110 .prereq(renameIdleCycles);
111 renameUnblockCycles
112 .name(name() + ".RENAME:UnblockCycles")
113 .desc("Number of cycles rename is unblocking")
114 .prereq(renameUnblockCycles);
115 renameRenamedInsts
116 .name(name() + ".RENAME:RenamedInsts")
117 .desc("Number of instructions processed by rename")
118 .prereq(renameRenamedInsts);
119 renameSquashedInsts
120 .name(name() + ".RENAME:SquashedInsts")
121 .desc("Number of squashed instructions processed by rename")
122 .prereq(renameSquashedInsts);
123 renameROBFullEvents
124 .name(name() + ".RENAME:ROBFullEvents")
125 .desc("Number of times rename has blocked due to ROB full")
126 .prereq(renameROBFullEvents);
127 renameIQFullEvents
128 .name(name() + ".RENAME:IQFullEvents")
129 .desc("Number of times rename has blocked due to IQ full")
130 .prereq(renameIQFullEvents);
131 renameLSQFullEvents
132 .name(name() + ".RENAME:LSQFullEvents")
133 .desc("Number of times rename has blocked due to LSQ full")
134 .prereq(renameLSQFullEvents);
135 renameFullRegistersEvents
136 .name(name() + ".RENAME:FullRegisterEvents")
137 .desc("Number of times there has been no free registers")
138 .prereq(renameFullRegistersEvents);
139 renameRenamedOperands
140 .name(name() + ".RENAME:RenamedOperands")
141 .desc("Number of destination operands rename has renamed")
142 .prereq(renameRenamedOperands);
143 renameRenameLookups
144 .name(name() + ".RENAME:RenameLookups")
145 .desc("Number of register rename lookups that rename has made")
146 .prereq(renameRenameLookups);
147 renameCommittedMaps
148 .name(name() + ".RENAME:CommittedMaps")
149 .desc("Number of HB maps that are committed")
150 .prereq(renameCommittedMaps);
151 renameUndoneMaps
152 .name(name() + ".RENAME:UndoneMaps")
153 .desc("Number of HB maps that are undone due to squashing")
154 .prereq(renameUndoneMaps);
155 renamedSerializing
156 .name(name() + ".RENAME:serializingInsts")
157 .desc("count of serializing insts renamed")
158 .flags(Stats::total)
159 ;
160 renamedTempSerializing
161 .name(name() + ".RENAME:tempSerializingInsts")
162 .desc("count of temporary serializing insts renamed")
163 .flags(Stats::total)
164 ;
165 renameSkidInsts
166 .name(name() + ".RENAME:skidInsts")
167 .desc("count of insts added to the skid buffer")
168 .flags(Stats::total)
169 ;
170}
171
172template <class Impl>
173void
174DefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
175{
176 timeBuffer = tb_ptr;
177
178 // Setup wire to read information from time buffer, from IEW stage.
179 fromIEW = timeBuffer->getWire(-iewToRenameDelay);
180
181 // Setup wire to read infromation from time buffer, from commit stage.
182 fromCommit = timeBuffer->getWire(-commitToRenameDelay);
183
184 // Setup wire to write information to previous stages.
185 toDecode = timeBuffer->getWire(0);
186}
187
188template <class Impl>
189void
190DefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
191{
192 renameQueue = rq_ptr;
193
194 // Setup wire to write information to future stages.
195 toIEW = renameQueue->getWire(0);
196}
197
198template <class Impl>
199void
200DefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
201{
202 decodeQueue = dq_ptr;
203
204 // Setup wire to get information from decode.
205 fromDecode = decodeQueue->getWire(-decodeToRenameDelay);
206}
207
208template <class Impl>
209void
210DefaultRename<Impl>::initStage()
211{
212 // Grab the number of free entries directly from the stages.
213 for (ThreadID tid = 0; tid < numThreads; tid++) {
214 freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid);
215 freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid);
216 freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid);
217 emptyROB[tid] = true;
218 }
219}
220
221template<class Impl>
222void
223DefaultRename<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
224{
225 activeThreads = at_ptr;
226}
227
228
229template <class Impl>
230void
231DefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[])
232{
233 for (ThreadID tid = 0; tid < numThreads; tid++)
234 renameMap[tid] = &rm_ptr[tid];
235}
236
237template <class Impl>
238void
239DefaultRename<Impl>::setFreeList(FreeList *fl_ptr)
240{
241 freeList = fl_ptr;
242}
243
244template<class Impl>
245void
246DefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard)
247{
248 scoreboard = _scoreboard;
249}
250
251template <class Impl>
252bool
253DefaultRename<Impl>::drain()
254{
255 // Rename is ready to switch out at any time.
256 cpu->signalDrained();
257 return true;
258}
259
260template <class Impl>
261void
262DefaultRename<Impl>::switchOut()
263{
264 // Clear any state, fix up the rename map.
265 for (ThreadID tid = 0; tid < numThreads; tid++) {
266 typename std::list<RenameHistory>::iterator hb_it =
267 historyBuffer[tid].begin();
268
269 while (!historyBuffer[tid].empty()) {
270 assert(hb_it != historyBuffer[tid].end());
271
272 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
273 "number %i.\n", tid, (*hb_it).instSeqNum);
274
275 // Tell the rename map to set the architected register to the
276 // previous physical register that it was renamed to.
277 renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
278
279 // Put the renamed physical register back on the free list.
280 freeList->addReg(hb_it->newPhysReg);
281
282 // Be sure to mark its register as ready if it's a misc register.
283 if (hb_it->newPhysReg >= maxPhysicalRegs) {
284 scoreboard->setReg(hb_it->newPhysReg);
285 }
286
287 historyBuffer[tid].erase(hb_it++);
288 }
289 insts[tid].clear();
290 skidBuffer[tid].clear();
291 }
292}
293
294template <class Impl>
295void
296DefaultRename<Impl>::takeOverFrom()
297{
298 _status = Inactive;
299 initStage();
300
301 // Reset all state prior to taking over from the other CPU.
302 for (ThreadID tid = 0; tid < numThreads; tid++) {
303 renameStatus[tid] = Idle;
304
305 stalls[tid].iew = false;
306 stalls[tid].commit = false;
307 serializeInst[tid] = NULL;
308
309 instsInProgress[tid] = 0;
310
311 emptyROB[tid] = true;
312
313 serializeOnNextInst[tid] = false;
314 }
315}
316
317template <class Impl>
318void
319DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, ThreadID tid)
320{
321 DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid);
322
323 // Clear the stall signal if rename was blocked or unblocking before.
324 // If it still needs to block, the blocking should happen the next
325 // cycle and there should be space to hold everything due to the squash.
326 if (renameStatus[tid] == Blocked ||
327 renameStatus[tid] == Unblocking) {
328 toDecode->renameUnblock[tid] = 1;
329
330 resumeSerialize = false;
331 serializeInst[tid] = NULL;
332 } else if (renameStatus[tid] == SerializeStall) {
333 if (serializeInst[tid]->seqNum <= squash_seq_num) {
334 DPRINTF(Rename, "Rename will resume serializing after squash\n");
335 resumeSerialize = true;
336 assert(serializeInst[tid]);
337 } else {
338 resumeSerialize = false;
339 toDecode->renameUnblock[tid] = 1;
340
341 serializeInst[tid] = NULL;
342 }
343 }
344
345 // Set the status to Squashing.
346 renameStatus[tid] = Squashing;
347
348 // Squash any instructions from decode.
349 unsigned squashCount = 0;
350
351 for (int i=0; i<fromDecode->size; i++) {
352 if (fromDecode->insts[i]->threadNumber == tid &&
353 fromDecode->insts[i]->seqNum > squash_seq_num) {
354 fromDecode->insts[i]->setSquashed();
355 wroteToTimeBuffer = true;
356 squashCount++;
357 }
358
359 }
360
361 // Clear the instruction list and skid buffer in case they have any
362 // insts in them.
363 insts[tid].clear();
364
365 // Clear the skid buffer in case it has any data in it.
366 skidBuffer[tid].clear();
367
368 doSquash(squash_seq_num, tid);
369}
370
371template <class Impl>
372void
373DefaultRename<Impl>::tick()
374{
375 wroteToTimeBuffer = false;
376
377 blockThisCycle = false;
378
379 bool status_change = false;
380
381 toIEWIndex = 0;
382
383 sortInsts();
384
385 list<ThreadID>::iterator threads = activeThreads->begin();
386 list<ThreadID>::iterator end = activeThreads->end();
387
388 // Check stall and squash signals.
389 while (threads != end) {
390 ThreadID tid = *threads++;
391
392 DPRINTF(Rename, "Processing [tid:%i]\n", tid);
393
394 status_change = checkSignalsAndUpdate(tid) || status_change;
395
396 rename(status_change, tid);
397 }
398
399 if (status_change) {
400 updateStatus();
401 }
402
403 if (wroteToTimeBuffer) {
404 DPRINTF(Activity, "Activity this cycle.\n");
405 cpu->activityThisCycle();
406 }
407
408 threads = activeThreads->begin();
409
410 while (threads != end) {
411 ThreadID tid = *threads++;
412
413 // If we committed this cycle then doneSeqNum will be > 0
414 if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
415 !fromCommit->commitInfo[tid].squash &&
416 renameStatus[tid] != Squashing) {
417
418 removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum,
419 tid);
420 }
421 }
422
423 // @todo: make into updateProgress function
424 for (ThreadID tid = 0; tid < numThreads; tid++) {
425 instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched;
426
427 assert(instsInProgress[tid] >=0);
428 }
429
430}
431
432template<class Impl>
433void
434DefaultRename<Impl>::rename(bool &status_change, ThreadID tid)
435{
436 // If status is Running or idle,
437 // call renameInsts()
438 // If status is Unblocking,
439 // buffer any instructions coming from decode
440 // continue trying to empty skid buffer
441 // check if stall conditions have passed
442
443 if (renameStatus[tid] == Blocked) {
444 ++renameBlockCycles;
445 } else if (renameStatus[tid] == Squashing) {
446 ++renameSquashCycles;
447 } else if (renameStatus[tid] == SerializeStall) {
448 ++renameSerializeStallCycles;
449 // If we are currently in SerializeStall and resumeSerialize
450 // was set, then that means that we are resuming serializing
451 // this cycle. Tell the previous stages to block.
452 if (resumeSerialize) {
453 resumeSerialize = false;
454 block(tid);
455 toDecode->renameUnblock[tid] = false;
456 }
457 } else if (renameStatus[tid] == Unblocking) {
458 if (resumeUnblocking) {
459 block(tid);
460 resumeUnblocking = false;
461 toDecode->renameUnblock[tid] = false;
462 }
463 }
464
465 if (renameStatus[tid] == Running ||
466 renameStatus[tid] == Idle) {
467 DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run "
468 "stage.\n", tid);
469
470 renameInsts(tid);
471 } else if (renameStatus[tid] == Unblocking) {
472 renameInsts(tid);
473
474 if (validInsts()) {
475 // Add the current inputs to the skid buffer so they can be
476 // reprocessed when this stage unblocks.
477 skidInsert(tid);
478 }
479
480 // If we switched over to blocking, then there's a potential for
481 // an overall status change.
482 status_change = unblock(tid) || status_change || blockThisCycle;
483 }
484}
485
486template <class Impl>
487void
488DefaultRename<Impl>::renameInsts(ThreadID tid)
489{
490 // Instructions can be either in the skid buffer or the queue of
491 // instructions coming from decode, depending on the status.
492 int insts_available = renameStatus[tid] == Unblocking ?
493 skidBuffer[tid].size() : insts[tid].size();
494
495 // Check the decode queue to see if instructions are available.
496 // If there are no available instructions to rename, then do nothing.
497 if (insts_available == 0) {
498 DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n",
499 tid);
500 // Should I change status to idle?
501 ++renameIdleCycles;
502 return;
503 } else if (renameStatus[tid] == Unblocking) {
504 ++renameUnblockCycles;
505 } else if (renameStatus[tid] == Running) {
506 ++renameRunCycles;
507 }
508
509 DynInstPtr inst;
510
511 // Will have to do a different calculation for the number of free
512 // entries.
513 int free_rob_entries = calcFreeROBEntries(tid);
514 int free_iq_entries = calcFreeIQEntries(tid);
515 int free_lsq_entries = calcFreeLSQEntries(tid);
516 int min_free_entries = free_rob_entries;
517
518 FullSource source = ROB;
519
520 if (free_iq_entries < min_free_entries) {
521 min_free_entries = free_iq_entries;
522 source = IQ;
523 }
524
525 if (free_lsq_entries < min_free_entries) {
526 min_free_entries = free_lsq_entries;
527 source = LSQ;
528 }
529
530 // Check if there's any space left.
531 if (min_free_entries <= 0) {
532 DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ "
533 "entries.\n"
534 "ROB has %i free entries.\n"
535 "IQ has %i free entries.\n"
536 "LSQ has %i free entries.\n",
537 tid,
538 free_rob_entries,
539 free_iq_entries,
540 free_lsq_entries);
541
542 blockThisCycle = true;
543
544 block(tid);
545
546 incrFullStat(source);
547
548 return;
549 } else if (min_free_entries < insts_available) {
550 DPRINTF(Rename, "[tid:%u]: Will have to block this cycle."
551 "%i insts available, but only %i insts can be "
552 "renamed due to ROB/IQ/LSQ limits.\n",
553 tid, insts_available, min_free_entries);
554
555 insts_available = min_free_entries;
556
557 blockThisCycle = true;
558
559 incrFullStat(source);
560 }
561
562 InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ?
563 skidBuffer[tid] : insts[tid];
564
565 DPRINTF(Rename, "[tid:%u]: %i available instructions to "
566 "send iew.\n", tid, insts_available);
567
568 DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts "
569 "dispatched to IQ last cycle.\n",
570 tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched);
571
572 // Handle serializing the next instruction if necessary.
573 if (serializeOnNextInst[tid]) {
574 if (emptyROB[tid] && instsInProgress[tid] == 0) {
575 // ROB already empty; no need to serialize.
576 serializeOnNextInst[tid] = false;
577 } else if (!insts_to_rename.empty()) {
578 insts_to_rename.front()->setSerializeBefore();
579 }
580 }
581
582 int renamed_insts = 0;
583
584 while (insts_available > 0 && toIEWIndex < renameWidth) {
585 DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid);
586
587 assert(!insts_to_rename.empty());
588
589 inst = insts_to_rename.front();
590
591 insts_to_rename.pop_front();
592
593 if (renameStatus[tid] == Unblocking) {
594 DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%#x from rename "
595 "skidBuffer\n",
596 tid, inst->seqNum, inst->readPC());
597 }
598
599 if (inst->isSquashed()) {
600 DPRINTF(Rename, "[tid:%u]: instruction %i with PC %#x is "
601 "squashed, skipping.\n",
602 tid, inst->seqNum, inst->readPC());
603
604 ++renameSquashedInsts;
605
606 // Decrement how many instructions are available.
607 --insts_available;
608
609 continue;
610 }
611
612 DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with "
613 "PC %#x.\n",
614 tid, inst->seqNum, inst->readPC());
615
616 // Handle serializeAfter/serializeBefore instructions.
617 // serializeAfter marks the next instruction as serializeBefore.
618 // serializeBefore makes the instruction wait in rename until the ROB
619 // is empty.
620
621 // In this model, IPR accesses are serialize before
622 // instructions, and store conditionals are serialize after
623 // instructions. This is mainly due to lack of support for
624 // out-of-order operations of either of those classes of
625 // instructions.
626 if ((inst->isIprAccess() || inst->isSerializeBefore()) &&
627 !inst->isSerializeHandled()) {
628 DPRINTF(Rename, "Serialize before instruction encountered.\n");
629
630 if (!inst->isTempSerializeBefore()) {
631 renamedSerializing++;
632 inst->setSerializeHandled();
633 } else {
634 renamedTempSerializing++;
635 }
636
637 // Change status over to SerializeStall so that other stages know
638 // what this is blocked on.
639 renameStatus[tid] = SerializeStall;
640
641 serializeInst[tid] = inst;
642
643 blockThisCycle = true;
644
645 break;
646 } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) &&
647 !inst->isSerializeHandled()) {
648 DPRINTF(Rename, "Serialize after instruction encountered.\n");
649
650 renamedSerializing++;
651
652 inst->setSerializeHandled();
653
654 serializeAfter(insts_to_rename, tid);
655 }
656
657 // Check here to make sure there are enough destination registers
658 // to rename to. Otherwise block.
659 if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) {
660 DPRINTF(Rename, "Blocking due to lack of free "
661 "physical registers to rename to.\n");
662 blockThisCycle = true;
663 insts_to_rename.push_front(inst);
664 ++renameFullRegistersEvents;
665
666 break;
667 }
668
669 renameSrcRegs(inst, inst->threadNumber);
670
671 renameDestRegs(inst, inst->threadNumber);
672
673 ++renamed_insts;
674
675 // Put instruction in rename queue.
676 toIEW->insts[toIEWIndex] = inst;
677 ++(toIEW->size);
678
679 // Increment which instruction we're on.
680 ++toIEWIndex;
681
682 // Decrement how many instructions are available.
683 --insts_available;
684 }
685
686 instsInProgress[tid] += renamed_insts;
687 renameRenamedInsts += renamed_insts;
688
689 // If we wrote to the time buffer, record this.
690 if (toIEWIndex) {
691 wroteToTimeBuffer = true;
692 }
693
694 // Check if there's any instructions left that haven't yet been renamed.
695 // If so then block.
696 if (insts_available) {
697 blockThisCycle = true;
698 }
699
700 if (blockThisCycle) {
701 block(tid);
702 toDecode->renameUnblock[tid] = false;
703 }
704}
705
706template<class Impl>
707void
708DefaultRename<Impl>::skidInsert(ThreadID tid)
709{
710 DynInstPtr inst = NULL;
711
712 while (!insts[tid].empty()) {
713 inst = insts[tid].front();
714
715 insts[tid].pop_front();
716
717 assert(tid == inst->threadNumber);
718
719 DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC:%#x into Rename "
720 "skidBuffer\n", tid, inst->seqNum, inst->readPC());
721
722 ++renameSkidInsts;
723
724 skidBuffer[tid].push_back(inst);
725 }
726
727 if (skidBuffer[tid].size() > skidBufferMax)
728 {
729 typename InstQueue::iterator it;
730 warn("Skidbuffer contents:\n");
731 for(it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++)
732 {
733 warn("[tid:%u]: %s [sn:%i].\n", tid,
734 (*it)->staticInst->disassemble(inst->readPC()),
735 (*it)->seqNum);
736 }
737 panic("Skidbuffer Exceeded Max Size");
738 }
739}
740
741template <class Impl>
742void
743DefaultRename<Impl>::sortInsts()
744{
745 int insts_from_decode = fromDecode->size;
746#ifdef DEBUG
747 for (ThreadID tid = 0; tid < numThreads; tid++)
748 assert(insts[tid].empty());
749#endif
750 for (int i = 0; i < insts_from_decode; ++i) {
751 DynInstPtr inst = fromDecode->insts[i];
752 insts[inst->threadNumber].push_back(inst);
753 }
754}
755
756template<class Impl>
757bool
758DefaultRename<Impl>::skidsEmpty()
759{
760 list<ThreadID>::iterator threads = activeThreads->begin();
761 list<ThreadID>::iterator end = activeThreads->end();
762
763 while (threads != end) {
764 ThreadID tid = *threads++;
765
766 if (!skidBuffer[tid].empty())
767 return false;
768 }
769
770 return true;
771}
772
773template<class Impl>
774void
775DefaultRename<Impl>::updateStatus()
776{
777 bool any_unblocking = false;
778
779 list<ThreadID>::iterator threads = activeThreads->begin();
780 list<ThreadID>::iterator end = activeThreads->end();
781
782 while (threads != end) {
783 ThreadID tid = *threads++;
784
785 if (renameStatus[tid] == Unblocking) {
786 any_unblocking = true;
787 break;
788 }
789 }
790
791 // Rename will have activity if it's unblocking.
792 if (any_unblocking) {
793 if (_status == Inactive) {
794 _status = Active;
795
796 DPRINTF(Activity, "Activating stage.\n");
797
798 cpu->activateStage(O3CPU::RenameIdx);
799 }
800 } else {
801 // If it's not unblocking, then rename will not have any internal
802 // activity. Switch it to inactive.
803 if (_status == Active) {
804 _status = Inactive;
805 DPRINTF(Activity, "Deactivating stage.\n");
806
807 cpu->deactivateStage(O3CPU::RenameIdx);
808 }
809 }
810}
811
812template <class Impl>
813bool
814DefaultRename<Impl>::block(ThreadID tid)
815{
816 DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid);
817
818 // Add the current inputs onto the skid buffer, so they can be
819 // reprocessed when this stage unblocks.
820 skidInsert(tid);
821
822 // Only signal backwards to block if the previous stages do not think
823 // rename is already blocked.
824 if (renameStatus[tid] != Blocked) {
825 // If resumeUnblocking is set, we unblocked during the squash,
826 // but now we're have unblocking status. We need to tell earlier
827 // stages to block.
828 if (resumeUnblocking || renameStatus[tid] != Unblocking) {
829 toDecode->renameBlock[tid] = true;
830 toDecode->renameUnblock[tid] = false;
831 wroteToTimeBuffer = true;
832 }
833
834 // Rename can not go from SerializeStall to Blocked, otherwise
835 // it would not know to complete the serialize stall.
836 if (renameStatus[tid] != SerializeStall) {
837 // Set status to Blocked.
838 renameStatus[tid] = Blocked;
839 return true;
840 }
841 }
842
843 return false;
844}
845
846template <class Impl>
847bool
848DefaultRename<Impl>::unblock(ThreadID tid)
849{
850 DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid);
851
852 // Rename is done unblocking if the skid buffer is empty.
853 if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) {
854
855 DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid);
856
857 toDecode->renameUnblock[tid] = true;
858 wroteToTimeBuffer = true;
859
860 renameStatus[tid] = Running;
861 return true;
862 }
863
864 return false;
865}
866
867template <class Impl>
868void
869DefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, ThreadID tid)
870{
871 typename std::list<RenameHistory>::iterator hb_it =
872 historyBuffer[tid].begin();
873
874 // After a syscall squashes everything, the history buffer may be empty
875 // but the ROB may still be squashing instructions.
876 if (historyBuffer[tid].empty()) {
877 return;
878 }
879
880 // Go through the most recent instructions, undoing the mappings
881 // they did and freeing up the registers.
882 while (!historyBuffer[tid].empty() &&
883 (*hb_it).instSeqNum > squashed_seq_num) {
884 assert(hb_it != historyBuffer[tid].end());
885
886 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
887 "number %i.\n", tid, (*hb_it).instSeqNum);
888
889 // Tell the rename map to set the architected register to the
890 // previous physical register that it was renamed to.
891 renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
892
893 // Put the renamed physical register back on the free list.
894 freeList->addReg(hb_it->newPhysReg);
895
896 // Be sure to mark its register as ready if it's a misc register.
897 if (hb_it->newPhysReg >= maxPhysicalRegs) {
898 scoreboard->setReg(hb_it->newPhysReg);
899 }
900
901 historyBuffer[tid].erase(hb_it++);
902
903 ++renameUndoneMaps;
904 }
905}
906
907template<class Impl>
908void
909DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid)
910{
911 DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the "
912 "history buffer %u (size=%i), until [sn:%lli].\n",
913 tid, tid, historyBuffer[tid].size(), inst_seq_num);
914
915 typename std::list<RenameHistory>::iterator hb_it =
916 historyBuffer[tid].end();
917
918 --hb_it;
919
920 if (historyBuffer[tid].empty()) {
921 DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid);
922 return;
923 } else if (hb_it->instSeqNum > inst_seq_num) {
924 DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure "
925 "that a syscall happened recently.\n", tid);
926 return;
927 }
928
929 // Commit all the renames up until (and including) the committed sequence
930 // number. Some or even all of the committed instructions may not have
931 // rename histories if they did not have destination registers that were
932 // renamed.
933 while (!historyBuffer[tid].empty() &&
934 hb_it != historyBuffer[tid].end() &&
935 (*hb_it).instSeqNum <= inst_seq_num) {
936
937 DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, "
938 "[sn:%lli].\n",
939 tid, (*hb_it).prevPhysReg, (*hb_it).instSeqNum);
940
941 freeList->addReg((*hb_it).prevPhysReg);
942 ++renameCommittedMaps;
943
944 historyBuffer[tid].erase(hb_it--);
945 }
946}
947
948template <class Impl>
949inline void
950DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid)
951{
952 assert(renameMap[tid] != 0);
953
954 unsigned num_src_regs = inst->numSrcRegs();
955
956 // Get the architectual register numbers from the source and
957 // destination operands, and redirect them to the right register.
958 // Will need to mark dependencies though.
959 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) {
960 RegIndex src_reg = inst->srcRegIdx(src_idx);
961 RegIndex flat_src_reg = src_reg;
962 if (src_reg < TheISA::FP_Base_DepTag) {
963 flat_src_reg = inst->tcBase()->flattenIntIndex(src_reg);
964 DPRINTF(Rename, "Flattening index %d to %d.\n", (int)src_reg, (int)flat_src_reg);
965 } else if (src_reg < TheISA::Ctrl_Base_DepTag) {
966 src_reg = src_reg - TheISA::FP_Base_DepTag;
967 flat_src_reg = inst->tcBase()->flattenFloatIndex(src_reg);
968 flat_src_reg += TheISA::NumIntRegs;
|
1020 }
1021
1022 inst->flattenDestReg(dest_idx, flat_dest_reg);
1023
1024 // Get the physical register that the destination will be
1025 // renamed to.
1026 rename_result = renameMap[tid]->rename(flat_dest_reg);
1027
1028 //Mark Scoreboard entry as not ready
1029 scoreboard->unsetReg(rename_result.first);
1030
1031 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical "
1032 "reg %i.\n", tid, (int)flat_dest_reg,
1033 (int)rename_result.first);
1034
1035 // Record the rename information so that a history can be kept.
1036 RenameHistory hb_entry(inst->seqNum, flat_dest_reg,
1037 rename_result.first,
1038 rename_result.second);
1039
1040 historyBuffer[tid].push_front(hb_entry);
1041
1042 DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer "
1043 "(size=%i), [sn:%lli].\n",tid,
1044 historyBuffer[tid].size(),
1045 (*historyBuffer[tid].begin()).instSeqNum);
1046
1047 // Tell the instruction to rename the appropriate destination
1048 // register (dest_idx) to the new physical register
1049 // (rename_result.first), and record the previous physical
1050 // register that the same logical register was renamed to
1051 // (rename_result.second).
1052 inst->renameDestReg(dest_idx,
1053 rename_result.first,
1054 rename_result.second);
1055
1056 ++renameRenamedOperands;
1057 }
1058}
1059
1060template <class Impl>
1061inline int
1062DefaultRename<Impl>::calcFreeROBEntries(ThreadID tid)
1063{
1064 int num_free = freeEntries[tid].robEntries -
1065 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1066
1067 //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free);
1068
1069 return num_free;
1070}
1071
1072template <class Impl>
1073inline int
1074DefaultRename<Impl>::calcFreeIQEntries(ThreadID tid)
1075{
1076 int num_free = freeEntries[tid].iqEntries -
1077 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1078
1079 //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free);
1080
1081 return num_free;
1082}
1083
1084template <class Impl>
1085inline int
1086DefaultRename<Impl>::calcFreeLSQEntries(ThreadID tid)
1087{
1088 int num_free = freeEntries[tid].lsqEntries -
1089 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ);
1090
1091 //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free);
1092
1093 return num_free;
1094}
1095
1096template <class Impl>
1097unsigned
1098DefaultRename<Impl>::validInsts()
1099{
1100 unsigned inst_count = 0;
1101
1102 for (int i=0; i<fromDecode->size; i++) {
1103 if (!fromDecode->insts[i]->isSquashed())
1104 inst_count++;
1105 }
1106
1107 return inst_count;
1108}
1109
1110template <class Impl>
1111void
1112DefaultRename<Impl>::readStallSignals(ThreadID tid)
1113{
1114 if (fromIEW->iewBlock[tid]) {
1115 stalls[tid].iew = true;
1116 }
1117
1118 if (fromIEW->iewUnblock[tid]) {
1119 assert(stalls[tid].iew);
1120 stalls[tid].iew = false;
1121 }
1122
1123 if (fromCommit->commitBlock[tid]) {
1124 stalls[tid].commit = true;
1125 }
1126
1127 if (fromCommit->commitUnblock[tid]) {
1128 assert(stalls[tid].commit);
1129 stalls[tid].commit = false;
1130 }
1131}
1132
1133template <class Impl>
1134bool
1135DefaultRename<Impl>::checkStall(ThreadID tid)
1136{
1137 bool ret_val = false;
1138
1139 if (stalls[tid].iew) {
1140 DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid);
1141 ret_val = true;
1142 } else if (stalls[tid].commit) {
1143 DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid);
1144 ret_val = true;
1145 } else if (calcFreeROBEntries(tid) <= 0) {
1146 DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid);
1147 ret_val = true;
1148 } else if (calcFreeIQEntries(tid) <= 0) {
1149 DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid);
1150 ret_val = true;
1151 } else if (calcFreeLSQEntries(tid) <= 0) {
1152 DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid);
1153 ret_val = true;
1154 } else if (renameMap[tid]->numFreeEntries() <= 0) {
1155 DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid);
1156 ret_val = true;
1157 } else if (renameStatus[tid] == SerializeStall &&
1158 (!emptyROB[tid] || instsInProgress[tid])) {
1159 DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not "
1160 "empty.\n",
1161 tid);
1162 ret_val = true;
1163 }
1164
1165 return ret_val;
1166}
1167
1168template <class Impl>
1169void
1170DefaultRename<Impl>::readFreeEntries(ThreadID tid)
1171{
1172 bool updated = false;
1173 if (fromIEW->iewInfo[tid].usedIQ) {
1174 freeEntries[tid].iqEntries =
1175 fromIEW->iewInfo[tid].freeIQEntries;
1176 updated = true;
1177 }
1178
1179 if (fromIEW->iewInfo[tid].usedLSQ) {
1180 freeEntries[tid].lsqEntries =
1181 fromIEW->iewInfo[tid].freeLSQEntries;
1182 updated = true;
1183 }
1184
1185 if (fromCommit->commitInfo[tid].usedROB) {
1186 freeEntries[tid].robEntries =
1187 fromCommit->commitInfo[tid].freeROBEntries;
1188 emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB;
1189 updated = true;
1190 }
1191
1192 DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n",
1193 tid,
1194 freeEntries[tid].iqEntries,
1195 freeEntries[tid].robEntries,
1196 freeEntries[tid].lsqEntries);
1197
1198 DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n",
1199 tid, instsInProgress[tid]);
1200}
1201
1202template <class Impl>
1203bool
1204DefaultRename<Impl>::checkSignalsAndUpdate(ThreadID tid)
1205{
1206 // Check if there's a squash signal, squash if there is
1207 // Check stall signals, block if necessary.
1208 // If status was blocked
1209 // check if stall conditions have passed
1210 // if so then go to unblocking
1211 // If status was Squashing
1212 // check if squashing is not high. Switch to running this cycle.
1213 // If status was serialize stall
1214 // check if ROB is empty and no insts are in flight to the ROB
1215
1216 readFreeEntries(tid);
1217 readStallSignals(tid);
1218
1219 if (fromCommit->commitInfo[tid].squash) {
1220 DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from "
1221 "commit.\n", tid);
1222
1223 squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
1224
1225 return true;
1226 }
1227
1228 if (fromCommit->commitInfo[tid].robSquashing) {
1229 DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid);
1230
1231 renameStatus[tid] = Squashing;
1232
1233 return true;
1234 }
1235
1236 if (checkStall(tid)) {
1237 return block(tid);
1238 }
1239
1240 if (renameStatus[tid] == Blocked) {
1241 DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n",
1242 tid);
1243
1244 renameStatus[tid] = Unblocking;
1245
1246 unblock(tid);
1247
1248 return true;
1249 }
1250
1251 if (renameStatus[tid] == Squashing) {
1252 // Switch status to running if rename isn't being told to block or
1253 // squash this cycle.
1254 if (resumeSerialize) {
1255 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n",
1256 tid);
1257
1258 renameStatus[tid] = SerializeStall;
1259 return true;
1260 } else if (resumeUnblocking) {
1261 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n",
1262 tid);
1263 renameStatus[tid] = Unblocking;
1264 return true;
1265 } else {
1266 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n",
1267 tid);
1268
1269 renameStatus[tid] = Running;
1270 return false;
1271 }
1272 }
1273
1274 if (renameStatus[tid] == SerializeStall) {
1275 // Stall ends once the ROB is free.
1276 DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to "
1277 "unblocking.\n", tid);
1278
1279 DynInstPtr serial_inst = serializeInst[tid];
1280
1281 renameStatus[tid] = Unblocking;
1282
1283 unblock(tid);
1284
1285 DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with "
1286 "PC %#x.\n",
1287 tid, serial_inst->seqNum, serial_inst->readPC());
1288
1289 // Put instruction into queue here.
1290 serial_inst->clearSerializeBefore();
1291
1292 if (!skidBuffer[tid].empty()) {
1293 skidBuffer[tid].push_front(serial_inst);
1294 } else {
1295 insts[tid].push_front(serial_inst);
1296 }
1297
1298 DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename."
1299 " Adding to front of list.\n", tid);
1300
1301 serializeInst[tid] = NULL;
1302
1303 return true;
1304 }
1305
1306 // If we've reached this point, we have not gotten any signals that
1307 // cause rename to change its status. Rename remains the same as before.
1308 return false;
1309}
1310
1311template<class Impl>
1312void
1313DefaultRename<Impl>::serializeAfter(InstQueue &inst_list, ThreadID tid)
1314{
1315 if (inst_list.empty()) {
1316 // Mark a bit to say that I must serialize on the next instruction.
1317 serializeOnNextInst[tid] = true;
1318 return;
1319 }
1320
1321 // Set the next instruction as serializing.
1322 inst_list.front()->setSerializeBefore();
1323}
1324
1325template <class Impl>
1326inline void
1327DefaultRename<Impl>::incrFullStat(const FullSource &source)
1328{
1329 switch (source) {
1330 case ROB:
1331 ++renameROBFullEvents;
1332 break;
1333 case IQ:
1334 ++renameIQFullEvents;
1335 break;
1336 case LSQ:
1337 ++renameLSQFullEvents;
1338 break;
1339 default:
1340 panic("Rename full stall stat should be incremented for a reason!");
1341 break;
1342 }
1343}
1344
1345template <class Impl>
1346void
1347DefaultRename<Impl>::dumpHistory()
1348{
1349 typename std::list<RenameHistory>::iterator buf_it;
1350
1351 for (ThreadID tid = 0; tid < numThreads; tid++) {
1352
1353 buf_it = historyBuffer[tid].begin();
1354
1355 while (buf_it != historyBuffer[tid].end()) {
1356 cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys "
1357 "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg,
1358 (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg);
1359
1360 buf_it++;
1361 }
1362 }
1363}
| 1024 }
1025
1026 inst->flattenDestReg(dest_idx, flat_dest_reg);
1027
1028 // Get the physical register that the destination will be
1029 // renamed to.
1030 rename_result = renameMap[tid]->rename(flat_dest_reg);
1031
1032 //Mark Scoreboard entry as not ready
1033 scoreboard->unsetReg(rename_result.first);
1034
1035 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical "
1036 "reg %i.\n", tid, (int)flat_dest_reg,
1037 (int)rename_result.first);
1038
1039 // Record the rename information so that a history can be kept.
1040 RenameHistory hb_entry(inst->seqNum, flat_dest_reg,
1041 rename_result.first,
1042 rename_result.second);
1043
1044 historyBuffer[tid].push_front(hb_entry);
1045
1046 DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer "
1047 "(size=%i), [sn:%lli].\n",tid,
1048 historyBuffer[tid].size(),
1049 (*historyBuffer[tid].begin()).instSeqNum);
1050
1051 // Tell the instruction to rename the appropriate destination
1052 // register (dest_idx) to the new physical register
1053 // (rename_result.first), and record the previous physical
1054 // register that the same logical register was renamed to
1055 // (rename_result.second).
1056 inst->renameDestReg(dest_idx,
1057 rename_result.first,
1058 rename_result.second);
1059
1060 ++renameRenamedOperands;
1061 }
1062}
1063
1064template <class Impl>
1065inline int
1066DefaultRename<Impl>::calcFreeROBEntries(ThreadID tid)
1067{
1068 int num_free = freeEntries[tid].robEntries -
1069 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1070
1071 //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free);
1072
1073 return num_free;
1074}
1075
1076template <class Impl>
1077inline int
1078DefaultRename<Impl>::calcFreeIQEntries(ThreadID tid)
1079{
1080 int num_free = freeEntries[tid].iqEntries -
1081 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1082
1083 //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free);
1084
1085 return num_free;
1086}
1087
1088template <class Impl>
1089inline int
1090DefaultRename<Impl>::calcFreeLSQEntries(ThreadID tid)
1091{
1092 int num_free = freeEntries[tid].lsqEntries -
1093 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ);
1094
1095 //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free);
1096
1097 return num_free;
1098}
1099
1100template <class Impl>
1101unsigned
1102DefaultRename<Impl>::validInsts()
1103{
1104 unsigned inst_count = 0;
1105
1106 for (int i=0; i<fromDecode->size; i++) {
1107 if (!fromDecode->insts[i]->isSquashed())
1108 inst_count++;
1109 }
1110
1111 return inst_count;
1112}
1113
1114template <class Impl>
1115void
1116DefaultRename<Impl>::readStallSignals(ThreadID tid)
1117{
1118 if (fromIEW->iewBlock[tid]) {
1119 stalls[tid].iew = true;
1120 }
1121
1122 if (fromIEW->iewUnblock[tid]) {
1123 assert(stalls[tid].iew);
1124 stalls[tid].iew = false;
1125 }
1126
1127 if (fromCommit->commitBlock[tid]) {
1128 stalls[tid].commit = true;
1129 }
1130
1131 if (fromCommit->commitUnblock[tid]) {
1132 assert(stalls[tid].commit);
1133 stalls[tid].commit = false;
1134 }
1135}
1136
1137template <class Impl>
1138bool
1139DefaultRename<Impl>::checkStall(ThreadID tid)
1140{
1141 bool ret_val = false;
1142
1143 if (stalls[tid].iew) {
1144 DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid);
1145 ret_val = true;
1146 } else if (stalls[tid].commit) {
1147 DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid);
1148 ret_val = true;
1149 } else if (calcFreeROBEntries(tid) <= 0) {
1150 DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid);
1151 ret_val = true;
1152 } else if (calcFreeIQEntries(tid) <= 0) {
1153 DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid);
1154 ret_val = true;
1155 } else if (calcFreeLSQEntries(tid) <= 0) {
1156 DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid);
1157 ret_val = true;
1158 } else if (renameMap[tid]->numFreeEntries() <= 0) {
1159 DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid);
1160 ret_val = true;
1161 } else if (renameStatus[tid] == SerializeStall &&
1162 (!emptyROB[tid] || instsInProgress[tid])) {
1163 DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not "
1164 "empty.\n",
1165 tid);
1166 ret_val = true;
1167 }
1168
1169 return ret_val;
1170}
1171
1172template <class Impl>
1173void
1174DefaultRename<Impl>::readFreeEntries(ThreadID tid)
1175{
1176 bool updated = false;
1177 if (fromIEW->iewInfo[tid].usedIQ) {
1178 freeEntries[tid].iqEntries =
1179 fromIEW->iewInfo[tid].freeIQEntries;
1180 updated = true;
1181 }
1182
1183 if (fromIEW->iewInfo[tid].usedLSQ) {
1184 freeEntries[tid].lsqEntries =
1185 fromIEW->iewInfo[tid].freeLSQEntries;
1186 updated = true;
1187 }
1188
1189 if (fromCommit->commitInfo[tid].usedROB) {
1190 freeEntries[tid].robEntries =
1191 fromCommit->commitInfo[tid].freeROBEntries;
1192 emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB;
1193 updated = true;
1194 }
1195
1196 DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n",
1197 tid,
1198 freeEntries[tid].iqEntries,
1199 freeEntries[tid].robEntries,
1200 freeEntries[tid].lsqEntries);
1201
1202 DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n",
1203 tid, instsInProgress[tid]);
1204}
1205
1206template <class Impl>
1207bool
1208DefaultRename<Impl>::checkSignalsAndUpdate(ThreadID tid)
1209{
1210 // Check if there's a squash signal, squash if there is
1211 // Check stall signals, block if necessary.
1212 // If status was blocked
1213 // check if stall conditions have passed
1214 // if so then go to unblocking
1215 // If status was Squashing
1216 // check if squashing is not high. Switch to running this cycle.
1217 // If status was serialize stall
1218 // check if ROB is empty and no insts are in flight to the ROB
1219
1220 readFreeEntries(tid);
1221 readStallSignals(tid);
1222
1223 if (fromCommit->commitInfo[tid].squash) {
1224 DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from "
1225 "commit.\n", tid);
1226
1227 squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
1228
1229 return true;
1230 }
1231
1232 if (fromCommit->commitInfo[tid].robSquashing) {
1233 DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid);
1234
1235 renameStatus[tid] = Squashing;
1236
1237 return true;
1238 }
1239
1240 if (checkStall(tid)) {
1241 return block(tid);
1242 }
1243
1244 if (renameStatus[tid] == Blocked) {
1245 DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n",
1246 tid);
1247
1248 renameStatus[tid] = Unblocking;
1249
1250 unblock(tid);
1251
1252 return true;
1253 }
1254
1255 if (renameStatus[tid] == Squashing) {
1256 // Switch status to running if rename isn't being told to block or
1257 // squash this cycle.
1258 if (resumeSerialize) {
1259 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n",
1260 tid);
1261
1262 renameStatus[tid] = SerializeStall;
1263 return true;
1264 } else if (resumeUnblocking) {
1265 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n",
1266 tid);
1267 renameStatus[tid] = Unblocking;
1268 return true;
1269 } else {
1270 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n",
1271 tid);
1272
1273 renameStatus[tid] = Running;
1274 return false;
1275 }
1276 }
1277
1278 if (renameStatus[tid] == SerializeStall) {
1279 // Stall ends once the ROB is free.
1280 DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to "
1281 "unblocking.\n", tid);
1282
1283 DynInstPtr serial_inst = serializeInst[tid];
1284
1285 renameStatus[tid] = Unblocking;
1286
1287 unblock(tid);
1288
1289 DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with "
1290 "PC %#x.\n",
1291 tid, serial_inst->seqNum, serial_inst->readPC());
1292
1293 // Put instruction into queue here.
1294 serial_inst->clearSerializeBefore();
1295
1296 if (!skidBuffer[tid].empty()) {
1297 skidBuffer[tid].push_front(serial_inst);
1298 } else {
1299 insts[tid].push_front(serial_inst);
1300 }
1301
1302 DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename."
1303 " Adding to front of list.\n", tid);
1304
1305 serializeInst[tid] = NULL;
1306
1307 return true;
1308 }
1309
1310 // If we've reached this point, we have not gotten any signals that
1311 // cause rename to change its status. Rename remains the same as before.
1312 return false;
1313}
1314
1315template<class Impl>
1316void
1317DefaultRename<Impl>::serializeAfter(InstQueue &inst_list, ThreadID tid)
1318{
1319 if (inst_list.empty()) {
1320 // Mark a bit to say that I must serialize on the next instruction.
1321 serializeOnNextInst[tid] = true;
1322 return;
1323 }
1324
1325 // Set the next instruction as serializing.
1326 inst_list.front()->setSerializeBefore();
1327}
1328
1329template <class Impl>
1330inline void
1331DefaultRename<Impl>::incrFullStat(const FullSource &source)
1332{
1333 switch (source) {
1334 case ROB:
1335 ++renameROBFullEvents;
1336 break;
1337 case IQ:
1338 ++renameIQFullEvents;
1339 break;
1340 case LSQ:
1341 ++renameLSQFullEvents;
1342 break;
1343 default:
1344 panic("Rename full stall stat should be incremented for a reason!");
1345 break;
1346 }
1347}
1348
1349template <class Impl>
1350void
1351DefaultRename<Impl>::dumpHistory()
1352{
1353 typename std::list<RenameHistory>::iterator buf_it;
1354
1355 for (ThreadID tid = 0; tid < numThreads; tid++) {
1356
1357 buf_it = historyBuffer[tid].begin();
1358
1359 while (buf_it != historyBuffer[tid].end()) {
1360 cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys "
1361 "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg,
1362 (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg);
1363
1364 buf_it++;
1365 }
1366 }
1367}
|