260 scoreboard = _scoreboard;
261}
262
263template <class Impl>
264bool
265DefaultRename<Impl>::drain()
266{
267 // Rename is ready to switch out at any time.
268 cpu->signalDrained();
269 return true;
270}
271
272template <class Impl>
273void
274DefaultRename<Impl>::switchOut()
275{
276 // Clear any state, fix up the rename map.
277 for (int i = 0; i < numThreads; i++) {
278 typename std::list<RenameHistory>::iterator hb_it =
279 historyBuffer[i].begin();
280
281 while (!historyBuffer[i].empty()) {
282 assert(hb_it != historyBuffer[i].end());
283
284 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
285 "number %i.\n", i, (*hb_it).instSeqNum);
286
287 // Tell the rename map to set the architected register to the
288 // previous physical register that it was renamed to.
289 renameMap[i]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
290
291 // Put the renamed physical register back on the free list.
292 freeList->addReg(hb_it->newPhysReg);
293
294 // Be sure to mark its register as ready if it's a misc register.
295 if (hb_it->newPhysReg >= maxPhysicalRegs) {
296 scoreboard->setReg(hb_it->newPhysReg);
297 }
298
299 historyBuffer[i].erase(hb_it++);
300 }
301 insts[i].clear();
302 skidBuffer[i].clear();
303 }
304}
305
306template <class Impl>
307void
308DefaultRename<Impl>::takeOverFrom()
309{
310 _status = Inactive;
311 initStage();
312
313 // Reset all state prior to taking over from the other CPU.
314 for (int i=0; i< numThreads; i++) {
315 renameStatus[i] = Idle;
316
317 stalls[i].iew = false;
318 stalls[i].commit = false;
319 serializeInst[i] = NULL;
320
321 instsInProgress[i] = 0;
322
323 emptyROB[i] = true;
324
325 serializeOnNextInst[i] = false;
326 }
327}
328
329template <class Impl>
330void
331DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, unsigned tid)
332{
333 DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid);
334
335 // Clear the stall signal if rename was blocked or unblocking before.
336 // If it still needs to block, the blocking should happen the next
337 // cycle and there should be space to hold everything due to the squash.
338 if (renameStatus[tid] == Blocked ||
339 renameStatus[tid] == Unblocking) {
340 toDecode->renameUnblock[tid] = 1;
341
342 resumeSerialize = false;
343 serializeInst[tid] = NULL;
344 } else if (renameStatus[tid] == SerializeStall) {
345 if (serializeInst[tid]->seqNum <= squash_seq_num) {
346 DPRINTF(Rename, "Rename will resume serializing after squash\n");
347 resumeSerialize = true;
348 assert(serializeInst[tid]);
349 } else {
350 resumeSerialize = false;
351 toDecode->renameUnblock[tid] = 1;
352
353 serializeInst[tid] = NULL;
354 }
355 }
356
357 // Set the status to Squashing.
358 renameStatus[tid] = Squashing;
359
360 // Squash any instructions from decode.
361 unsigned squashCount = 0;
362
363 for (int i=0; i<fromDecode->size; i++) {
364 if (fromDecode->insts[i]->threadNumber == tid &&
365 fromDecode->insts[i]->seqNum > squash_seq_num) {
366 fromDecode->insts[i]->setSquashed();
367 wroteToTimeBuffer = true;
368 squashCount++;
369 }
370
371 }
372
373 // Clear the instruction list and skid buffer in case they have any
374 // insts in them. Since we support multiple ISAs, we cant just:
375 // "insts[tid].clear();" or "skidBuffer[tid].clear()" since there is
376 // a possible delay slot inst for different architectures
377 // insts[tid].clear();
378#if ISA_HAS_DELAY_SLOT
379 DPRINTF(Rename, "[tid:%i] Squashing incoming decode instructions until "
380 "[sn:%i].\n",tid, squash_seq_num);
381 ListIt ilist_it = insts[tid].begin();
382 while (ilist_it != insts[tid].end()) {
383 if ((*ilist_it)->seqNum > squash_seq_num) {
384 (*ilist_it)->setSquashed();
385 DPRINTF(Rename, "Squashing incoming decode instruction, "
386 "[tid:%i] [sn:%i] PC %08p.\n", tid, (*ilist_it)->seqNum, (*ilist_it)->PC);
387 }
388 ilist_it++;
389 }
390#else
391 insts[tid].clear();
392#endif
393
394 // Clear the skid buffer in case it has any data in it.
395 // See comments above.
396 // skidBuffer[tid].clear();
397#if ISA_HAS_DELAY_SLOT
398 DPRINTF(Rename, "[tid:%i] Squashing incoming skidbuffer instructions "
399 "until [sn:%i].\n", tid, squash_seq_num);
400 ListIt slist_it = skidBuffer[tid].begin();
401 while (slist_it != skidBuffer[tid].end()) {
402 if ((*slist_it)->seqNum > squash_seq_num) {
403 (*slist_it)->setSquashed();
404 DPRINTF(Rename, "Squashing skidbuffer instruction, [tid:%i] [sn:%i]"
405 "PC %08p.\n", tid, (*slist_it)->seqNum, (*slist_it)->PC);
406 }
407 slist_it++;
408 }
409 resumeUnblocking = (skidBuffer[tid].size() != 0);
410 DPRINTF(Rename, "Resume unblocking set to %s\n",
411 resumeUnblocking ? "true" : "false");
412#else
413 skidBuffer[tid].clear();
414#endif
415 doSquash(squash_seq_num, tid);
416}
417
418template <class Impl>
419void
420DefaultRename<Impl>::tick()
421{
422 wroteToTimeBuffer = false;
423
424 blockThisCycle = false;
425
426 bool status_change = false;
427
428 toIEWIndex = 0;
429
430 sortInsts();
431
432 std::list<unsigned>::iterator threads = activeThreads->begin();
433 std::list<unsigned>::iterator end = activeThreads->end();
434
435 // Check stall and squash signals.
436 while (threads != end) {
437 unsigned tid = *threads++;
438
439 DPRINTF(Rename, "Processing [tid:%i]\n", tid);
440
441 status_change = checkSignalsAndUpdate(tid) || status_change;
442
443 rename(status_change, tid);
444 }
445
446 if (status_change) {
447 updateStatus();
448 }
449
450 if (wroteToTimeBuffer) {
451 DPRINTF(Activity, "Activity this cycle.\n");
452 cpu->activityThisCycle();
453 }
454
455 threads = activeThreads->begin();
456
457 while (threads != end) {
458 unsigned tid = *threads++;
459
460 // If we committed this cycle then doneSeqNum will be > 0
461 if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
462 !fromCommit->commitInfo[tid].squash &&
463 renameStatus[tid] != Squashing) {
464
465 removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum,
466 tid);
467 }
468 }
469
470 // @todo: make into updateProgress function
471 for (int tid=0; tid < numThreads; tid++) {
472 instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched;
473
474 assert(instsInProgress[tid] >=0);
475 }
476
477}
478
479template<class Impl>
480void
481DefaultRename<Impl>::rename(bool &status_change, unsigned tid)
482{
483 // If status is Running or idle,
484 // call renameInsts()
485 // If status is Unblocking,
486 // buffer any instructions coming from decode
487 // continue trying to empty skid buffer
488 // check if stall conditions have passed
489
490 if (renameStatus[tid] == Blocked) {
491 ++renameBlockCycles;
492 } else if (renameStatus[tid] == Squashing) {
493 ++renameSquashCycles;
494 } else if (renameStatus[tid] == SerializeStall) {
495 ++renameSerializeStallCycles;
496 // If we are currently in SerializeStall and resumeSerialize
497 // was set, then that means that we are resuming serializing
498 // this cycle. Tell the previous stages to block.
499 if (resumeSerialize) {
500 resumeSerialize = false;
501 block(tid);
502 toDecode->renameUnblock[tid] = false;
503 }
504 } else if (renameStatus[tid] == Unblocking) {
505 if (resumeUnblocking) {
506 block(tid);
507 resumeUnblocking = false;
508 toDecode->renameUnblock[tid] = false;
509 }
510 }
511
512 if (renameStatus[tid] == Running ||
513 renameStatus[tid] == Idle) {
514 DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run "
515 "stage.\n", tid);
516
517 renameInsts(tid);
518 } else if (renameStatus[tid] == Unblocking) {
519 renameInsts(tid);
520
521 if (validInsts()) {
522 // Add the current inputs to the skid buffer so they can be
523 // reprocessed when this stage unblocks.
524 skidInsert(tid);
525 }
526
527 // If we switched over to blocking, then there's a potential for
528 // an overall status change.
529 status_change = unblock(tid) || status_change || blockThisCycle;
530 }
531}
532
533template <class Impl>
534void
535DefaultRename<Impl>::renameInsts(unsigned tid)
536{
537 // Instructions can be either in the skid buffer or the queue of
538 // instructions coming from decode, depending on the status.
539 int insts_available = renameStatus[tid] == Unblocking ?
540 skidBuffer[tid].size() : insts[tid].size();
541
542 // Check the decode queue to see if instructions are available.
543 // If there are no available instructions to rename, then do nothing.
544 if (insts_available == 0) {
545 DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n",
546 tid);
547 // Should I change status to idle?
548 ++renameIdleCycles;
549 return;
550 } else if (renameStatus[tid] == Unblocking) {
551 ++renameUnblockCycles;
552 } else if (renameStatus[tid] == Running) {
553 ++renameRunCycles;
554 }
555
556 DynInstPtr inst;
557
558 // Will have to do a different calculation for the number of free
559 // entries.
560 int free_rob_entries = calcFreeROBEntries(tid);
561 int free_iq_entries = calcFreeIQEntries(tid);
562 int free_lsq_entries = calcFreeLSQEntries(tid);
563 int min_free_entries = free_rob_entries;
564
565 FullSource source = ROB;
566
567 if (free_iq_entries < min_free_entries) {
568 min_free_entries = free_iq_entries;
569 source = IQ;
570 }
571
572 if (free_lsq_entries < min_free_entries) {
573 min_free_entries = free_lsq_entries;
574 source = LSQ;
575 }
576
577 // Check if there's any space left.
578 if (min_free_entries <= 0) {
579 DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ "
580 "entries.\n"
581 "ROB has %i free entries.\n"
582 "IQ has %i free entries.\n"
583 "LSQ has %i free entries.\n",
584 tid,
585 free_rob_entries,
586 free_iq_entries,
587 free_lsq_entries);
588
589 blockThisCycle = true;
590
591 block(tid);
592
593 incrFullStat(source);
594
595 return;
596 } else if (min_free_entries < insts_available) {
597 DPRINTF(Rename, "[tid:%u]: Will have to block this cycle."
598 "%i insts available, but only %i insts can be "
599 "renamed due to ROB/IQ/LSQ limits.\n",
600 tid, insts_available, min_free_entries);
601
602 insts_available = min_free_entries;
603
604 blockThisCycle = true;
605
606 incrFullStat(source);
607 }
608
609 InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ?
610 skidBuffer[tid] : insts[tid];
611
612 DPRINTF(Rename, "[tid:%u]: %i available instructions to "
613 "send iew.\n", tid, insts_available);
614
615 DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts "
616 "dispatched to IQ last cycle.\n",
617 tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched);
618
619 // Handle serializing the next instruction if necessary.
620 if (serializeOnNextInst[tid]) {
621 if (emptyROB[tid] && instsInProgress[tid] == 0) {
622 // ROB already empty; no need to serialize.
623 serializeOnNextInst[tid] = false;
624 } else if (!insts_to_rename.empty()) {
625 insts_to_rename.front()->setSerializeBefore();
626 }
627 }
628
629 int renamed_insts = 0;
630
631 while (insts_available > 0 && toIEWIndex < renameWidth) {
632 DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid);
633
634 assert(!insts_to_rename.empty());
635
636 inst = insts_to_rename.front();
637
638 insts_to_rename.pop_front();
639
640 if (renameStatus[tid] == Unblocking) {
641 DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%#x from rename "
642 "skidBuffer\n",
643 tid, inst->seqNum, inst->readPC());
644 }
645
646 if (inst->isSquashed()) {
647 DPRINTF(Rename, "[tid:%u]: instruction %i with PC %#x is "
648 "squashed, skipping.\n",
649 tid, inst->seqNum, inst->readPC());
650
651 ++renameSquashedInsts;
652
653 // Decrement how many instructions are available.
654 --insts_available;
655
656 continue;
657 }
658
659 DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with "
660 "PC %#x.\n",
661 tid, inst->seqNum, inst->readPC());
662
663 // Handle serializeAfter/serializeBefore instructions.
664 // serializeAfter marks the next instruction as serializeBefore.
665 // serializeBefore makes the instruction wait in rename until the ROB
666 // is empty.
667
668 // In this model, IPR accesses are serialize before
669 // instructions, and store conditionals are serialize after
670 // instructions. This is mainly due to lack of support for
671 // out-of-order operations of either of those classes of
672 // instructions.
673 if ((inst->isIprAccess() || inst->isSerializeBefore()) &&
674 !inst->isSerializeHandled()) {
675 DPRINTF(Rename, "Serialize before instruction encountered.\n");
676
677 if (!inst->isTempSerializeBefore()) {
678 renamedSerializing++;
679 inst->setSerializeHandled();
680 } else {
681 renamedTempSerializing++;
682 }
683
684 // Change status over to SerializeStall so that other stages know
685 // what this is blocked on.
686 renameStatus[tid] = SerializeStall;
687
688 serializeInst[tid] = inst;
689
690 blockThisCycle = true;
691
692 break;
693 } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) &&
694 !inst->isSerializeHandled()) {
695 DPRINTF(Rename, "Serialize after instruction encountered.\n");
696
697 renamedSerializing++;
698
699 inst->setSerializeHandled();
700
701 serializeAfter(insts_to_rename, tid);
702 }
703
704 // Check here to make sure there are enough destination registers
705 // to rename to. Otherwise block.
706 if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) {
707 DPRINTF(Rename, "Blocking due to lack of free "
708 "physical registers to rename to.\n");
709 blockThisCycle = true;
710
711 ++renameFullRegistersEvents;
712
713 break;
714 }
715
716 renameSrcRegs(inst, inst->threadNumber);
717
718 renameDestRegs(inst, inst->threadNumber);
719
720 ++renamed_insts;
721
722 // Put instruction in rename queue.
723 toIEW->insts[toIEWIndex] = inst;
724 ++(toIEW->size);
725
726 // Increment which instruction we're on.
727 ++toIEWIndex;
728
729 // Decrement how many instructions are available.
730 --insts_available;
731 }
732
733 instsInProgress[tid] += renamed_insts;
734 renameRenamedInsts += renamed_insts;
735
736 // If we wrote to the time buffer, record this.
737 if (toIEWIndex) {
738 wroteToTimeBuffer = true;
739 }
740
741 // Check if there's any instructions left that haven't yet been renamed.
742 // If so then block.
743 if (insts_available) {
744 blockThisCycle = true;
745 }
746
747 if (blockThisCycle) {
748 block(tid);
749 toDecode->renameUnblock[tid] = false;
750 }
751}
752
753template<class Impl>
754void
755DefaultRename<Impl>::skidInsert(unsigned tid)
756{
757 DynInstPtr inst = NULL;
758
759 while (!insts[tid].empty()) {
760 inst = insts[tid].front();
761
762 insts[tid].pop_front();
763
764 assert(tid == inst->threadNumber);
765
766 DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC:%#x into Rename "
767 "skidBuffer\n", tid, inst->seqNum, inst->readPC());
768
769 ++renameSkidInsts;
770
771 skidBuffer[tid].push_back(inst);
772 }
773
774 if (skidBuffer[tid].size() > skidBufferMax)
775 {
776 typename InstQueue::iterator it;
777 warn("Skidbuffer contents:\n");
778 for(it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++)
779 {
780 warn("[tid:%u]: %s [sn:%i].\n", tid,
781 (*it)->staticInst->disassemble(inst->readPC()),
782 (*it)->seqNum);
783 }
784 panic("Skidbuffer Exceeded Max Size");
785 }
786}
787
788template <class Impl>
789void
790DefaultRename<Impl>::sortInsts()
791{
792 int insts_from_decode = fromDecode->size;
793#ifdef DEBUG
794#if !ISA_HAS_DELAY_SLOT
795 for (int i=0; i < numThreads; i++)
796 assert(insts[i].empty());
797#endif
798#endif
799 for (int i = 0; i < insts_from_decode; ++i) {
800 DynInstPtr inst = fromDecode->insts[i];
801 insts[inst->threadNumber].push_back(inst);
802 }
803}
804
805template<class Impl>
806bool
807DefaultRename<Impl>::skidsEmpty()
808{
809 std::list<unsigned>::iterator threads = activeThreads->begin();
810 std::list<unsigned>::iterator end = activeThreads->end();
811
812 while (threads != end) {
813 unsigned tid = *threads++;
814
815 if (!skidBuffer[tid].empty())
816 return false;
817 }
818
819 return true;
820}
821
822template<class Impl>
823void
824DefaultRename<Impl>::updateStatus()
825{
826 bool any_unblocking = false;
827
828 std::list<unsigned>::iterator threads = activeThreads->begin();
829 std::list<unsigned>::iterator end = activeThreads->end();
830
831 while (threads != end) {
832 unsigned tid = *threads++;
833
834 if (renameStatus[tid] == Unblocking) {
835 any_unblocking = true;
836 break;
837 }
838 }
839
840 // Rename will have activity if it's unblocking.
841 if (any_unblocking) {
842 if (_status == Inactive) {
843 _status = Active;
844
845 DPRINTF(Activity, "Activating stage.\n");
846
847 cpu->activateStage(O3CPU::RenameIdx);
848 }
849 } else {
850 // If it's not unblocking, then rename will not have any internal
851 // activity. Switch it to inactive.
852 if (_status == Active) {
853 _status = Inactive;
854 DPRINTF(Activity, "Deactivating stage.\n");
855
856 cpu->deactivateStage(O3CPU::RenameIdx);
857 }
858 }
859}
860
861template <class Impl>
862bool
863DefaultRename<Impl>::block(unsigned tid)
864{
865 DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid);
866
867 // Add the current inputs onto the skid buffer, so they can be
868 // reprocessed when this stage unblocks.
869 skidInsert(tid);
870
871 // Only signal backwards to block if the previous stages do not think
872 // rename is already blocked.
873 if (renameStatus[tid] != Blocked) {
874 // If resumeUnblocking is set, we unblocked during the squash,
875 // but now we're have unblocking status. We need to tell earlier
876 // stages to block.
877 if (resumeUnblocking || renameStatus[tid] != Unblocking) {
878 toDecode->renameBlock[tid] = true;
879 toDecode->renameUnblock[tid] = false;
880 wroteToTimeBuffer = true;
881 }
882
883 // Rename can not go from SerializeStall to Blocked, otherwise
884 // it would not know to complete the serialize stall.
885 if (renameStatus[tid] != SerializeStall) {
886 // Set status to Blocked.
887 renameStatus[tid] = Blocked;
888 return true;
889 }
890 }
891
892 return false;
893}
894
895template <class Impl>
896bool
897DefaultRename<Impl>::unblock(unsigned tid)
898{
899 DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid);
900
901 // Rename is done unblocking if the skid buffer is empty.
902 if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) {
903
904 DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid);
905
906 toDecode->renameUnblock[tid] = true;
907 wroteToTimeBuffer = true;
908
909 renameStatus[tid] = Running;
910 return true;
911 }
912
913 return false;
914}
915
916template <class Impl>
917void
918DefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, unsigned tid)
919{
920 typename std::list<RenameHistory>::iterator hb_it =
921 historyBuffer[tid].begin();
922
923 // After a syscall squashes everything, the history buffer may be empty
924 // but the ROB may still be squashing instructions.
925 if (historyBuffer[tid].empty()) {
926 return;
927 }
928
929 // Go through the most recent instructions, undoing the mappings
930 // they did and freeing up the registers.
931 while (!historyBuffer[tid].empty() &&
932 (*hb_it).instSeqNum > squashed_seq_num) {
933 assert(hb_it != historyBuffer[tid].end());
934
935 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
936 "number %i.\n", tid, (*hb_it).instSeqNum);
937
938 // Tell the rename map to set the architected register to the
939 // previous physical register that it was renamed to.
940 renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
941
942 // Put the renamed physical register back on the free list.
943 freeList->addReg(hb_it->newPhysReg);
944
945 // Be sure to mark its register as ready if it's a misc register.
946 if (hb_it->newPhysReg >= maxPhysicalRegs) {
947 scoreboard->setReg(hb_it->newPhysReg);
948 }
949
950 historyBuffer[tid].erase(hb_it++);
951
952 ++renameUndoneMaps;
953 }
954}
955
956template<class Impl>
957void
958DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, unsigned tid)
959{
960 DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the "
961 "history buffer %u (size=%i), until [sn:%lli].\n",
962 tid, tid, historyBuffer[tid].size(), inst_seq_num);
963
964 typename std::list<RenameHistory>::iterator hb_it =
965 historyBuffer[tid].end();
966
967 --hb_it;
968
969 if (historyBuffer[tid].empty()) {
970 DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid);
971 return;
972 } else if (hb_it->instSeqNum > inst_seq_num) {
973 DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure "
974 "that a syscall happened recently.\n", tid);
975 return;
976 }
977
978 // Commit all the renames up until (and including) the committed sequence
979 // number. Some or even all of the committed instructions may not have
980 // rename histories if they did not have destination registers that were
981 // renamed.
982 while (!historyBuffer[tid].empty() &&
983 hb_it != historyBuffer[tid].end() &&
984 (*hb_it).instSeqNum <= inst_seq_num) {
985
986 DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, "
987 "[sn:%lli].\n",
988 tid, (*hb_it).prevPhysReg, (*hb_it).instSeqNum);
989
990 freeList->addReg((*hb_it).prevPhysReg);
991 ++renameCommittedMaps;
992
993 historyBuffer[tid].erase(hb_it--);
994 }
995}
996
997template <class Impl>
998inline void
999DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst,unsigned tid)
1000{
1001 assert(renameMap[tid] != 0);
1002
1003 unsigned num_src_regs = inst->numSrcRegs();
1004
1005 // Get the architectual register numbers from the source and
1006 // destination operands, and redirect them to the right register.
1007 // Will need to mark dependencies though.
1008 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) {
1009 RegIndex src_reg = inst->srcRegIdx(src_idx);
1010 RegIndex flat_src_reg = src_reg;
1011 if (src_reg < TheISA::FP_Base_DepTag) {
1012 flat_src_reg = TheISA::flattenIntIndex(inst->tcBase(), src_reg);
1013 DPRINTF(Rename, "Flattening index %d to %d.\n", (int)src_reg, (int)flat_src_reg);
1014 }
1015 inst->flattenSrcReg(src_idx, flat_src_reg);
1016
1017 // Look up the source registers to get the phys. register they've
1018 // been renamed to, and set the sources to those registers.
1019 PhysRegIndex renamed_reg = renameMap[tid]->lookup(flat_src_reg);
1020
1021 DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got "
1022 "physical reg %i.\n", tid, (int)flat_src_reg,
1023 (int)renamed_reg);
1024
1025 inst->renameSrcReg(src_idx, renamed_reg);
1026
1027 // See if the register is ready or not.
1028 if (scoreboard->getReg(renamed_reg) == true) {
1029 DPRINTF(Rename, "[tid:%u]: Register is ready.\n", tid);
1030
1031 inst->markSrcRegReady(src_idx);
1032 }
1033
1034 ++renameRenameLookups;
1035 }
1036}
1037
1038template <class Impl>
1039inline void
1040DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst,unsigned tid)
1041{
1042 typename RenameMap::RenameInfo rename_result;
1043
1044 unsigned num_dest_regs = inst->numDestRegs();
1045
1046 // Rename the destination registers.
1047 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) {
1048 RegIndex dest_reg = inst->destRegIdx(dest_idx);
1049 RegIndex flat_dest_reg = dest_reg;
1050 if (dest_reg < TheISA::FP_Base_DepTag) {
1051 flat_dest_reg = TheISA::flattenIntIndex(inst->tcBase(), dest_reg);
1052 DPRINTF(Rename, "Flattening index %d to %d.\n", (int)dest_reg, (int)flat_dest_reg);
1053 }
1054
1055 inst->flattenDestReg(dest_idx, flat_dest_reg);
1056
1057 // Get the physical register that the destination will be
1058 // renamed to.
1059 rename_result = renameMap[tid]->rename(flat_dest_reg);
1060
1061 //Mark Scoreboard entry as not ready
1062 scoreboard->unsetReg(rename_result.first);
1063
1064 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical "
1065 "reg %i.\n", tid, (int)flat_dest_reg,
1066 (int)rename_result.first);
1067
1068 // Record the rename information so that a history can be kept.
1069 RenameHistory hb_entry(inst->seqNum, flat_dest_reg,
1070 rename_result.first,
1071 rename_result.second);
1072
1073 historyBuffer[tid].push_front(hb_entry);
1074
1075 DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer "
1076 "(size=%i), [sn:%lli].\n",tid,
1077 historyBuffer[tid].size(),
1078 (*historyBuffer[tid].begin()).instSeqNum);
1079
1080 // Tell the instruction to rename the appropriate destination
1081 // register (dest_idx) to the new physical register
1082 // (rename_result.first), and record the previous physical
1083 // register that the same logical register was renamed to
1084 // (rename_result.second).
1085 inst->renameDestReg(dest_idx,
1086 rename_result.first,
1087 rename_result.second);
1088
1089 ++renameRenamedOperands;
1090 }
1091}
1092
1093template <class Impl>
1094inline int
1095DefaultRename<Impl>::calcFreeROBEntries(unsigned tid)
1096{
1097 int num_free = freeEntries[tid].robEntries -
1098 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1099
1100 //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free);
1101
1102 return num_free;
1103}
1104
1105template <class Impl>
1106inline int
1107DefaultRename<Impl>::calcFreeIQEntries(unsigned tid)
1108{
1109 int num_free = freeEntries[tid].iqEntries -
1110 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1111
1112 //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free);
1113
1114 return num_free;
1115}
1116
1117template <class Impl>
1118inline int
1119DefaultRename<Impl>::calcFreeLSQEntries(unsigned tid)
1120{
1121 int num_free = freeEntries[tid].lsqEntries -
1122 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ);
1123
1124 //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free);
1125
1126 return num_free;
1127}
1128
1129template <class Impl>
1130unsigned
1131DefaultRename<Impl>::validInsts()
1132{
1133 unsigned inst_count = 0;
1134
1135 for (int i=0; i<fromDecode->size; i++) {
1136 if (!fromDecode->insts[i]->isSquashed())
1137 inst_count++;
1138 }
1139
1140 return inst_count;
1141}
1142
1143template <class Impl>
1144void
1145DefaultRename<Impl>::readStallSignals(unsigned tid)
1146{
1147 if (fromIEW->iewBlock[tid]) {
1148 stalls[tid].iew = true;
1149 }
1150
1151 if (fromIEW->iewUnblock[tid]) {
1152 assert(stalls[tid].iew);
1153 stalls[tid].iew = false;
1154 }
1155
1156 if (fromCommit->commitBlock[tid]) {
1157 stalls[tid].commit = true;
1158 }
1159
1160 if (fromCommit->commitUnblock[tid]) {
1161 assert(stalls[tid].commit);
1162 stalls[tid].commit = false;
1163 }
1164}
1165
1166template <class Impl>
1167bool
1168DefaultRename<Impl>::checkStall(unsigned tid)
1169{
1170 bool ret_val = false;
1171
1172 if (stalls[tid].iew) {
1173 DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid);
1174 ret_val = true;
1175 } else if (stalls[tid].commit) {
1176 DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid);
1177 ret_val = true;
1178 } else if (calcFreeROBEntries(tid) <= 0) {
1179 DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid);
1180 ret_val = true;
1181 } else if (calcFreeIQEntries(tid) <= 0) {
1182 DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid);
1183 ret_val = true;
1184 } else if (calcFreeLSQEntries(tid) <= 0) {
1185 DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid);
1186 ret_val = true;
1187 } else if (renameMap[tid]->numFreeEntries() <= 0) {
1188 DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid);
1189 ret_val = true;
1190 } else if (renameStatus[tid] == SerializeStall &&
1191 (!emptyROB[tid] || instsInProgress[tid])) {
1192 DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not "
1193 "empty.\n",
1194 tid);
1195 ret_val = true;
1196 }
1197
1198 return ret_val;
1199}
1200
1201template <class Impl>
1202void
1203DefaultRename<Impl>::readFreeEntries(unsigned tid)
1204{
1205 bool updated = false;
1206 if (fromIEW->iewInfo[tid].usedIQ) {
1207 freeEntries[tid].iqEntries =
1208 fromIEW->iewInfo[tid].freeIQEntries;
1209 updated = true;
1210 }
1211
1212 if (fromIEW->iewInfo[tid].usedLSQ) {
1213 freeEntries[tid].lsqEntries =
1214 fromIEW->iewInfo[tid].freeLSQEntries;
1215 updated = true;
1216 }
1217
1218 if (fromCommit->commitInfo[tid].usedROB) {
1219 freeEntries[tid].robEntries =
1220 fromCommit->commitInfo[tid].freeROBEntries;
1221 emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB;
1222 updated = true;
1223 }
1224
1225 DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n",
1226 tid,
1227 freeEntries[tid].iqEntries,
1228 freeEntries[tid].robEntries,
1229 freeEntries[tid].lsqEntries);
1230
1231 DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n",
1232 tid, instsInProgress[tid]);
1233}
1234
1235template <class Impl>
1236bool
1237DefaultRename<Impl>::checkSignalsAndUpdate(unsigned tid)
1238{
1239 // Check if there's a squash signal, squash if there is
1240 // Check stall signals, block if necessary.
1241 // If status was blocked
1242 // check if stall conditions have passed
1243 // if so then go to unblocking
1244 // If status was Squashing
1245 // check if squashing is not high. Switch to running this cycle.
1246 // If status was serialize stall
1247 // check if ROB is empty and no insts are in flight to the ROB
1248
1249 readFreeEntries(tid);
1250 readStallSignals(tid);
1251
1252 if (fromCommit->commitInfo[tid].squash) {
1253 DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from "
1254 "commit.\n", tid);
1255
1256#if ISA_HAS_DELAY_SLOT
1257 InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
1258#else
1259 InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].doneSeqNum;
1260#endif
1261
1262 squash(squashed_seq_num, tid);
1263
1264 return true;
1265 }
1266
1267 if (fromCommit->commitInfo[tid].robSquashing) {
1268 DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid);
1269
1270 renameStatus[tid] = Squashing;
1271
1272 return true;
1273 }
1274
1275 if (checkStall(tid)) {
1276 return block(tid);
1277 }
1278
1279 if (renameStatus[tid] == Blocked) {
1280 DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n",
1281 tid);
1282
1283 renameStatus[tid] = Unblocking;
1284
1285 unblock(tid);
1286
1287 return true;
1288 }
1289
1290 if (renameStatus[tid] == Squashing) {
1291 // Switch status to running if rename isn't being told to block or
1292 // squash this cycle.
1293 if (resumeSerialize) {
1294 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n",
1295 tid);
1296
1297 renameStatus[tid] = SerializeStall;
1298 return true;
1299 } else if (resumeUnblocking) {
1300 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n",
1301 tid);
1302 renameStatus[tid] = Unblocking;
1303 return true;
1304 } else {
1305 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n",
1306 tid);
1307
1308 renameStatus[tid] = Running;
1309 return false;
1310 }
1311 }
1312
1313 if (renameStatus[tid] == SerializeStall) {
1314 // Stall ends once the ROB is free.
1315 DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to "
1316 "unblocking.\n", tid);
1317
1318 DynInstPtr serial_inst = serializeInst[tid];
1319
1320 renameStatus[tid] = Unblocking;
1321
1322 unblock(tid);
1323
1324 DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with "
1325 "PC %#x.\n",
1326 tid, serial_inst->seqNum, serial_inst->readPC());
1327
1328 // Put instruction into queue here.
1329 serial_inst->clearSerializeBefore();
1330
1331 if (!skidBuffer[tid].empty()) {
1332 skidBuffer[tid].push_front(serial_inst);
1333 } else {
1334 insts[tid].push_front(serial_inst);
1335 }
1336
1337 DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename."
1338 " Adding to front of list.\n", tid);
1339
1340 serializeInst[tid] = NULL;
1341
1342 return true;
1343 }
1344
1345 // If we've reached this point, we have not gotten any signals that
1346 // cause rename to change its status. Rename remains the same as before.
1347 return false;
1348}
1349
1350template<class Impl>
1351void
1352DefaultRename<Impl>::serializeAfter(InstQueue &inst_list,
1353 unsigned tid)
1354{
1355 if (inst_list.empty()) {
1356 // Mark a bit to say that I must serialize on the next instruction.
1357 serializeOnNextInst[tid] = true;
1358 return;
1359 }
1360
1361 // Set the next instruction as serializing.
1362 inst_list.front()->setSerializeBefore();
1363}
1364
1365template <class Impl>
1366inline void
1367DefaultRename<Impl>::incrFullStat(const FullSource &source)
1368{
1369 switch (source) {
1370 case ROB:
1371 ++renameROBFullEvents;
1372 break;
1373 case IQ:
1374 ++renameIQFullEvents;
1375 break;
1376 case LSQ:
1377 ++renameLSQFullEvents;
1378 break;
1379 default:
1380 panic("Rename full stall stat should be incremented for a reason!");
1381 break;
1382 }
1383}
1384
1385template <class Impl>
1386void
1387DefaultRename<Impl>::dumpHistory()
1388{
1389 typename std::list<RenameHistory>::iterator buf_it;
1390
1391 for (int i = 0; i < numThreads; i++) {
1392
1393 buf_it = historyBuffer[i].begin();
1394
1395 while (buf_it != historyBuffer[i].end()) {
1396 cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys "
1397 "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg,
1398 (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg);
1399
1400 buf_it++;
1401 }
1402 }
1403}
| 252 scoreboard = _scoreboard;
253}
254
255template <class Impl>
256bool
257DefaultRename<Impl>::drain()
258{
259 // Rename is ready to switch out at any time.
260 cpu->signalDrained();
261 return true;
262}
263
264template <class Impl>
265void
266DefaultRename<Impl>::switchOut()
267{
268 // Clear any state, fix up the rename map.
269 for (int i = 0; i < numThreads; i++) {
270 typename std::list<RenameHistory>::iterator hb_it =
271 historyBuffer[i].begin();
272
273 while (!historyBuffer[i].empty()) {
274 assert(hb_it != historyBuffer[i].end());
275
276 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
277 "number %i.\n", i, (*hb_it).instSeqNum);
278
279 // Tell the rename map to set the architected register to the
280 // previous physical register that it was renamed to.
281 renameMap[i]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
282
283 // Put the renamed physical register back on the free list.
284 freeList->addReg(hb_it->newPhysReg);
285
286 // Be sure to mark its register as ready if it's a misc register.
287 if (hb_it->newPhysReg >= maxPhysicalRegs) {
288 scoreboard->setReg(hb_it->newPhysReg);
289 }
290
291 historyBuffer[i].erase(hb_it++);
292 }
293 insts[i].clear();
294 skidBuffer[i].clear();
295 }
296}
297
298template <class Impl>
299void
300DefaultRename<Impl>::takeOverFrom()
301{
302 _status = Inactive;
303 initStage();
304
305 // Reset all state prior to taking over from the other CPU.
306 for (int i=0; i< numThreads; i++) {
307 renameStatus[i] = Idle;
308
309 stalls[i].iew = false;
310 stalls[i].commit = false;
311 serializeInst[i] = NULL;
312
313 instsInProgress[i] = 0;
314
315 emptyROB[i] = true;
316
317 serializeOnNextInst[i] = false;
318 }
319}
320
321template <class Impl>
322void
323DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, unsigned tid)
324{
325 DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid);
326
327 // Clear the stall signal if rename was blocked or unblocking before.
328 // If it still needs to block, the blocking should happen the next
329 // cycle and there should be space to hold everything due to the squash.
330 if (renameStatus[tid] == Blocked ||
331 renameStatus[tid] == Unblocking) {
332 toDecode->renameUnblock[tid] = 1;
333
334 resumeSerialize = false;
335 serializeInst[tid] = NULL;
336 } else if (renameStatus[tid] == SerializeStall) {
337 if (serializeInst[tid]->seqNum <= squash_seq_num) {
338 DPRINTF(Rename, "Rename will resume serializing after squash\n");
339 resumeSerialize = true;
340 assert(serializeInst[tid]);
341 } else {
342 resumeSerialize = false;
343 toDecode->renameUnblock[tid] = 1;
344
345 serializeInst[tid] = NULL;
346 }
347 }
348
349 // Set the status to Squashing.
350 renameStatus[tid] = Squashing;
351
352 // Squash any instructions from decode.
353 unsigned squashCount = 0;
354
355 for (int i=0; i<fromDecode->size; i++) {
356 if (fromDecode->insts[i]->threadNumber == tid &&
357 fromDecode->insts[i]->seqNum > squash_seq_num) {
358 fromDecode->insts[i]->setSquashed();
359 wroteToTimeBuffer = true;
360 squashCount++;
361 }
362
363 }
364
365 // Clear the instruction list and skid buffer in case they have any
366 // insts in them. Since we support multiple ISAs, we cant just:
367 // "insts[tid].clear();" or "skidBuffer[tid].clear()" since there is
368 // a possible delay slot inst for different architectures
369 // insts[tid].clear();
370#if ISA_HAS_DELAY_SLOT
371 DPRINTF(Rename, "[tid:%i] Squashing incoming decode instructions until "
372 "[sn:%i].\n",tid, squash_seq_num);
373 ListIt ilist_it = insts[tid].begin();
374 while (ilist_it != insts[tid].end()) {
375 if ((*ilist_it)->seqNum > squash_seq_num) {
376 (*ilist_it)->setSquashed();
377 DPRINTF(Rename, "Squashing incoming decode instruction, "
378 "[tid:%i] [sn:%i] PC %08p.\n", tid, (*ilist_it)->seqNum, (*ilist_it)->PC);
379 }
380 ilist_it++;
381 }
382#else
383 insts[tid].clear();
384#endif
385
386 // Clear the skid buffer in case it has any data in it.
387 // See comments above.
388 // skidBuffer[tid].clear();
389#if ISA_HAS_DELAY_SLOT
390 DPRINTF(Rename, "[tid:%i] Squashing incoming skidbuffer instructions "
391 "until [sn:%i].\n", tid, squash_seq_num);
392 ListIt slist_it = skidBuffer[tid].begin();
393 while (slist_it != skidBuffer[tid].end()) {
394 if ((*slist_it)->seqNum > squash_seq_num) {
395 (*slist_it)->setSquashed();
396 DPRINTF(Rename, "Squashing skidbuffer instruction, [tid:%i] [sn:%i]"
397 "PC %08p.\n", tid, (*slist_it)->seqNum, (*slist_it)->PC);
398 }
399 slist_it++;
400 }
401 resumeUnblocking = (skidBuffer[tid].size() != 0);
402 DPRINTF(Rename, "Resume unblocking set to %s\n",
403 resumeUnblocking ? "true" : "false");
404#else
405 skidBuffer[tid].clear();
406#endif
407 doSquash(squash_seq_num, tid);
408}
409
410template <class Impl>
411void
412DefaultRename<Impl>::tick()
413{
414 wroteToTimeBuffer = false;
415
416 blockThisCycle = false;
417
418 bool status_change = false;
419
420 toIEWIndex = 0;
421
422 sortInsts();
423
424 std::list<unsigned>::iterator threads = activeThreads->begin();
425 std::list<unsigned>::iterator end = activeThreads->end();
426
427 // Check stall and squash signals.
428 while (threads != end) {
429 unsigned tid = *threads++;
430
431 DPRINTF(Rename, "Processing [tid:%i]\n", tid);
432
433 status_change = checkSignalsAndUpdate(tid) || status_change;
434
435 rename(status_change, tid);
436 }
437
438 if (status_change) {
439 updateStatus();
440 }
441
442 if (wroteToTimeBuffer) {
443 DPRINTF(Activity, "Activity this cycle.\n");
444 cpu->activityThisCycle();
445 }
446
447 threads = activeThreads->begin();
448
449 while (threads != end) {
450 unsigned tid = *threads++;
451
452 // If we committed this cycle then doneSeqNum will be > 0
453 if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
454 !fromCommit->commitInfo[tid].squash &&
455 renameStatus[tid] != Squashing) {
456
457 removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum,
458 tid);
459 }
460 }
461
462 // @todo: make into updateProgress function
463 for (int tid=0; tid < numThreads; tid++) {
464 instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched;
465
466 assert(instsInProgress[tid] >=0);
467 }
468
469}
470
471template<class Impl>
472void
473DefaultRename<Impl>::rename(bool &status_change, unsigned tid)
474{
475 // If status is Running or idle,
476 // call renameInsts()
477 // If status is Unblocking,
478 // buffer any instructions coming from decode
479 // continue trying to empty skid buffer
480 // check if stall conditions have passed
481
482 if (renameStatus[tid] == Blocked) {
483 ++renameBlockCycles;
484 } else if (renameStatus[tid] == Squashing) {
485 ++renameSquashCycles;
486 } else if (renameStatus[tid] == SerializeStall) {
487 ++renameSerializeStallCycles;
488 // If we are currently in SerializeStall and resumeSerialize
489 // was set, then that means that we are resuming serializing
490 // this cycle. Tell the previous stages to block.
491 if (resumeSerialize) {
492 resumeSerialize = false;
493 block(tid);
494 toDecode->renameUnblock[tid] = false;
495 }
496 } else if (renameStatus[tid] == Unblocking) {
497 if (resumeUnblocking) {
498 block(tid);
499 resumeUnblocking = false;
500 toDecode->renameUnblock[tid] = false;
501 }
502 }
503
504 if (renameStatus[tid] == Running ||
505 renameStatus[tid] == Idle) {
506 DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run "
507 "stage.\n", tid);
508
509 renameInsts(tid);
510 } else if (renameStatus[tid] == Unblocking) {
511 renameInsts(tid);
512
513 if (validInsts()) {
514 // Add the current inputs to the skid buffer so they can be
515 // reprocessed when this stage unblocks.
516 skidInsert(tid);
517 }
518
519 // If we switched over to blocking, then there's a potential for
520 // an overall status change.
521 status_change = unblock(tid) || status_change || blockThisCycle;
522 }
523}
524
525template <class Impl>
526void
527DefaultRename<Impl>::renameInsts(unsigned tid)
528{
529 // Instructions can be either in the skid buffer or the queue of
530 // instructions coming from decode, depending on the status.
531 int insts_available = renameStatus[tid] == Unblocking ?
532 skidBuffer[tid].size() : insts[tid].size();
533
534 // Check the decode queue to see if instructions are available.
535 // If there are no available instructions to rename, then do nothing.
536 if (insts_available == 0) {
537 DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n",
538 tid);
539 // Should I change status to idle?
540 ++renameIdleCycles;
541 return;
542 } else if (renameStatus[tid] == Unblocking) {
543 ++renameUnblockCycles;
544 } else if (renameStatus[tid] == Running) {
545 ++renameRunCycles;
546 }
547
548 DynInstPtr inst;
549
550 // Will have to do a different calculation for the number of free
551 // entries.
552 int free_rob_entries = calcFreeROBEntries(tid);
553 int free_iq_entries = calcFreeIQEntries(tid);
554 int free_lsq_entries = calcFreeLSQEntries(tid);
555 int min_free_entries = free_rob_entries;
556
557 FullSource source = ROB;
558
559 if (free_iq_entries < min_free_entries) {
560 min_free_entries = free_iq_entries;
561 source = IQ;
562 }
563
564 if (free_lsq_entries < min_free_entries) {
565 min_free_entries = free_lsq_entries;
566 source = LSQ;
567 }
568
569 // Check if there's any space left.
570 if (min_free_entries <= 0) {
571 DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ "
572 "entries.\n"
573 "ROB has %i free entries.\n"
574 "IQ has %i free entries.\n"
575 "LSQ has %i free entries.\n",
576 tid,
577 free_rob_entries,
578 free_iq_entries,
579 free_lsq_entries);
580
581 blockThisCycle = true;
582
583 block(tid);
584
585 incrFullStat(source);
586
587 return;
588 } else if (min_free_entries < insts_available) {
589 DPRINTF(Rename, "[tid:%u]: Will have to block this cycle."
590 "%i insts available, but only %i insts can be "
591 "renamed due to ROB/IQ/LSQ limits.\n",
592 tid, insts_available, min_free_entries);
593
594 insts_available = min_free_entries;
595
596 blockThisCycle = true;
597
598 incrFullStat(source);
599 }
600
601 InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ?
602 skidBuffer[tid] : insts[tid];
603
604 DPRINTF(Rename, "[tid:%u]: %i available instructions to "
605 "send iew.\n", tid, insts_available);
606
607 DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts "
608 "dispatched to IQ last cycle.\n",
609 tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched);
610
611 // Handle serializing the next instruction if necessary.
612 if (serializeOnNextInst[tid]) {
613 if (emptyROB[tid] && instsInProgress[tid] == 0) {
614 // ROB already empty; no need to serialize.
615 serializeOnNextInst[tid] = false;
616 } else if (!insts_to_rename.empty()) {
617 insts_to_rename.front()->setSerializeBefore();
618 }
619 }
620
621 int renamed_insts = 0;
622
623 while (insts_available > 0 && toIEWIndex < renameWidth) {
624 DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid);
625
626 assert(!insts_to_rename.empty());
627
628 inst = insts_to_rename.front();
629
630 insts_to_rename.pop_front();
631
632 if (renameStatus[tid] == Unblocking) {
633 DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%#x from rename "
634 "skidBuffer\n",
635 tid, inst->seqNum, inst->readPC());
636 }
637
638 if (inst->isSquashed()) {
639 DPRINTF(Rename, "[tid:%u]: instruction %i with PC %#x is "
640 "squashed, skipping.\n",
641 tid, inst->seqNum, inst->readPC());
642
643 ++renameSquashedInsts;
644
645 // Decrement how many instructions are available.
646 --insts_available;
647
648 continue;
649 }
650
651 DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with "
652 "PC %#x.\n",
653 tid, inst->seqNum, inst->readPC());
654
655 // Handle serializeAfter/serializeBefore instructions.
656 // serializeAfter marks the next instruction as serializeBefore.
657 // serializeBefore makes the instruction wait in rename until the ROB
658 // is empty.
659
660 // In this model, IPR accesses are serialize before
661 // instructions, and store conditionals are serialize after
662 // instructions. This is mainly due to lack of support for
663 // out-of-order operations of either of those classes of
664 // instructions.
665 if ((inst->isIprAccess() || inst->isSerializeBefore()) &&
666 !inst->isSerializeHandled()) {
667 DPRINTF(Rename, "Serialize before instruction encountered.\n");
668
669 if (!inst->isTempSerializeBefore()) {
670 renamedSerializing++;
671 inst->setSerializeHandled();
672 } else {
673 renamedTempSerializing++;
674 }
675
676 // Change status over to SerializeStall so that other stages know
677 // what this is blocked on.
678 renameStatus[tid] = SerializeStall;
679
680 serializeInst[tid] = inst;
681
682 blockThisCycle = true;
683
684 break;
685 } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) &&
686 !inst->isSerializeHandled()) {
687 DPRINTF(Rename, "Serialize after instruction encountered.\n");
688
689 renamedSerializing++;
690
691 inst->setSerializeHandled();
692
693 serializeAfter(insts_to_rename, tid);
694 }
695
696 // Check here to make sure there are enough destination registers
697 // to rename to. Otherwise block.
698 if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) {
699 DPRINTF(Rename, "Blocking due to lack of free "
700 "physical registers to rename to.\n");
701 blockThisCycle = true;
702
703 ++renameFullRegistersEvents;
704
705 break;
706 }
707
708 renameSrcRegs(inst, inst->threadNumber);
709
710 renameDestRegs(inst, inst->threadNumber);
711
712 ++renamed_insts;
713
714 // Put instruction in rename queue.
715 toIEW->insts[toIEWIndex] = inst;
716 ++(toIEW->size);
717
718 // Increment which instruction we're on.
719 ++toIEWIndex;
720
721 // Decrement how many instructions are available.
722 --insts_available;
723 }
724
725 instsInProgress[tid] += renamed_insts;
726 renameRenamedInsts += renamed_insts;
727
728 // If we wrote to the time buffer, record this.
729 if (toIEWIndex) {
730 wroteToTimeBuffer = true;
731 }
732
733 // Check if there's any instructions left that haven't yet been renamed.
734 // If so then block.
735 if (insts_available) {
736 blockThisCycle = true;
737 }
738
739 if (blockThisCycle) {
740 block(tid);
741 toDecode->renameUnblock[tid] = false;
742 }
743}
744
745template<class Impl>
746void
747DefaultRename<Impl>::skidInsert(unsigned tid)
748{
749 DynInstPtr inst = NULL;
750
751 while (!insts[tid].empty()) {
752 inst = insts[tid].front();
753
754 insts[tid].pop_front();
755
756 assert(tid == inst->threadNumber);
757
758 DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC:%#x into Rename "
759 "skidBuffer\n", tid, inst->seqNum, inst->readPC());
760
761 ++renameSkidInsts;
762
763 skidBuffer[tid].push_back(inst);
764 }
765
766 if (skidBuffer[tid].size() > skidBufferMax)
767 {
768 typename InstQueue::iterator it;
769 warn("Skidbuffer contents:\n");
770 for(it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++)
771 {
772 warn("[tid:%u]: %s [sn:%i].\n", tid,
773 (*it)->staticInst->disassemble(inst->readPC()),
774 (*it)->seqNum);
775 }
776 panic("Skidbuffer Exceeded Max Size");
777 }
778}
779
780template <class Impl>
781void
782DefaultRename<Impl>::sortInsts()
783{
784 int insts_from_decode = fromDecode->size;
785#ifdef DEBUG
786#if !ISA_HAS_DELAY_SLOT
787 for (int i=0; i < numThreads; i++)
788 assert(insts[i].empty());
789#endif
790#endif
791 for (int i = 0; i < insts_from_decode; ++i) {
792 DynInstPtr inst = fromDecode->insts[i];
793 insts[inst->threadNumber].push_back(inst);
794 }
795}
796
797template<class Impl>
798bool
799DefaultRename<Impl>::skidsEmpty()
800{
801 std::list<unsigned>::iterator threads = activeThreads->begin();
802 std::list<unsigned>::iterator end = activeThreads->end();
803
804 while (threads != end) {
805 unsigned tid = *threads++;
806
807 if (!skidBuffer[tid].empty())
808 return false;
809 }
810
811 return true;
812}
813
814template<class Impl>
815void
816DefaultRename<Impl>::updateStatus()
817{
818 bool any_unblocking = false;
819
820 std::list<unsigned>::iterator threads = activeThreads->begin();
821 std::list<unsigned>::iterator end = activeThreads->end();
822
823 while (threads != end) {
824 unsigned tid = *threads++;
825
826 if (renameStatus[tid] == Unblocking) {
827 any_unblocking = true;
828 break;
829 }
830 }
831
832 // Rename will have activity if it's unblocking.
833 if (any_unblocking) {
834 if (_status == Inactive) {
835 _status = Active;
836
837 DPRINTF(Activity, "Activating stage.\n");
838
839 cpu->activateStage(O3CPU::RenameIdx);
840 }
841 } else {
842 // If it's not unblocking, then rename will not have any internal
843 // activity. Switch it to inactive.
844 if (_status == Active) {
845 _status = Inactive;
846 DPRINTF(Activity, "Deactivating stage.\n");
847
848 cpu->deactivateStage(O3CPU::RenameIdx);
849 }
850 }
851}
852
853template <class Impl>
854bool
855DefaultRename<Impl>::block(unsigned tid)
856{
857 DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid);
858
859 // Add the current inputs onto the skid buffer, so they can be
860 // reprocessed when this stage unblocks.
861 skidInsert(tid);
862
863 // Only signal backwards to block if the previous stages do not think
864 // rename is already blocked.
865 if (renameStatus[tid] != Blocked) {
866 // If resumeUnblocking is set, we unblocked during the squash,
867 // but now we're have unblocking status. We need to tell earlier
868 // stages to block.
869 if (resumeUnblocking || renameStatus[tid] != Unblocking) {
870 toDecode->renameBlock[tid] = true;
871 toDecode->renameUnblock[tid] = false;
872 wroteToTimeBuffer = true;
873 }
874
875 // Rename can not go from SerializeStall to Blocked, otherwise
876 // it would not know to complete the serialize stall.
877 if (renameStatus[tid] != SerializeStall) {
878 // Set status to Blocked.
879 renameStatus[tid] = Blocked;
880 return true;
881 }
882 }
883
884 return false;
885}
886
887template <class Impl>
888bool
889DefaultRename<Impl>::unblock(unsigned tid)
890{
891 DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid);
892
893 // Rename is done unblocking if the skid buffer is empty.
894 if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) {
895
896 DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid);
897
898 toDecode->renameUnblock[tid] = true;
899 wroteToTimeBuffer = true;
900
901 renameStatus[tid] = Running;
902 return true;
903 }
904
905 return false;
906}
907
908template <class Impl>
909void
910DefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, unsigned tid)
911{
912 typename std::list<RenameHistory>::iterator hb_it =
913 historyBuffer[tid].begin();
914
915 // After a syscall squashes everything, the history buffer may be empty
916 // but the ROB may still be squashing instructions.
917 if (historyBuffer[tid].empty()) {
918 return;
919 }
920
921 // Go through the most recent instructions, undoing the mappings
922 // they did and freeing up the registers.
923 while (!historyBuffer[tid].empty() &&
924 (*hb_it).instSeqNum > squashed_seq_num) {
925 assert(hb_it != historyBuffer[tid].end());
926
927 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
928 "number %i.\n", tid, (*hb_it).instSeqNum);
929
930 // Tell the rename map to set the architected register to the
931 // previous physical register that it was renamed to.
932 renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
933
934 // Put the renamed physical register back on the free list.
935 freeList->addReg(hb_it->newPhysReg);
936
937 // Be sure to mark its register as ready if it's a misc register.
938 if (hb_it->newPhysReg >= maxPhysicalRegs) {
939 scoreboard->setReg(hb_it->newPhysReg);
940 }
941
942 historyBuffer[tid].erase(hb_it++);
943
944 ++renameUndoneMaps;
945 }
946}
947
948template<class Impl>
949void
950DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, unsigned tid)
951{
952 DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the "
953 "history buffer %u (size=%i), until [sn:%lli].\n",
954 tid, tid, historyBuffer[tid].size(), inst_seq_num);
955
956 typename std::list<RenameHistory>::iterator hb_it =
957 historyBuffer[tid].end();
958
959 --hb_it;
960
961 if (historyBuffer[tid].empty()) {
962 DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid);
963 return;
964 } else if (hb_it->instSeqNum > inst_seq_num) {
965 DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure "
966 "that a syscall happened recently.\n", tid);
967 return;
968 }
969
970 // Commit all the renames up until (and including) the committed sequence
971 // number. Some or even all of the committed instructions may not have
972 // rename histories if they did not have destination registers that were
973 // renamed.
974 while (!historyBuffer[tid].empty() &&
975 hb_it != historyBuffer[tid].end() &&
976 (*hb_it).instSeqNum <= inst_seq_num) {
977
978 DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, "
979 "[sn:%lli].\n",
980 tid, (*hb_it).prevPhysReg, (*hb_it).instSeqNum);
981
982 freeList->addReg((*hb_it).prevPhysReg);
983 ++renameCommittedMaps;
984
985 historyBuffer[tid].erase(hb_it--);
986 }
987}
988
989template <class Impl>
990inline void
991DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst,unsigned tid)
992{
993 assert(renameMap[tid] != 0);
994
995 unsigned num_src_regs = inst->numSrcRegs();
996
997 // Get the architectual register numbers from the source and
998 // destination operands, and redirect them to the right register.
999 // Will need to mark dependencies though.
1000 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) {
1001 RegIndex src_reg = inst->srcRegIdx(src_idx);
1002 RegIndex flat_src_reg = src_reg;
1003 if (src_reg < TheISA::FP_Base_DepTag) {
1004 flat_src_reg = TheISA::flattenIntIndex(inst->tcBase(), src_reg);
1005 DPRINTF(Rename, "Flattening index %d to %d.\n", (int)src_reg, (int)flat_src_reg);
1006 }
1007 inst->flattenSrcReg(src_idx, flat_src_reg);
1008
1009 // Look up the source registers to get the phys. register they've
1010 // been renamed to, and set the sources to those registers.
1011 PhysRegIndex renamed_reg = renameMap[tid]->lookup(flat_src_reg);
1012
1013 DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got "
1014 "physical reg %i.\n", tid, (int)flat_src_reg,
1015 (int)renamed_reg);
1016
1017 inst->renameSrcReg(src_idx, renamed_reg);
1018
1019 // See if the register is ready or not.
1020 if (scoreboard->getReg(renamed_reg) == true) {
1021 DPRINTF(Rename, "[tid:%u]: Register is ready.\n", tid);
1022
1023 inst->markSrcRegReady(src_idx);
1024 }
1025
1026 ++renameRenameLookups;
1027 }
1028}
1029
1030template <class Impl>
1031inline void
1032DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst,unsigned tid)
1033{
1034 typename RenameMap::RenameInfo rename_result;
1035
1036 unsigned num_dest_regs = inst->numDestRegs();
1037
1038 // Rename the destination registers.
1039 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) {
1040 RegIndex dest_reg = inst->destRegIdx(dest_idx);
1041 RegIndex flat_dest_reg = dest_reg;
1042 if (dest_reg < TheISA::FP_Base_DepTag) {
1043 flat_dest_reg = TheISA::flattenIntIndex(inst->tcBase(), dest_reg);
1044 DPRINTF(Rename, "Flattening index %d to %d.\n", (int)dest_reg, (int)flat_dest_reg);
1045 }
1046
1047 inst->flattenDestReg(dest_idx, flat_dest_reg);
1048
1049 // Get the physical register that the destination will be
1050 // renamed to.
1051 rename_result = renameMap[tid]->rename(flat_dest_reg);
1052
1053 //Mark Scoreboard entry as not ready
1054 scoreboard->unsetReg(rename_result.first);
1055
1056 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical "
1057 "reg %i.\n", tid, (int)flat_dest_reg,
1058 (int)rename_result.first);
1059
1060 // Record the rename information so that a history can be kept.
1061 RenameHistory hb_entry(inst->seqNum, flat_dest_reg,
1062 rename_result.first,
1063 rename_result.second);
1064
1065 historyBuffer[tid].push_front(hb_entry);
1066
1067 DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer "
1068 "(size=%i), [sn:%lli].\n",tid,
1069 historyBuffer[tid].size(),
1070 (*historyBuffer[tid].begin()).instSeqNum);
1071
1072 // Tell the instruction to rename the appropriate destination
1073 // register (dest_idx) to the new physical register
1074 // (rename_result.first), and record the previous physical
1075 // register that the same logical register was renamed to
1076 // (rename_result.second).
1077 inst->renameDestReg(dest_idx,
1078 rename_result.first,
1079 rename_result.second);
1080
1081 ++renameRenamedOperands;
1082 }
1083}
1084
1085template <class Impl>
1086inline int
1087DefaultRename<Impl>::calcFreeROBEntries(unsigned tid)
1088{
1089 int num_free = freeEntries[tid].robEntries -
1090 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1091
1092 //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free);
1093
1094 return num_free;
1095}
1096
1097template <class Impl>
1098inline int
1099DefaultRename<Impl>::calcFreeIQEntries(unsigned tid)
1100{
1101 int num_free = freeEntries[tid].iqEntries -
1102 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1103
1104 //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free);
1105
1106 return num_free;
1107}
1108
1109template <class Impl>
1110inline int
1111DefaultRename<Impl>::calcFreeLSQEntries(unsigned tid)
1112{
1113 int num_free = freeEntries[tid].lsqEntries -
1114 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ);
1115
1116 //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free);
1117
1118 return num_free;
1119}
1120
1121template <class Impl>
1122unsigned
1123DefaultRename<Impl>::validInsts()
1124{
1125 unsigned inst_count = 0;
1126
1127 for (int i=0; i<fromDecode->size; i++) {
1128 if (!fromDecode->insts[i]->isSquashed())
1129 inst_count++;
1130 }
1131
1132 return inst_count;
1133}
1134
1135template <class Impl>
1136void
1137DefaultRename<Impl>::readStallSignals(unsigned tid)
1138{
1139 if (fromIEW->iewBlock[tid]) {
1140 stalls[tid].iew = true;
1141 }
1142
1143 if (fromIEW->iewUnblock[tid]) {
1144 assert(stalls[tid].iew);
1145 stalls[tid].iew = false;
1146 }
1147
1148 if (fromCommit->commitBlock[tid]) {
1149 stalls[tid].commit = true;
1150 }
1151
1152 if (fromCommit->commitUnblock[tid]) {
1153 assert(stalls[tid].commit);
1154 stalls[tid].commit = false;
1155 }
1156}
1157
1158template <class Impl>
1159bool
1160DefaultRename<Impl>::checkStall(unsigned tid)
1161{
1162 bool ret_val = false;
1163
1164 if (stalls[tid].iew) {
1165 DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid);
1166 ret_val = true;
1167 } else if (stalls[tid].commit) {
1168 DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid);
1169 ret_val = true;
1170 } else if (calcFreeROBEntries(tid) <= 0) {
1171 DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid);
1172 ret_val = true;
1173 } else if (calcFreeIQEntries(tid) <= 0) {
1174 DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid);
1175 ret_val = true;
1176 } else if (calcFreeLSQEntries(tid) <= 0) {
1177 DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid);
1178 ret_val = true;
1179 } else if (renameMap[tid]->numFreeEntries() <= 0) {
1180 DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid);
1181 ret_val = true;
1182 } else if (renameStatus[tid] == SerializeStall &&
1183 (!emptyROB[tid] || instsInProgress[tid])) {
1184 DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not "
1185 "empty.\n",
1186 tid);
1187 ret_val = true;
1188 }
1189
1190 return ret_val;
1191}
1192
1193template <class Impl>
1194void
1195DefaultRename<Impl>::readFreeEntries(unsigned tid)
1196{
1197 bool updated = false;
1198 if (fromIEW->iewInfo[tid].usedIQ) {
1199 freeEntries[tid].iqEntries =
1200 fromIEW->iewInfo[tid].freeIQEntries;
1201 updated = true;
1202 }
1203
1204 if (fromIEW->iewInfo[tid].usedLSQ) {
1205 freeEntries[tid].lsqEntries =
1206 fromIEW->iewInfo[tid].freeLSQEntries;
1207 updated = true;
1208 }
1209
1210 if (fromCommit->commitInfo[tid].usedROB) {
1211 freeEntries[tid].robEntries =
1212 fromCommit->commitInfo[tid].freeROBEntries;
1213 emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB;
1214 updated = true;
1215 }
1216
1217 DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n",
1218 tid,
1219 freeEntries[tid].iqEntries,
1220 freeEntries[tid].robEntries,
1221 freeEntries[tid].lsqEntries);
1222
1223 DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n",
1224 tid, instsInProgress[tid]);
1225}
1226
1227template <class Impl>
1228bool
1229DefaultRename<Impl>::checkSignalsAndUpdate(unsigned tid)
1230{
1231 // Check if there's a squash signal, squash if there is
1232 // Check stall signals, block if necessary.
1233 // If status was blocked
1234 // check if stall conditions have passed
1235 // if so then go to unblocking
1236 // If status was Squashing
1237 // check if squashing is not high. Switch to running this cycle.
1238 // If status was serialize stall
1239 // check if ROB is empty and no insts are in flight to the ROB
1240
1241 readFreeEntries(tid);
1242 readStallSignals(tid);
1243
1244 if (fromCommit->commitInfo[tid].squash) {
1245 DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from "
1246 "commit.\n", tid);
1247
1248#if ISA_HAS_DELAY_SLOT
1249 InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
1250#else
1251 InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].doneSeqNum;
1252#endif
1253
1254 squash(squashed_seq_num, tid);
1255
1256 return true;
1257 }
1258
1259 if (fromCommit->commitInfo[tid].robSquashing) {
1260 DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid);
1261
1262 renameStatus[tid] = Squashing;
1263
1264 return true;
1265 }
1266
1267 if (checkStall(tid)) {
1268 return block(tid);
1269 }
1270
1271 if (renameStatus[tid] == Blocked) {
1272 DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n",
1273 tid);
1274
1275 renameStatus[tid] = Unblocking;
1276
1277 unblock(tid);
1278
1279 return true;
1280 }
1281
1282 if (renameStatus[tid] == Squashing) {
1283 // Switch status to running if rename isn't being told to block or
1284 // squash this cycle.
1285 if (resumeSerialize) {
1286 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n",
1287 tid);
1288
1289 renameStatus[tid] = SerializeStall;
1290 return true;
1291 } else if (resumeUnblocking) {
1292 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n",
1293 tid);
1294 renameStatus[tid] = Unblocking;
1295 return true;
1296 } else {
1297 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n",
1298 tid);
1299
1300 renameStatus[tid] = Running;
1301 return false;
1302 }
1303 }
1304
1305 if (renameStatus[tid] == SerializeStall) {
1306 // Stall ends once the ROB is free.
1307 DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to "
1308 "unblocking.\n", tid);
1309
1310 DynInstPtr serial_inst = serializeInst[tid];
1311
1312 renameStatus[tid] = Unblocking;
1313
1314 unblock(tid);
1315
1316 DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with "
1317 "PC %#x.\n",
1318 tid, serial_inst->seqNum, serial_inst->readPC());
1319
1320 // Put instruction into queue here.
1321 serial_inst->clearSerializeBefore();
1322
1323 if (!skidBuffer[tid].empty()) {
1324 skidBuffer[tid].push_front(serial_inst);
1325 } else {
1326 insts[tid].push_front(serial_inst);
1327 }
1328
1329 DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename."
1330 " Adding to front of list.\n", tid);
1331
1332 serializeInst[tid] = NULL;
1333
1334 return true;
1335 }
1336
1337 // If we've reached this point, we have not gotten any signals that
1338 // cause rename to change its status. Rename remains the same as before.
1339 return false;
1340}
1341
1342template<class Impl>
1343void
1344DefaultRename<Impl>::serializeAfter(InstQueue &inst_list,
1345 unsigned tid)
1346{
1347 if (inst_list.empty()) {
1348 // Mark a bit to say that I must serialize on the next instruction.
1349 serializeOnNextInst[tid] = true;
1350 return;
1351 }
1352
1353 // Set the next instruction as serializing.
1354 inst_list.front()->setSerializeBefore();
1355}
1356
1357template <class Impl>
1358inline void
1359DefaultRename<Impl>::incrFullStat(const FullSource &source)
1360{
1361 switch (source) {
1362 case ROB:
1363 ++renameROBFullEvents;
1364 break;
1365 case IQ:
1366 ++renameIQFullEvents;
1367 break;
1368 case LSQ:
1369 ++renameLSQFullEvents;
1370 break;
1371 default:
1372 panic("Rename full stall stat should be incremented for a reason!");
1373 break;
1374 }
1375}
1376
1377template <class Impl>
1378void
1379DefaultRename<Impl>::dumpHistory()
1380{
1381 typename std::list<RenameHistory>::iterator buf_it;
1382
1383 for (int i = 0; i < numThreads; i++) {
1384
1385 buf_it = historyBuffer[i].begin();
1386
1387 while (buf_it != historyBuffer[i].end()) {
1388 cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys "
1389 "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg,
1390 (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg);
1391
1392 buf_it++;
1393 }
1394 }
1395}
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