1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 * Korey Sewell 30 */ 31 32#include <list> 33
| 1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 * Korey Sewell 30 */ 31 32#include <list> 33
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| 34#include "arch/isa_traits.hh" 35#include "arch/regfile.hh"
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34#include "config/full_system.hh" 35#include "cpu/o3/rename.hh" 36 37template <class Impl> 38DefaultRename<Impl>::DefaultRename(Params *params) 39 : iewToRenameDelay(params->iewToRenameDelay), 40 decodeToRenameDelay(params->decodeToRenameDelay), 41 commitToRenameDelay(params->commitToRenameDelay), 42 renameWidth(params->renameWidth), 43 commitWidth(params->commitWidth),
| 36#include "config/full_system.hh" 37#include "cpu/o3/rename.hh" 38 39template <class Impl> 40DefaultRename<Impl>::DefaultRename(Params *params) 41 : iewToRenameDelay(params->iewToRenameDelay), 42 decodeToRenameDelay(params->decodeToRenameDelay), 43 commitToRenameDelay(params->commitToRenameDelay), 44 renameWidth(params->renameWidth), 45 commitWidth(params->commitWidth),
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| 46 resumeSerialize(false), 47 resumeUnblocking(false),
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44 numThreads(params->numberOfThreads), 45 maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs) 46{ 47 _status = Inactive; 48 49 for (int i=0; i< numThreads; i++) { 50 renameStatus[i] = Idle; 51 52 freeEntries[i].iqEntries = 0; 53 freeEntries[i].lsqEntries = 0; 54 freeEntries[i].robEntries = 0; 55 56 stalls[i].iew = false; 57 stalls[i].commit = false; 58 serializeInst[i] = NULL; 59 60 instsInProgress[i] = 0; 61 62 emptyROB[i] = true; 63 64 serializeOnNextInst[i] = false; 65 } 66 67 // @todo: Make into a parameter. 68 skidBufferMax = (2 * (iewToRenameDelay * params->decodeWidth)) + renameWidth; 69} 70 71template <class Impl> 72std::string 73DefaultRename<Impl>::name() const 74{ 75 return cpu->name() + ".rename"; 76} 77 78template <class Impl> 79void 80DefaultRename<Impl>::regStats() 81{ 82 renameSquashCycles 83 .name(name() + ".RENAME:SquashCycles") 84 .desc("Number of cycles rename is squashing") 85 .prereq(renameSquashCycles); 86 renameIdleCycles 87 .name(name() + ".RENAME:IdleCycles") 88 .desc("Number of cycles rename is idle") 89 .prereq(renameIdleCycles); 90 renameBlockCycles 91 .name(name() + ".RENAME:BlockCycles") 92 .desc("Number of cycles rename is blocking") 93 .prereq(renameBlockCycles); 94 renameSerializeStallCycles 95 .name(name() + ".RENAME:serializeStallCycles") 96 .desc("count of cycles rename stalled for serializing inst") 97 .flags(Stats::total); 98 renameRunCycles 99 .name(name() + ".RENAME:RunCycles") 100 .desc("Number of cycles rename is running") 101 .prereq(renameIdleCycles); 102 renameUnblockCycles 103 .name(name() + ".RENAME:UnblockCycles") 104 .desc("Number of cycles rename is unblocking") 105 .prereq(renameUnblockCycles); 106 renameRenamedInsts 107 .name(name() + ".RENAME:RenamedInsts") 108 .desc("Number of instructions processed by rename") 109 .prereq(renameRenamedInsts); 110 renameSquashedInsts 111 .name(name() + ".RENAME:SquashedInsts") 112 .desc("Number of squashed instructions processed by rename") 113 .prereq(renameSquashedInsts); 114 renameROBFullEvents 115 .name(name() + ".RENAME:ROBFullEvents") 116 .desc("Number of times rename has blocked due to ROB full") 117 .prereq(renameROBFullEvents); 118 renameIQFullEvents 119 .name(name() + ".RENAME:IQFullEvents") 120 .desc("Number of times rename has blocked due to IQ full") 121 .prereq(renameIQFullEvents); 122 renameLSQFullEvents 123 .name(name() + ".RENAME:LSQFullEvents") 124 .desc("Number of times rename has blocked due to LSQ full") 125 .prereq(renameLSQFullEvents); 126 renameFullRegistersEvents 127 .name(name() + ".RENAME:FullRegisterEvents") 128 .desc("Number of times there has been no free registers") 129 .prereq(renameFullRegistersEvents); 130 renameRenamedOperands 131 .name(name() + ".RENAME:RenamedOperands") 132 .desc("Number of destination operands rename has renamed") 133 .prereq(renameRenamedOperands); 134 renameRenameLookups 135 .name(name() + ".RENAME:RenameLookups") 136 .desc("Number of register rename lookups that rename has made") 137 .prereq(renameRenameLookups); 138 renameCommittedMaps 139 .name(name() + ".RENAME:CommittedMaps") 140 .desc("Number of HB maps that are committed") 141 .prereq(renameCommittedMaps); 142 renameUndoneMaps 143 .name(name() + ".RENAME:UndoneMaps") 144 .desc("Number of HB maps that are undone due to squashing") 145 .prereq(renameUndoneMaps); 146 renamedSerializing 147 .name(name() + ".RENAME:serializingInsts") 148 .desc("count of serializing insts renamed") 149 .flags(Stats::total) 150 ; 151 renamedTempSerializing 152 .name(name() + ".RENAME:tempSerializingInsts") 153 .desc("count of temporary serializing insts renamed") 154 .flags(Stats::total) 155 ; 156 renameSkidInsts 157 .name(name() + ".RENAME:skidInsts") 158 .desc("count of insts added to the skid buffer") 159 .flags(Stats::total) 160 ; 161} 162 163template <class Impl> 164void 165DefaultRename<Impl>::setCPU(O3CPU *cpu_ptr) 166{ 167 DPRINTF(Rename, "Setting CPU pointer.\n"); 168 cpu = cpu_ptr; 169} 170 171template <class Impl> 172void 173DefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 174{ 175 DPRINTF(Rename, "Setting time buffer pointer.\n"); 176 timeBuffer = tb_ptr; 177 178 // Setup wire to read information from time buffer, from IEW stage. 179 fromIEW = timeBuffer->getWire(-iewToRenameDelay); 180 181 // Setup wire to read infromation from time buffer, from commit stage. 182 fromCommit = timeBuffer->getWire(-commitToRenameDelay); 183 184 // Setup wire to write information to previous stages. 185 toDecode = timeBuffer->getWire(0); 186} 187 188template <class Impl> 189void 190DefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 191{ 192 DPRINTF(Rename, "Setting rename queue pointer.\n"); 193 renameQueue = rq_ptr; 194 195 // Setup wire to write information to future stages. 196 toIEW = renameQueue->getWire(0); 197} 198 199template <class Impl> 200void 201DefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 202{ 203 DPRINTF(Rename, "Setting decode queue pointer.\n"); 204 decodeQueue = dq_ptr; 205 206 // Setup wire to get information from decode. 207 fromDecode = decodeQueue->getWire(-decodeToRenameDelay); 208} 209 210template <class Impl> 211void 212DefaultRename<Impl>::initStage() 213{ 214 // Grab the number of free entries directly from the stages. 215 for (int tid=0; tid < numThreads; tid++) { 216 freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid); 217 freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid); 218 freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid); 219 emptyROB[tid] = true; 220 } 221} 222 223template<class Impl> 224void 225DefaultRename<Impl>::setActiveThreads(std::list<unsigned> *at_ptr) 226{ 227 DPRINTF(Rename, "Setting active threads list pointer.\n"); 228 activeThreads = at_ptr; 229} 230 231 232template <class Impl> 233void 234DefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[]) 235{ 236 DPRINTF(Rename, "Setting rename map pointers.\n"); 237 238 for (int i=0; i<numThreads; i++) { 239 renameMap[i] = &rm_ptr[i]; 240 } 241} 242 243template <class Impl> 244void 245DefaultRename<Impl>::setFreeList(FreeList *fl_ptr) 246{ 247 DPRINTF(Rename, "Setting free list pointer.\n"); 248 freeList = fl_ptr; 249} 250 251template<class Impl> 252void 253DefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard) 254{ 255 DPRINTF(Rename, "Setting scoreboard pointer.\n"); 256 scoreboard = _scoreboard; 257} 258 259template <class Impl> 260bool 261DefaultRename<Impl>::drain() 262{ 263 // Rename is ready to switch out at any time. 264 cpu->signalDrained(); 265 return true; 266} 267 268template <class Impl> 269void 270DefaultRename<Impl>::switchOut() 271{ 272 // Clear any state, fix up the rename map. 273 for (int i = 0; i < numThreads; i++) { 274 typename std::list<RenameHistory>::iterator hb_it = 275 historyBuffer[i].begin(); 276 277 while (!historyBuffer[i].empty()) { 278 assert(hb_it != historyBuffer[i].end()); 279 280 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 281 "number %i.\n", i, (*hb_it).instSeqNum); 282 283 // Tell the rename map to set the architected register to the 284 // previous physical register that it was renamed to. 285 renameMap[i]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 286 287 // Put the renamed physical register back on the free list. 288 freeList->addReg(hb_it->newPhysReg); 289 290 // Be sure to mark its register as ready if it's a misc register. 291 if (hb_it->newPhysReg >= maxPhysicalRegs) { 292 scoreboard->setReg(hb_it->newPhysReg); 293 } 294 295 historyBuffer[i].erase(hb_it++); 296 } 297 insts[i].clear(); 298 skidBuffer[i].clear(); 299 } 300} 301 302template <class Impl> 303void 304DefaultRename<Impl>::takeOverFrom() 305{ 306 _status = Inactive; 307 initStage(); 308 309 // Reset all state prior to taking over from the other CPU. 310 for (int i=0; i< numThreads; i++) { 311 renameStatus[i] = Idle; 312 313 stalls[i].iew = false; 314 stalls[i].commit = false; 315 serializeInst[i] = NULL; 316 317 instsInProgress[i] = 0; 318 319 emptyROB[i] = true; 320 321 serializeOnNextInst[i] = false; 322 } 323} 324 325template <class Impl> 326void 327DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, unsigned tid) 328{ 329 DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid); 330 331 // Clear the stall signal if rename was blocked or unblocking before. 332 // If it still needs to block, the blocking should happen the next 333 // cycle and there should be space to hold everything due to the squash. 334 if (renameStatus[tid] == Blocked ||
| 48 numThreads(params->numberOfThreads), 49 maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs) 50{ 51 _status = Inactive; 52 53 for (int i=0; i< numThreads; i++) { 54 renameStatus[i] = Idle; 55 56 freeEntries[i].iqEntries = 0; 57 freeEntries[i].lsqEntries = 0; 58 freeEntries[i].robEntries = 0; 59 60 stalls[i].iew = false; 61 stalls[i].commit = false; 62 serializeInst[i] = NULL; 63 64 instsInProgress[i] = 0; 65 66 emptyROB[i] = true; 67 68 serializeOnNextInst[i] = false; 69 } 70 71 // @todo: Make into a parameter. 72 skidBufferMax = (2 * (iewToRenameDelay * params->decodeWidth)) + renameWidth; 73} 74 75template <class Impl> 76std::string 77DefaultRename<Impl>::name() const 78{ 79 return cpu->name() + ".rename"; 80} 81 82template <class Impl> 83void 84DefaultRename<Impl>::regStats() 85{ 86 renameSquashCycles 87 .name(name() + ".RENAME:SquashCycles") 88 .desc("Number of cycles rename is squashing") 89 .prereq(renameSquashCycles); 90 renameIdleCycles 91 .name(name() + ".RENAME:IdleCycles") 92 .desc("Number of cycles rename is idle") 93 .prereq(renameIdleCycles); 94 renameBlockCycles 95 .name(name() + ".RENAME:BlockCycles") 96 .desc("Number of cycles rename is blocking") 97 .prereq(renameBlockCycles); 98 renameSerializeStallCycles 99 .name(name() + ".RENAME:serializeStallCycles") 100 .desc("count of cycles rename stalled for serializing inst") 101 .flags(Stats::total); 102 renameRunCycles 103 .name(name() + ".RENAME:RunCycles") 104 .desc("Number of cycles rename is running") 105 .prereq(renameIdleCycles); 106 renameUnblockCycles 107 .name(name() + ".RENAME:UnblockCycles") 108 .desc("Number of cycles rename is unblocking") 109 .prereq(renameUnblockCycles); 110 renameRenamedInsts 111 .name(name() + ".RENAME:RenamedInsts") 112 .desc("Number of instructions processed by rename") 113 .prereq(renameRenamedInsts); 114 renameSquashedInsts 115 .name(name() + ".RENAME:SquashedInsts") 116 .desc("Number of squashed instructions processed by rename") 117 .prereq(renameSquashedInsts); 118 renameROBFullEvents 119 .name(name() + ".RENAME:ROBFullEvents") 120 .desc("Number of times rename has blocked due to ROB full") 121 .prereq(renameROBFullEvents); 122 renameIQFullEvents 123 .name(name() + ".RENAME:IQFullEvents") 124 .desc("Number of times rename has blocked due to IQ full") 125 .prereq(renameIQFullEvents); 126 renameLSQFullEvents 127 .name(name() + ".RENAME:LSQFullEvents") 128 .desc("Number of times rename has blocked due to LSQ full") 129 .prereq(renameLSQFullEvents); 130 renameFullRegistersEvents 131 .name(name() + ".RENAME:FullRegisterEvents") 132 .desc("Number of times there has been no free registers") 133 .prereq(renameFullRegistersEvents); 134 renameRenamedOperands 135 .name(name() + ".RENAME:RenamedOperands") 136 .desc("Number of destination operands rename has renamed") 137 .prereq(renameRenamedOperands); 138 renameRenameLookups 139 .name(name() + ".RENAME:RenameLookups") 140 .desc("Number of register rename lookups that rename has made") 141 .prereq(renameRenameLookups); 142 renameCommittedMaps 143 .name(name() + ".RENAME:CommittedMaps") 144 .desc("Number of HB maps that are committed") 145 .prereq(renameCommittedMaps); 146 renameUndoneMaps 147 .name(name() + ".RENAME:UndoneMaps") 148 .desc("Number of HB maps that are undone due to squashing") 149 .prereq(renameUndoneMaps); 150 renamedSerializing 151 .name(name() + ".RENAME:serializingInsts") 152 .desc("count of serializing insts renamed") 153 .flags(Stats::total) 154 ; 155 renamedTempSerializing 156 .name(name() + ".RENAME:tempSerializingInsts") 157 .desc("count of temporary serializing insts renamed") 158 .flags(Stats::total) 159 ; 160 renameSkidInsts 161 .name(name() + ".RENAME:skidInsts") 162 .desc("count of insts added to the skid buffer") 163 .flags(Stats::total) 164 ; 165} 166 167template <class Impl> 168void 169DefaultRename<Impl>::setCPU(O3CPU *cpu_ptr) 170{ 171 DPRINTF(Rename, "Setting CPU pointer.\n"); 172 cpu = cpu_ptr; 173} 174 175template <class Impl> 176void 177DefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 178{ 179 DPRINTF(Rename, "Setting time buffer pointer.\n"); 180 timeBuffer = tb_ptr; 181 182 // Setup wire to read information from time buffer, from IEW stage. 183 fromIEW = timeBuffer->getWire(-iewToRenameDelay); 184 185 // Setup wire to read infromation from time buffer, from commit stage. 186 fromCommit = timeBuffer->getWire(-commitToRenameDelay); 187 188 // Setup wire to write information to previous stages. 189 toDecode = timeBuffer->getWire(0); 190} 191 192template <class Impl> 193void 194DefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 195{ 196 DPRINTF(Rename, "Setting rename queue pointer.\n"); 197 renameQueue = rq_ptr; 198 199 // Setup wire to write information to future stages. 200 toIEW = renameQueue->getWire(0); 201} 202 203template <class Impl> 204void 205DefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 206{ 207 DPRINTF(Rename, "Setting decode queue pointer.\n"); 208 decodeQueue = dq_ptr; 209 210 // Setup wire to get information from decode. 211 fromDecode = decodeQueue->getWire(-decodeToRenameDelay); 212} 213 214template <class Impl> 215void 216DefaultRename<Impl>::initStage() 217{ 218 // Grab the number of free entries directly from the stages. 219 for (int tid=0; tid < numThreads; tid++) { 220 freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid); 221 freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid); 222 freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid); 223 emptyROB[tid] = true; 224 } 225} 226 227template<class Impl> 228void 229DefaultRename<Impl>::setActiveThreads(std::list<unsigned> *at_ptr) 230{ 231 DPRINTF(Rename, "Setting active threads list pointer.\n"); 232 activeThreads = at_ptr; 233} 234 235 236template <class Impl> 237void 238DefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[]) 239{ 240 DPRINTF(Rename, "Setting rename map pointers.\n"); 241 242 for (int i=0; i<numThreads; i++) { 243 renameMap[i] = &rm_ptr[i]; 244 } 245} 246 247template <class Impl> 248void 249DefaultRename<Impl>::setFreeList(FreeList *fl_ptr) 250{ 251 DPRINTF(Rename, "Setting free list pointer.\n"); 252 freeList = fl_ptr; 253} 254 255template<class Impl> 256void 257DefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard) 258{ 259 DPRINTF(Rename, "Setting scoreboard pointer.\n"); 260 scoreboard = _scoreboard; 261} 262 263template <class Impl> 264bool 265DefaultRename<Impl>::drain() 266{ 267 // Rename is ready to switch out at any time. 268 cpu->signalDrained(); 269 return true; 270} 271 272template <class Impl> 273void 274DefaultRename<Impl>::switchOut() 275{ 276 // Clear any state, fix up the rename map. 277 for (int i = 0; i < numThreads; i++) { 278 typename std::list<RenameHistory>::iterator hb_it = 279 historyBuffer[i].begin(); 280 281 while (!historyBuffer[i].empty()) { 282 assert(hb_it != historyBuffer[i].end()); 283 284 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 285 "number %i.\n", i, (*hb_it).instSeqNum); 286 287 // Tell the rename map to set the architected register to the 288 // previous physical register that it was renamed to. 289 renameMap[i]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 290 291 // Put the renamed physical register back on the free list. 292 freeList->addReg(hb_it->newPhysReg); 293 294 // Be sure to mark its register as ready if it's a misc register. 295 if (hb_it->newPhysReg >= maxPhysicalRegs) { 296 scoreboard->setReg(hb_it->newPhysReg); 297 } 298 299 historyBuffer[i].erase(hb_it++); 300 } 301 insts[i].clear(); 302 skidBuffer[i].clear(); 303 } 304} 305 306template <class Impl> 307void 308DefaultRename<Impl>::takeOverFrom() 309{ 310 _status = Inactive; 311 initStage(); 312 313 // Reset all state prior to taking over from the other CPU. 314 for (int i=0; i< numThreads; i++) { 315 renameStatus[i] = Idle; 316 317 stalls[i].iew = false; 318 stalls[i].commit = false; 319 serializeInst[i] = NULL; 320 321 instsInProgress[i] = 0; 322 323 emptyROB[i] = true; 324 325 serializeOnNextInst[i] = false; 326 } 327} 328 329template <class Impl> 330void 331DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, unsigned tid) 332{ 333 DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid); 334 335 // Clear the stall signal if rename was blocked or unblocking before. 336 // If it still needs to block, the blocking should happen the next 337 // cycle and there should be space to hold everything due to the squash. 338 if (renameStatus[tid] == Blocked ||
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335 renameStatus[tid] == Unblocking || 336 renameStatus[tid] == SerializeStall) { 337
| 339 renameStatus[tid] == Unblocking) {
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338 toDecode->renameUnblock[tid] = 1; 339
| 340 toDecode->renameUnblock[tid] = 1; 341
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| 342 resumeSerialize = false;
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340 serializeInst[tid] = NULL;
| 343 serializeInst[tid] = NULL;
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| 344 } else if (renameStatus[tid] == SerializeStall) { 345 if (serializeInst[tid]->seqNum <= squash_seq_num) { 346 DPRINTF(Rename, "Rename will resume serializing after squash\n"); 347 resumeSerialize = true; 348 assert(serializeInst[tid]); 349 } else { 350 resumeSerialize = false; 351 toDecode->renameUnblock[tid] = 1; 352 353 serializeInst[tid] = NULL; 354 }
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341 } 342 343 // Set the status to Squashing. 344 renameStatus[tid] = Squashing; 345 346 // Squash any instructions from decode. 347 unsigned squashCount = 0; 348 349 for (int i=0; i<fromDecode->size; i++) { 350 if (fromDecode->insts[i]->threadNumber == tid && 351 fromDecode->insts[i]->seqNum > squash_seq_num) { 352 fromDecode->insts[i]->setSquashed(); 353 wroteToTimeBuffer = true; 354 squashCount++; 355 } 356 357 } 358 359 // Clear the instruction list and skid buffer in case they have any 360 // insts in them. Since we support multiple ISAs, we cant just: 361 // "insts[tid].clear();" or "skidBuffer[tid].clear()" since there is 362 // a possible delay slot inst for different architectures 363 // insts[tid].clear(); 364#if ISA_HAS_DELAY_SLOT 365 DPRINTF(Rename, "[tid:%i] Squashing incoming decode instructions until " 366 "[sn:%i].\n",tid, squash_seq_num); 367 ListIt ilist_it = insts[tid].begin(); 368 while (ilist_it != insts[tid].end()) { 369 if ((*ilist_it)->seqNum > squash_seq_num) { 370 (*ilist_it)->setSquashed(); 371 DPRINTF(Rename, "Squashing incoming decode instruction, " 372 "[tid:%i] [sn:%i] PC %08p.\n", tid, (*ilist_it)->seqNum, (*ilist_it)->PC); 373 } 374 ilist_it++; 375 } 376#else 377 insts[tid].clear(); 378#endif 379 380 // Clear the skid buffer in case it has any data in it. 381 // See comments above. 382 // skidBuffer[tid].clear(); 383#if ISA_HAS_DELAY_SLOT 384 DPRINTF(Rename, "[tid:%i] Squashing incoming skidbuffer instructions " 385 "until [sn:%i].\n", tid, squash_seq_num); 386 ListIt slist_it = skidBuffer[tid].begin(); 387 while (slist_it != skidBuffer[tid].end()) { 388 if ((*slist_it)->seqNum > squash_seq_num) { 389 (*slist_it)->setSquashed(); 390 DPRINTF(Rename, "Squashing skidbuffer instruction, [tid:%i] [sn:%i]" 391 "PC %08p.\n", tid, (*slist_it)->seqNum, (*slist_it)->PC); 392 } 393 slist_it++; 394 }
| 355 } 356 357 // Set the status to Squashing. 358 renameStatus[tid] = Squashing; 359 360 // Squash any instructions from decode. 361 unsigned squashCount = 0; 362 363 for (int i=0; i<fromDecode->size; i++) { 364 if (fromDecode->insts[i]->threadNumber == tid && 365 fromDecode->insts[i]->seqNum > squash_seq_num) { 366 fromDecode->insts[i]->setSquashed(); 367 wroteToTimeBuffer = true; 368 squashCount++; 369 } 370 371 } 372 373 // Clear the instruction list and skid buffer in case they have any 374 // insts in them. Since we support multiple ISAs, we cant just: 375 // "insts[tid].clear();" or "skidBuffer[tid].clear()" since there is 376 // a possible delay slot inst for different architectures 377 // insts[tid].clear(); 378#if ISA_HAS_DELAY_SLOT 379 DPRINTF(Rename, "[tid:%i] Squashing incoming decode instructions until " 380 "[sn:%i].\n",tid, squash_seq_num); 381 ListIt ilist_it = insts[tid].begin(); 382 while (ilist_it != insts[tid].end()) { 383 if ((*ilist_it)->seqNum > squash_seq_num) { 384 (*ilist_it)->setSquashed(); 385 DPRINTF(Rename, "Squashing incoming decode instruction, " 386 "[tid:%i] [sn:%i] PC %08p.\n", tid, (*ilist_it)->seqNum, (*ilist_it)->PC); 387 } 388 ilist_it++; 389 } 390#else 391 insts[tid].clear(); 392#endif 393 394 // Clear the skid buffer in case it has any data in it. 395 // See comments above. 396 // skidBuffer[tid].clear(); 397#if ISA_HAS_DELAY_SLOT 398 DPRINTF(Rename, "[tid:%i] Squashing incoming skidbuffer instructions " 399 "until [sn:%i].\n", tid, squash_seq_num); 400 ListIt slist_it = skidBuffer[tid].begin(); 401 while (slist_it != skidBuffer[tid].end()) { 402 if ((*slist_it)->seqNum > squash_seq_num) { 403 (*slist_it)->setSquashed(); 404 DPRINTF(Rename, "Squashing skidbuffer instruction, [tid:%i] [sn:%i]" 405 "PC %08p.\n", tid, (*slist_it)->seqNum, (*slist_it)->PC); 406 } 407 slist_it++; 408 }
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| 409 resumeUnblocking = (skidBuffer[tid].size() != 0); 410 DPRINTF(Rename, "Resume unblocking set to %s\n", 411 resumeUnblocking ? "true" : "false");
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395#else 396 skidBuffer[tid].clear(); 397#endif 398 doSquash(squash_seq_num, tid); 399} 400 401template <class Impl> 402void 403DefaultRename<Impl>::tick() 404{ 405 wroteToTimeBuffer = false; 406 407 blockThisCycle = false; 408 409 bool status_change = false; 410 411 toIEWIndex = 0; 412 413 sortInsts(); 414 415 std::list<unsigned>::iterator threads = activeThreads->begin(); 416 std::list<unsigned>::iterator end = activeThreads->end(); 417 418 // Check stall and squash signals. 419 while (threads != end) { 420 unsigned tid = *threads++; 421 422 DPRINTF(Rename, "Processing [tid:%i]\n", tid); 423 424 status_change = checkSignalsAndUpdate(tid) || status_change; 425 426 rename(status_change, tid); 427 } 428 429 if (status_change) { 430 updateStatus(); 431 } 432 433 if (wroteToTimeBuffer) { 434 DPRINTF(Activity, "Activity this cycle.\n"); 435 cpu->activityThisCycle(); 436 } 437 438 threads = activeThreads->begin(); 439 440 while (threads != end) { 441 unsigned tid = *threads++; 442 443 // If we committed this cycle then doneSeqNum will be > 0 444 if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 445 !fromCommit->commitInfo[tid].squash && 446 renameStatus[tid] != Squashing) { 447 448 removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum, 449 tid); 450 } 451 } 452 453 // @todo: make into updateProgress function 454 for (int tid=0; tid < numThreads; tid++) { 455 instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched; 456 457 assert(instsInProgress[tid] >=0); 458 } 459 460} 461 462template<class Impl> 463void 464DefaultRename<Impl>::rename(bool &status_change, unsigned tid) 465{ 466 // If status is Running or idle, 467 // call renameInsts() 468 // If status is Unblocking, 469 // buffer any instructions coming from decode 470 // continue trying to empty skid buffer 471 // check if stall conditions have passed 472 473 if (renameStatus[tid] == Blocked) { 474 ++renameBlockCycles; 475 } else if (renameStatus[tid] == Squashing) { 476 ++renameSquashCycles; 477 } else if (renameStatus[tid] == SerializeStall) { 478 ++renameSerializeStallCycles;
| 412#else 413 skidBuffer[tid].clear(); 414#endif 415 doSquash(squash_seq_num, tid); 416} 417 418template <class Impl> 419void 420DefaultRename<Impl>::tick() 421{ 422 wroteToTimeBuffer = false; 423 424 blockThisCycle = false; 425 426 bool status_change = false; 427 428 toIEWIndex = 0; 429 430 sortInsts(); 431 432 std::list<unsigned>::iterator threads = activeThreads->begin(); 433 std::list<unsigned>::iterator end = activeThreads->end(); 434 435 // Check stall and squash signals. 436 while (threads != end) { 437 unsigned tid = *threads++; 438 439 DPRINTF(Rename, "Processing [tid:%i]\n", tid); 440 441 status_change = checkSignalsAndUpdate(tid) || status_change; 442 443 rename(status_change, tid); 444 } 445 446 if (status_change) { 447 updateStatus(); 448 } 449 450 if (wroteToTimeBuffer) { 451 DPRINTF(Activity, "Activity this cycle.\n"); 452 cpu->activityThisCycle(); 453 } 454 455 threads = activeThreads->begin(); 456 457 while (threads != end) { 458 unsigned tid = *threads++; 459 460 // If we committed this cycle then doneSeqNum will be > 0 461 if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 462 !fromCommit->commitInfo[tid].squash && 463 renameStatus[tid] != Squashing) { 464 465 removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum, 466 tid); 467 } 468 } 469 470 // @todo: make into updateProgress function 471 for (int tid=0; tid < numThreads; tid++) { 472 instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched; 473 474 assert(instsInProgress[tid] >=0); 475 } 476 477} 478 479template<class Impl> 480void 481DefaultRename<Impl>::rename(bool &status_change, unsigned tid) 482{ 483 // If status is Running or idle, 484 // call renameInsts() 485 // If status is Unblocking, 486 // buffer any instructions coming from decode 487 // continue trying to empty skid buffer 488 // check if stall conditions have passed 489 490 if (renameStatus[tid] == Blocked) { 491 ++renameBlockCycles; 492 } else if (renameStatus[tid] == Squashing) { 493 ++renameSquashCycles; 494 } else if (renameStatus[tid] == SerializeStall) { 495 ++renameSerializeStallCycles;
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| 496 // If we are currently in SerializeStall and resumeSerialize 497 // was set, then that means that we are resuming serializing 498 // this cycle. Tell the previous stages to block. 499 if (resumeSerialize) { 500 resumeSerialize = false; 501 block(tid); 502 toDecode->renameUnblock[tid] = false; 503 } 504 } else if (renameStatus[tid] == Unblocking) { 505 if (resumeUnblocking) { 506 block(tid); 507 resumeUnblocking = false; 508 toDecode->renameUnblock[tid] = false; 509 }
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479 } 480 481 if (renameStatus[tid] == Running || 482 renameStatus[tid] == Idle) { 483 DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run " 484 "stage.\n", tid); 485 486 renameInsts(tid); 487 } else if (renameStatus[tid] == Unblocking) { 488 renameInsts(tid); 489 490 if (validInsts()) { 491 // Add the current inputs to the skid buffer so they can be 492 // reprocessed when this stage unblocks. 493 skidInsert(tid); 494 } 495 496 // If we switched over to blocking, then there's a potential for 497 // an overall status change. 498 status_change = unblock(tid) || status_change || blockThisCycle; 499 } 500} 501 502template <class Impl> 503void 504DefaultRename<Impl>::renameInsts(unsigned tid) 505{ 506 // Instructions can be either in the skid buffer or the queue of 507 // instructions coming from decode, depending on the status. 508 int insts_available = renameStatus[tid] == Unblocking ? 509 skidBuffer[tid].size() : insts[tid].size(); 510 511 // Check the decode queue to see if instructions are available. 512 // If there are no available instructions to rename, then do nothing. 513 if (insts_available == 0) { 514 DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n", 515 tid); 516 // Should I change status to idle? 517 ++renameIdleCycles; 518 return; 519 } else if (renameStatus[tid] == Unblocking) { 520 ++renameUnblockCycles; 521 } else if (renameStatus[tid] == Running) { 522 ++renameRunCycles; 523 } 524 525 DynInstPtr inst; 526 527 // Will have to do a different calculation for the number of free 528 // entries. 529 int free_rob_entries = calcFreeROBEntries(tid); 530 int free_iq_entries = calcFreeIQEntries(tid); 531 int free_lsq_entries = calcFreeLSQEntries(tid); 532 int min_free_entries = free_rob_entries; 533 534 FullSource source = ROB; 535 536 if (free_iq_entries < min_free_entries) { 537 min_free_entries = free_iq_entries; 538 source = IQ; 539 } 540 541 if (free_lsq_entries < min_free_entries) { 542 min_free_entries = free_lsq_entries; 543 source = LSQ; 544 } 545 546 // Check if there's any space left. 547 if (min_free_entries <= 0) { 548 DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ " 549 "entries.\n" 550 "ROB has %i free entries.\n" 551 "IQ has %i free entries.\n" 552 "LSQ has %i free entries.\n", 553 tid, 554 free_rob_entries, 555 free_iq_entries, 556 free_lsq_entries); 557 558 blockThisCycle = true; 559 560 block(tid); 561 562 incrFullStat(source); 563 564 return; 565 } else if (min_free_entries < insts_available) { 566 DPRINTF(Rename, "[tid:%u]: Will have to block this cycle." 567 "%i insts available, but only %i insts can be " 568 "renamed due to ROB/IQ/LSQ limits.\n", 569 tid, insts_available, min_free_entries); 570 571 insts_available = min_free_entries; 572 573 blockThisCycle = true; 574 575 incrFullStat(source); 576 } 577 578 InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ? 579 skidBuffer[tid] : insts[tid]; 580 581 DPRINTF(Rename, "[tid:%u]: %i available instructions to " 582 "send iew.\n", tid, insts_available); 583 584 DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts " 585 "dispatched to IQ last cycle.\n", 586 tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched); 587 588 // Handle serializing the next instruction if necessary. 589 if (serializeOnNextInst[tid]) { 590 if (emptyROB[tid] && instsInProgress[tid] == 0) { 591 // ROB already empty; no need to serialize. 592 serializeOnNextInst[tid] = false; 593 } else if (!insts_to_rename.empty()) { 594 insts_to_rename.front()->setSerializeBefore(); 595 } 596 } 597 598 int renamed_insts = 0; 599 600 while (insts_available > 0 && toIEWIndex < renameWidth) { 601 DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid); 602 603 assert(!insts_to_rename.empty()); 604 605 inst = insts_to_rename.front(); 606 607 insts_to_rename.pop_front(); 608 609 if (renameStatus[tid] == Unblocking) { 610 DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%#x from rename " 611 "skidBuffer\n", 612 tid, inst->seqNum, inst->readPC()); 613 } 614 615 if (inst->isSquashed()) { 616 DPRINTF(Rename, "[tid:%u]: instruction %i with PC %#x is " 617 "squashed, skipping.\n", 618 tid, inst->seqNum, inst->readPC()); 619 620 ++renameSquashedInsts; 621 622 // Decrement how many instructions are available. 623 --insts_available; 624 625 continue; 626 } 627 628 DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with " 629 "PC %#x.\n", 630 tid, inst->seqNum, inst->readPC()); 631 632 // Handle serializeAfter/serializeBefore instructions. 633 // serializeAfter marks the next instruction as serializeBefore. 634 // serializeBefore makes the instruction wait in rename until the ROB 635 // is empty. 636 637 // In this model, IPR accesses are serialize before 638 // instructions, and store conditionals are serialize after 639 // instructions. This is mainly due to lack of support for 640 // out-of-order operations of either of those classes of 641 // instructions. 642 if ((inst->isIprAccess() || inst->isSerializeBefore()) && 643 !inst->isSerializeHandled()) { 644 DPRINTF(Rename, "Serialize before instruction encountered.\n"); 645 646 if (!inst->isTempSerializeBefore()) { 647 renamedSerializing++; 648 inst->setSerializeHandled(); 649 } else { 650 renamedTempSerializing++; 651 } 652 653 // Change status over to SerializeStall so that other stages know 654 // what this is blocked on. 655 renameStatus[tid] = SerializeStall; 656 657 serializeInst[tid] = inst; 658 659 blockThisCycle = true; 660 661 break; 662 } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) && 663 !inst->isSerializeHandled()) { 664 DPRINTF(Rename, "Serialize after instruction encountered.\n"); 665 666 renamedSerializing++; 667 668 inst->setSerializeHandled(); 669 670 serializeAfter(insts_to_rename, tid); 671 } 672 673 // Check here to make sure there are enough destination registers 674 // to rename to. Otherwise block. 675 if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) { 676 DPRINTF(Rename, "Blocking due to lack of free " 677 "physical registers to rename to.\n"); 678 blockThisCycle = true; 679 680 ++renameFullRegistersEvents; 681 682 break; 683 } 684 685 renameSrcRegs(inst, inst->threadNumber); 686 687 renameDestRegs(inst, inst->threadNumber); 688 689 ++renamed_insts; 690 691 // Put instruction in rename queue. 692 toIEW->insts[toIEWIndex] = inst; 693 ++(toIEW->size); 694 695 // Increment which instruction we're on. 696 ++toIEWIndex; 697 698 // Decrement how many instructions are available. 699 --insts_available; 700 } 701 702 instsInProgress[tid] += renamed_insts; 703 renameRenamedInsts += renamed_insts; 704 705 // If we wrote to the time buffer, record this. 706 if (toIEWIndex) { 707 wroteToTimeBuffer = true; 708 } 709 710 // Check if there's any instructions left that haven't yet been renamed. 711 // If so then block. 712 if (insts_available) { 713 blockThisCycle = true; 714 } 715 716 if (blockThisCycle) { 717 block(tid); 718 toDecode->renameUnblock[tid] = false; 719 } 720} 721 722template<class Impl> 723void 724DefaultRename<Impl>::skidInsert(unsigned tid) 725{ 726 DynInstPtr inst = NULL; 727 728 while (!insts[tid].empty()) { 729 inst = insts[tid].front(); 730 731 insts[tid].pop_front(); 732 733 assert(tid == inst->threadNumber); 734 735 DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC:%#x into Rename " 736 "skidBuffer\n", tid, inst->seqNum, inst->readPC()); 737 738 ++renameSkidInsts; 739 740 skidBuffer[tid].push_back(inst); 741 } 742 743 if (skidBuffer[tid].size() > skidBufferMax)
| 510 } 511 512 if (renameStatus[tid] == Running || 513 renameStatus[tid] == Idle) { 514 DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run " 515 "stage.\n", tid); 516 517 renameInsts(tid); 518 } else if (renameStatus[tid] == Unblocking) { 519 renameInsts(tid); 520 521 if (validInsts()) { 522 // Add the current inputs to the skid buffer so they can be 523 // reprocessed when this stage unblocks. 524 skidInsert(tid); 525 } 526 527 // If we switched over to blocking, then there's a potential for 528 // an overall status change. 529 status_change = unblock(tid) || status_change || blockThisCycle; 530 } 531} 532 533template <class Impl> 534void 535DefaultRename<Impl>::renameInsts(unsigned tid) 536{ 537 // Instructions can be either in the skid buffer or the queue of 538 // instructions coming from decode, depending on the status. 539 int insts_available = renameStatus[tid] == Unblocking ? 540 skidBuffer[tid].size() : insts[tid].size(); 541 542 // Check the decode queue to see if instructions are available. 543 // If there are no available instructions to rename, then do nothing. 544 if (insts_available == 0) { 545 DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n", 546 tid); 547 // Should I change status to idle? 548 ++renameIdleCycles; 549 return; 550 } else if (renameStatus[tid] == Unblocking) { 551 ++renameUnblockCycles; 552 } else if (renameStatus[tid] == Running) { 553 ++renameRunCycles; 554 } 555 556 DynInstPtr inst; 557 558 // Will have to do a different calculation for the number of free 559 // entries. 560 int free_rob_entries = calcFreeROBEntries(tid); 561 int free_iq_entries = calcFreeIQEntries(tid); 562 int free_lsq_entries = calcFreeLSQEntries(tid); 563 int min_free_entries = free_rob_entries; 564 565 FullSource source = ROB; 566 567 if (free_iq_entries < min_free_entries) { 568 min_free_entries = free_iq_entries; 569 source = IQ; 570 } 571 572 if (free_lsq_entries < min_free_entries) { 573 min_free_entries = free_lsq_entries; 574 source = LSQ; 575 } 576 577 // Check if there's any space left. 578 if (min_free_entries <= 0) { 579 DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ " 580 "entries.\n" 581 "ROB has %i free entries.\n" 582 "IQ has %i free entries.\n" 583 "LSQ has %i free entries.\n", 584 tid, 585 free_rob_entries, 586 free_iq_entries, 587 free_lsq_entries); 588 589 blockThisCycle = true; 590 591 block(tid); 592 593 incrFullStat(source); 594 595 return; 596 } else if (min_free_entries < insts_available) { 597 DPRINTF(Rename, "[tid:%u]: Will have to block this cycle." 598 "%i insts available, but only %i insts can be " 599 "renamed due to ROB/IQ/LSQ limits.\n", 600 tid, insts_available, min_free_entries); 601 602 insts_available = min_free_entries; 603 604 blockThisCycle = true; 605 606 incrFullStat(source); 607 } 608 609 InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ? 610 skidBuffer[tid] : insts[tid]; 611 612 DPRINTF(Rename, "[tid:%u]: %i available instructions to " 613 "send iew.\n", tid, insts_available); 614 615 DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts " 616 "dispatched to IQ last cycle.\n", 617 tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched); 618 619 // Handle serializing the next instruction if necessary. 620 if (serializeOnNextInst[tid]) { 621 if (emptyROB[tid] && instsInProgress[tid] == 0) { 622 // ROB already empty; no need to serialize. 623 serializeOnNextInst[tid] = false; 624 } else if (!insts_to_rename.empty()) { 625 insts_to_rename.front()->setSerializeBefore(); 626 } 627 } 628 629 int renamed_insts = 0; 630 631 while (insts_available > 0 && toIEWIndex < renameWidth) { 632 DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid); 633 634 assert(!insts_to_rename.empty()); 635 636 inst = insts_to_rename.front(); 637 638 insts_to_rename.pop_front(); 639 640 if (renameStatus[tid] == Unblocking) { 641 DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%#x from rename " 642 "skidBuffer\n", 643 tid, inst->seqNum, inst->readPC()); 644 } 645 646 if (inst->isSquashed()) { 647 DPRINTF(Rename, "[tid:%u]: instruction %i with PC %#x is " 648 "squashed, skipping.\n", 649 tid, inst->seqNum, inst->readPC()); 650 651 ++renameSquashedInsts; 652 653 // Decrement how many instructions are available. 654 --insts_available; 655 656 continue; 657 } 658 659 DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with " 660 "PC %#x.\n", 661 tid, inst->seqNum, inst->readPC()); 662 663 // Handle serializeAfter/serializeBefore instructions. 664 // serializeAfter marks the next instruction as serializeBefore. 665 // serializeBefore makes the instruction wait in rename until the ROB 666 // is empty. 667 668 // In this model, IPR accesses are serialize before 669 // instructions, and store conditionals are serialize after 670 // instructions. This is mainly due to lack of support for 671 // out-of-order operations of either of those classes of 672 // instructions. 673 if ((inst->isIprAccess() || inst->isSerializeBefore()) && 674 !inst->isSerializeHandled()) { 675 DPRINTF(Rename, "Serialize before instruction encountered.\n"); 676 677 if (!inst->isTempSerializeBefore()) { 678 renamedSerializing++; 679 inst->setSerializeHandled(); 680 } else { 681 renamedTempSerializing++; 682 } 683 684 // Change status over to SerializeStall so that other stages know 685 // what this is blocked on. 686 renameStatus[tid] = SerializeStall; 687 688 serializeInst[tid] = inst; 689 690 blockThisCycle = true; 691 692 break; 693 } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) && 694 !inst->isSerializeHandled()) { 695 DPRINTF(Rename, "Serialize after instruction encountered.\n"); 696 697 renamedSerializing++; 698 699 inst->setSerializeHandled(); 700 701 serializeAfter(insts_to_rename, tid); 702 } 703 704 // Check here to make sure there are enough destination registers 705 // to rename to. Otherwise block. 706 if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) { 707 DPRINTF(Rename, "Blocking due to lack of free " 708 "physical registers to rename to.\n"); 709 blockThisCycle = true; 710 711 ++renameFullRegistersEvents; 712 713 break; 714 } 715 716 renameSrcRegs(inst, inst->threadNumber); 717 718 renameDestRegs(inst, inst->threadNumber); 719 720 ++renamed_insts; 721 722 // Put instruction in rename queue. 723 toIEW->insts[toIEWIndex] = inst; 724 ++(toIEW->size); 725 726 // Increment which instruction we're on. 727 ++toIEWIndex; 728 729 // Decrement how many instructions are available. 730 --insts_available; 731 } 732 733 instsInProgress[tid] += renamed_insts; 734 renameRenamedInsts += renamed_insts; 735 736 // If we wrote to the time buffer, record this. 737 if (toIEWIndex) { 738 wroteToTimeBuffer = true; 739 } 740 741 // Check if there's any instructions left that haven't yet been renamed. 742 // If so then block. 743 if (insts_available) { 744 blockThisCycle = true; 745 } 746 747 if (blockThisCycle) { 748 block(tid); 749 toDecode->renameUnblock[tid] = false; 750 } 751} 752 753template<class Impl> 754void 755DefaultRename<Impl>::skidInsert(unsigned tid) 756{ 757 DynInstPtr inst = NULL; 758 759 while (!insts[tid].empty()) { 760 inst = insts[tid].front(); 761 762 insts[tid].pop_front(); 763 764 assert(tid == inst->threadNumber); 765 766 DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC:%#x into Rename " 767 "skidBuffer\n", tid, inst->seqNum, inst->readPC()); 768 769 ++renameSkidInsts; 770 771 skidBuffer[tid].push_back(inst); 772 } 773 774 if (skidBuffer[tid].size() > skidBufferMax)
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| 775 { 776 typename InstQueue::iterator it; 777 warn("Skidbuffer contents:\n"); 778 for(it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++) 779 { 780 warn("[tid:%u]: %s [sn:%i].\n", tid, 781 (*it)->staticInst->disassemble(inst->readPC()), 782 (*it)->seqNum); 783 }
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744 panic("Skidbuffer Exceeded Max Size");
| 784 panic("Skidbuffer Exceeded Max Size");
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| 785 }
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745} 746 747template <class Impl> 748void 749DefaultRename<Impl>::sortInsts() 750{ 751 int insts_from_decode = fromDecode->size; 752#ifdef DEBUG 753#if !ISA_HAS_DELAY_SLOT 754 for (int i=0; i < numThreads; i++) 755 assert(insts[i].empty()); 756#endif 757#endif 758 for (int i = 0; i < insts_from_decode; ++i) { 759 DynInstPtr inst = fromDecode->insts[i]; 760 insts[inst->threadNumber].push_back(inst); 761 } 762} 763 764template<class Impl> 765bool 766DefaultRename<Impl>::skidsEmpty() 767{ 768 std::list<unsigned>::iterator threads = activeThreads->begin(); 769 std::list<unsigned>::iterator end = activeThreads->end(); 770 771 while (threads != end) { 772 unsigned tid = *threads++; 773 774 if (!skidBuffer[tid].empty()) 775 return false; 776 } 777 778 return true; 779} 780 781template<class Impl> 782void 783DefaultRename<Impl>::updateStatus() 784{ 785 bool any_unblocking = false; 786 787 std::list<unsigned>::iterator threads = activeThreads->begin(); 788 std::list<unsigned>::iterator end = activeThreads->end(); 789 790 while (threads != end) { 791 unsigned tid = *threads++; 792 793 if (renameStatus[tid] == Unblocking) { 794 any_unblocking = true; 795 break; 796 } 797 } 798 799 // Rename will have activity if it's unblocking. 800 if (any_unblocking) { 801 if (_status == Inactive) { 802 _status = Active; 803 804 DPRINTF(Activity, "Activating stage.\n"); 805 806 cpu->activateStage(O3CPU::RenameIdx); 807 } 808 } else { 809 // If it's not unblocking, then rename will not have any internal 810 // activity. Switch it to inactive. 811 if (_status == Active) { 812 _status = Inactive; 813 DPRINTF(Activity, "Deactivating stage.\n"); 814 815 cpu->deactivateStage(O3CPU::RenameIdx); 816 } 817 } 818} 819 820template <class Impl> 821bool 822DefaultRename<Impl>::block(unsigned tid) 823{ 824 DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid); 825 826 // Add the current inputs onto the skid buffer, so they can be 827 // reprocessed when this stage unblocks. 828 skidInsert(tid); 829 830 // Only signal backwards to block if the previous stages do not think 831 // rename is already blocked. 832 if (renameStatus[tid] != Blocked) {
| 786} 787 788template <class Impl> 789void 790DefaultRename<Impl>::sortInsts() 791{ 792 int insts_from_decode = fromDecode->size; 793#ifdef DEBUG 794#if !ISA_HAS_DELAY_SLOT 795 for (int i=0; i < numThreads; i++) 796 assert(insts[i].empty()); 797#endif 798#endif 799 for (int i = 0; i < insts_from_decode; ++i) { 800 DynInstPtr inst = fromDecode->insts[i]; 801 insts[inst->threadNumber].push_back(inst); 802 } 803} 804 805template<class Impl> 806bool 807DefaultRename<Impl>::skidsEmpty() 808{ 809 std::list<unsigned>::iterator threads = activeThreads->begin(); 810 std::list<unsigned>::iterator end = activeThreads->end(); 811 812 while (threads != end) { 813 unsigned tid = *threads++; 814 815 if (!skidBuffer[tid].empty()) 816 return false; 817 } 818 819 return true; 820} 821 822template<class Impl> 823void 824DefaultRename<Impl>::updateStatus() 825{ 826 bool any_unblocking = false; 827 828 std::list<unsigned>::iterator threads = activeThreads->begin(); 829 std::list<unsigned>::iterator end = activeThreads->end(); 830 831 while (threads != end) { 832 unsigned tid = *threads++; 833 834 if (renameStatus[tid] == Unblocking) { 835 any_unblocking = true; 836 break; 837 } 838 } 839 840 // Rename will have activity if it's unblocking. 841 if (any_unblocking) { 842 if (_status == Inactive) { 843 _status = Active; 844 845 DPRINTF(Activity, "Activating stage.\n"); 846 847 cpu->activateStage(O3CPU::RenameIdx); 848 } 849 } else { 850 // If it's not unblocking, then rename will not have any internal 851 // activity. Switch it to inactive. 852 if (_status == Active) { 853 _status = Inactive; 854 DPRINTF(Activity, "Deactivating stage.\n"); 855 856 cpu->deactivateStage(O3CPU::RenameIdx); 857 } 858 } 859} 860 861template <class Impl> 862bool 863DefaultRename<Impl>::block(unsigned tid) 864{ 865 DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid); 866 867 // Add the current inputs onto the skid buffer, so they can be 868 // reprocessed when this stage unblocks. 869 skidInsert(tid); 870 871 // Only signal backwards to block if the previous stages do not think 872 // rename is already blocked. 873 if (renameStatus[tid] != Blocked) {
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833 if (renameStatus[tid] != Unblocking) {
| 874 // If resumeUnblocking is set, we unblocked during the squash, 875 // but now we're have unblocking status. We need to tell earlier 876 // stages to block. 877 if (resumeUnblocking || renameStatus[tid] != Unblocking) {
|
834 toDecode->renameBlock[tid] = true; 835 toDecode->renameUnblock[tid] = false; 836 wroteToTimeBuffer = true; 837 } 838 839 // Rename can not go from SerializeStall to Blocked, otherwise 840 // it would not know to complete the serialize stall. 841 if (renameStatus[tid] != SerializeStall) { 842 // Set status to Blocked. 843 renameStatus[tid] = Blocked; 844 return true; 845 } 846 } 847 848 return false; 849} 850 851template <class Impl> 852bool 853DefaultRename<Impl>::unblock(unsigned tid) 854{ 855 DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid); 856 857 // Rename is done unblocking if the skid buffer is empty. 858 if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) { 859 860 DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid); 861 862 toDecode->renameUnblock[tid] = true; 863 wroteToTimeBuffer = true; 864 865 renameStatus[tid] = Running; 866 return true; 867 } 868 869 return false; 870} 871 872template <class Impl> 873void 874DefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, unsigned tid) 875{ 876 typename std::list<RenameHistory>::iterator hb_it = 877 historyBuffer[tid].begin(); 878 879 // After a syscall squashes everything, the history buffer may be empty 880 // but the ROB may still be squashing instructions. 881 if (historyBuffer[tid].empty()) { 882 return; 883 } 884 885 // Go through the most recent instructions, undoing the mappings 886 // they did and freeing up the registers. 887 while (!historyBuffer[tid].empty() && 888 (*hb_it).instSeqNum > squashed_seq_num) { 889 assert(hb_it != historyBuffer[tid].end()); 890 891 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 892 "number %i.\n", tid, (*hb_it).instSeqNum); 893 894 // Tell the rename map to set the architected register to the 895 // previous physical register that it was renamed to. 896 renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 897 898 // Put the renamed physical register back on the free list. 899 freeList->addReg(hb_it->newPhysReg); 900 901 // Be sure to mark its register as ready if it's a misc register. 902 if (hb_it->newPhysReg >= maxPhysicalRegs) { 903 scoreboard->setReg(hb_it->newPhysReg); 904 } 905 906 historyBuffer[tid].erase(hb_it++); 907 908 ++renameUndoneMaps; 909 } 910} 911 912template<class Impl> 913void 914DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, unsigned tid) 915{ 916 DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the " 917 "history buffer %u (size=%i), until [sn:%lli].\n", 918 tid, tid, historyBuffer[tid].size(), inst_seq_num); 919 920 typename std::list<RenameHistory>::iterator hb_it = 921 historyBuffer[tid].end(); 922 923 --hb_it; 924 925 if (historyBuffer[tid].empty()) { 926 DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid); 927 return; 928 } else if (hb_it->instSeqNum > inst_seq_num) { 929 DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure " 930 "that a syscall happened recently.\n", tid); 931 return; 932 } 933 934 // Commit all the renames up until (and including) the committed sequence 935 // number. Some or even all of the committed instructions may not have 936 // rename histories if they did not have destination registers that were 937 // renamed. 938 while (!historyBuffer[tid].empty() && 939 hb_it != historyBuffer[tid].end() && 940 (*hb_it).instSeqNum <= inst_seq_num) { 941 942 DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, " 943 "[sn:%lli].\n", 944 tid, (*hb_it).prevPhysReg, (*hb_it).instSeqNum); 945 946 freeList->addReg((*hb_it).prevPhysReg); 947 ++renameCommittedMaps; 948 949 historyBuffer[tid].erase(hb_it--); 950 } 951} 952 953template <class Impl> 954inline void 955DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst,unsigned tid) 956{ 957 assert(renameMap[tid] != 0); 958 959 unsigned num_src_regs = inst->numSrcRegs(); 960 961 // Get the architectual register numbers from the source and 962 // destination operands, and redirect them to the right register. 963 // Will need to mark dependencies though. 964 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) { 965 RegIndex src_reg = inst->srcRegIdx(src_idx);
| 878 toDecode->renameBlock[tid] = true; 879 toDecode->renameUnblock[tid] = false; 880 wroteToTimeBuffer = true; 881 } 882 883 // Rename can not go from SerializeStall to Blocked, otherwise 884 // it would not know to complete the serialize stall. 885 if (renameStatus[tid] != SerializeStall) { 886 // Set status to Blocked. 887 renameStatus[tid] = Blocked; 888 return true; 889 } 890 } 891 892 return false; 893} 894 895template <class Impl> 896bool 897DefaultRename<Impl>::unblock(unsigned tid) 898{ 899 DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid); 900 901 // Rename is done unblocking if the skid buffer is empty. 902 if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) { 903 904 DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid); 905 906 toDecode->renameUnblock[tid] = true; 907 wroteToTimeBuffer = true; 908 909 renameStatus[tid] = Running; 910 return true; 911 } 912 913 return false; 914} 915 916template <class Impl> 917void 918DefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, unsigned tid) 919{ 920 typename std::list<RenameHistory>::iterator hb_it = 921 historyBuffer[tid].begin(); 922 923 // After a syscall squashes everything, the history buffer may be empty 924 // but the ROB may still be squashing instructions. 925 if (historyBuffer[tid].empty()) { 926 return; 927 } 928 929 // Go through the most recent instructions, undoing the mappings 930 // they did and freeing up the registers. 931 while (!historyBuffer[tid].empty() && 932 (*hb_it).instSeqNum > squashed_seq_num) { 933 assert(hb_it != historyBuffer[tid].end()); 934 935 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 936 "number %i.\n", tid, (*hb_it).instSeqNum); 937 938 // Tell the rename map to set the architected register to the 939 // previous physical register that it was renamed to. 940 renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 941 942 // Put the renamed physical register back on the free list. 943 freeList->addReg(hb_it->newPhysReg); 944 945 // Be sure to mark its register as ready if it's a misc register. 946 if (hb_it->newPhysReg >= maxPhysicalRegs) { 947 scoreboard->setReg(hb_it->newPhysReg); 948 } 949 950 historyBuffer[tid].erase(hb_it++); 951 952 ++renameUndoneMaps; 953 } 954} 955 956template<class Impl> 957void 958DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, unsigned tid) 959{ 960 DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the " 961 "history buffer %u (size=%i), until [sn:%lli].\n", 962 tid, tid, historyBuffer[tid].size(), inst_seq_num); 963 964 typename std::list<RenameHistory>::iterator hb_it = 965 historyBuffer[tid].end(); 966 967 --hb_it; 968 969 if (historyBuffer[tid].empty()) { 970 DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid); 971 return; 972 } else if (hb_it->instSeqNum > inst_seq_num) { 973 DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure " 974 "that a syscall happened recently.\n", tid); 975 return; 976 } 977 978 // Commit all the renames up until (and including) the committed sequence 979 // number. Some or even all of the committed instructions may not have 980 // rename histories if they did not have destination registers that were 981 // renamed. 982 while (!historyBuffer[tid].empty() && 983 hb_it != historyBuffer[tid].end() && 984 (*hb_it).instSeqNum <= inst_seq_num) { 985 986 DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, " 987 "[sn:%lli].\n", 988 tid, (*hb_it).prevPhysReg, (*hb_it).instSeqNum); 989 990 freeList->addReg((*hb_it).prevPhysReg); 991 ++renameCommittedMaps; 992 993 historyBuffer[tid].erase(hb_it--); 994 } 995} 996 997template <class Impl> 998inline void 999DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst,unsigned tid) 1000{ 1001 assert(renameMap[tid] != 0); 1002 1003 unsigned num_src_regs = inst->numSrcRegs(); 1004 1005 // Get the architectual register numbers from the source and 1006 // destination operands, and redirect them to the right register. 1007 // Will need to mark dependencies though. 1008 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) { 1009 RegIndex src_reg = inst->srcRegIdx(src_idx);
|
| 1010 RegIndex flat_src_reg = src_reg; 1011 if (src_reg < TheISA::FP_Base_DepTag) { 1012 flat_src_reg = TheISA::flattenIntIndex(inst->tcBase(), src_reg); 1013 DPRINTF(Rename, "Flattening index %d to %d.\n", (int)src_reg, (int)flat_src_reg); 1014 } 1015 inst->flattenSrcReg(src_idx, flat_src_reg);
|
966 967 // Look up the source registers to get the phys. register they've 968 // been renamed to, and set the sources to those registers.
| 1016 1017 // Look up the source registers to get the phys. register they've 1018 // been renamed to, and set the sources to those registers.
|
969 PhysRegIndex renamed_reg = renameMap[tid]->lookup(src_reg);
| 1019 PhysRegIndex renamed_reg = renameMap[tid]->lookup(flat_src_reg);
|
970 971 DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got "
| 1020 1021 DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got "
|
972 "physical reg %i.\n", tid, (int)src_reg,
| 1022 "physical reg %i.\n", tid, (int)flat_src_reg,
|
973 (int)renamed_reg); 974 975 inst->renameSrcReg(src_idx, renamed_reg); 976 977 // See if the register is ready or not. 978 if (scoreboard->getReg(renamed_reg) == true) { 979 DPRINTF(Rename, "[tid:%u]: Register is ready.\n", tid); 980 981 inst->markSrcRegReady(src_idx); 982 } 983 984 ++renameRenameLookups; 985 } 986} 987 988template <class Impl> 989inline void 990DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst,unsigned tid) 991{ 992 typename RenameMap::RenameInfo rename_result; 993 994 unsigned num_dest_regs = inst->numDestRegs(); 995 996 // Rename the destination registers. 997 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) { 998 RegIndex dest_reg = inst->destRegIdx(dest_idx);
| 1023 (int)renamed_reg); 1024 1025 inst->renameSrcReg(src_idx, renamed_reg); 1026 1027 // See if the register is ready or not. 1028 if (scoreboard->getReg(renamed_reg) == true) { 1029 DPRINTF(Rename, "[tid:%u]: Register is ready.\n", tid); 1030 1031 inst->markSrcRegReady(src_idx); 1032 } 1033 1034 ++renameRenameLookups; 1035 } 1036} 1037 1038template <class Impl> 1039inline void 1040DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst,unsigned tid) 1041{ 1042 typename RenameMap::RenameInfo rename_result; 1043 1044 unsigned num_dest_regs = inst->numDestRegs(); 1045 1046 // Rename the destination registers. 1047 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) { 1048 RegIndex dest_reg = inst->destRegIdx(dest_idx);
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| 1049 RegIndex flat_dest_reg = dest_reg; 1050 if (dest_reg < TheISA::FP_Base_DepTag) { 1051 flat_dest_reg = TheISA::flattenIntIndex(inst->tcBase(), dest_reg); 1052 DPRINTF(Rename, "Flattening index %d to %d.\n", (int)dest_reg, (int)flat_dest_reg); 1053 }
|
999
| 1054
|
| 1055 inst->flattenDestReg(dest_idx, flat_dest_reg); 1056
|
1000 // Get the physical register that the destination will be 1001 // renamed to.
| 1057 // Get the physical register that the destination will be 1058 // renamed to.
|
1002 rename_result = renameMap[tid]->rename(dest_reg);
| 1059 rename_result = renameMap[tid]->rename(flat_dest_reg);
|
1003 1004 //Mark Scoreboard entry as not ready 1005 scoreboard->unsetReg(rename_result.first); 1006 1007 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical "
| 1060 1061 //Mark Scoreboard entry as not ready 1062 scoreboard->unsetReg(rename_result.first); 1063 1064 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical "
|
1008 "reg %i.\n", tid, (int)dest_reg,
| 1065 "reg %i.\n", tid, (int)flat_dest_reg,
|
1009 (int)rename_result.first); 1010 1011 // Record the rename information so that a history can be kept.
| 1066 (int)rename_result.first); 1067 1068 // Record the rename information so that a history can be kept.
|
1012 RenameHistory hb_entry(inst->seqNum, dest_reg,
| 1069 RenameHistory hb_entry(inst->seqNum, flat_dest_reg,
|
1013 rename_result.first, 1014 rename_result.second); 1015 1016 historyBuffer[tid].push_front(hb_entry); 1017 1018 DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer " 1019 "(size=%i), [sn:%lli].\n",tid, 1020 historyBuffer[tid].size(), 1021 (*historyBuffer[tid].begin()).instSeqNum); 1022 1023 // Tell the instruction to rename the appropriate destination 1024 // register (dest_idx) to the new physical register 1025 // (rename_result.first), and record the previous physical 1026 // register that the same logical register was renamed to 1027 // (rename_result.second). 1028 inst->renameDestReg(dest_idx, 1029 rename_result.first, 1030 rename_result.second); 1031 1032 ++renameRenamedOperands; 1033 } 1034} 1035 1036template <class Impl> 1037inline int 1038DefaultRename<Impl>::calcFreeROBEntries(unsigned tid) 1039{ 1040 int num_free = freeEntries[tid].robEntries - 1041 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 1042 1043 //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free); 1044 1045 return num_free; 1046} 1047 1048template <class Impl> 1049inline int 1050DefaultRename<Impl>::calcFreeIQEntries(unsigned tid) 1051{ 1052 int num_free = freeEntries[tid].iqEntries - 1053 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 1054 1055 //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free); 1056 1057 return num_free; 1058} 1059 1060template <class Impl> 1061inline int 1062DefaultRename<Impl>::calcFreeLSQEntries(unsigned tid) 1063{ 1064 int num_free = freeEntries[tid].lsqEntries - 1065 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ); 1066 1067 //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free); 1068 1069 return num_free; 1070} 1071 1072template <class Impl> 1073unsigned 1074DefaultRename<Impl>::validInsts() 1075{ 1076 unsigned inst_count = 0; 1077 1078 for (int i=0; i<fromDecode->size; i++) { 1079 if (!fromDecode->insts[i]->isSquashed()) 1080 inst_count++; 1081 } 1082 1083 return inst_count; 1084} 1085 1086template <class Impl> 1087void 1088DefaultRename<Impl>::readStallSignals(unsigned tid) 1089{ 1090 if (fromIEW->iewBlock[tid]) { 1091 stalls[tid].iew = true; 1092 } 1093 1094 if (fromIEW->iewUnblock[tid]) { 1095 assert(stalls[tid].iew); 1096 stalls[tid].iew = false; 1097 } 1098 1099 if (fromCommit->commitBlock[tid]) { 1100 stalls[tid].commit = true; 1101 } 1102 1103 if (fromCommit->commitUnblock[tid]) { 1104 assert(stalls[tid].commit); 1105 stalls[tid].commit = false; 1106 } 1107} 1108 1109template <class Impl> 1110bool 1111DefaultRename<Impl>::checkStall(unsigned tid) 1112{ 1113 bool ret_val = false; 1114 1115 if (stalls[tid].iew) { 1116 DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid); 1117 ret_val = true; 1118 } else if (stalls[tid].commit) { 1119 DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid); 1120 ret_val = true; 1121 } else if (calcFreeROBEntries(tid) <= 0) { 1122 DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid); 1123 ret_val = true; 1124 } else if (calcFreeIQEntries(tid) <= 0) { 1125 DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid); 1126 ret_val = true; 1127 } else if (calcFreeLSQEntries(tid) <= 0) { 1128 DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid); 1129 ret_val = true; 1130 } else if (renameMap[tid]->numFreeEntries() <= 0) { 1131 DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid); 1132 ret_val = true; 1133 } else if (renameStatus[tid] == SerializeStall && 1134 (!emptyROB[tid] || instsInProgress[tid])) { 1135 DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not " 1136 "empty.\n", 1137 tid); 1138 ret_val = true; 1139 } 1140 1141 return ret_val; 1142} 1143 1144template <class Impl> 1145void 1146DefaultRename<Impl>::readFreeEntries(unsigned tid) 1147{ 1148 bool updated = false; 1149 if (fromIEW->iewInfo[tid].usedIQ) { 1150 freeEntries[tid].iqEntries = 1151 fromIEW->iewInfo[tid].freeIQEntries; 1152 updated = true; 1153 } 1154 1155 if (fromIEW->iewInfo[tid].usedLSQ) { 1156 freeEntries[tid].lsqEntries = 1157 fromIEW->iewInfo[tid].freeLSQEntries; 1158 updated = true; 1159 } 1160 1161 if (fromCommit->commitInfo[tid].usedROB) { 1162 freeEntries[tid].robEntries = 1163 fromCommit->commitInfo[tid].freeROBEntries; 1164 emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB; 1165 updated = true; 1166 } 1167 1168 DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n", 1169 tid, 1170 freeEntries[tid].iqEntries, 1171 freeEntries[tid].robEntries, 1172 freeEntries[tid].lsqEntries); 1173 1174 DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n", 1175 tid, instsInProgress[tid]); 1176} 1177 1178template <class Impl> 1179bool 1180DefaultRename<Impl>::checkSignalsAndUpdate(unsigned tid) 1181{ 1182 // Check if there's a squash signal, squash if there is 1183 // Check stall signals, block if necessary. 1184 // If status was blocked 1185 // check if stall conditions have passed 1186 // if so then go to unblocking 1187 // If status was Squashing 1188 // check if squashing is not high. Switch to running this cycle. 1189 // If status was serialize stall 1190 // check if ROB is empty and no insts are in flight to the ROB 1191 1192 readFreeEntries(tid); 1193 readStallSignals(tid); 1194 1195 if (fromCommit->commitInfo[tid].squash) { 1196 DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from " 1197 "commit.\n", tid); 1198 1199#if ISA_HAS_DELAY_SLOT 1200 InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].bdelayDoneSeqNum; 1201#else 1202 InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].doneSeqNum; 1203#endif 1204 1205 squash(squashed_seq_num, tid); 1206 1207 return true; 1208 } 1209 1210 if (fromCommit->commitInfo[tid].robSquashing) { 1211 DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid); 1212 1213 renameStatus[tid] = Squashing; 1214 1215 return true; 1216 } 1217 1218 if (checkStall(tid)) { 1219 return block(tid); 1220 } 1221 1222 if (renameStatus[tid] == Blocked) { 1223 DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n", 1224 tid); 1225 1226 renameStatus[tid] = Unblocking; 1227 1228 unblock(tid); 1229 1230 return true; 1231 } 1232 1233 if (renameStatus[tid] == Squashing) { 1234 // Switch status to running if rename isn't being told to block or 1235 // squash this cycle.
| 1070 rename_result.first, 1071 rename_result.second); 1072 1073 historyBuffer[tid].push_front(hb_entry); 1074 1075 DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer " 1076 "(size=%i), [sn:%lli].\n",tid, 1077 historyBuffer[tid].size(), 1078 (*historyBuffer[tid].begin()).instSeqNum); 1079 1080 // Tell the instruction to rename the appropriate destination 1081 // register (dest_idx) to the new physical register 1082 // (rename_result.first), and record the previous physical 1083 // register that the same logical register was renamed to 1084 // (rename_result.second). 1085 inst->renameDestReg(dest_idx, 1086 rename_result.first, 1087 rename_result.second); 1088 1089 ++renameRenamedOperands; 1090 } 1091} 1092 1093template <class Impl> 1094inline int 1095DefaultRename<Impl>::calcFreeROBEntries(unsigned tid) 1096{ 1097 int num_free = freeEntries[tid].robEntries - 1098 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 1099 1100 //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free); 1101 1102 return num_free; 1103} 1104 1105template <class Impl> 1106inline int 1107DefaultRename<Impl>::calcFreeIQEntries(unsigned tid) 1108{ 1109 int num_free = freeEntries[tid].iqEntries - 1110 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 1111 1112 //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free); 1113 1114 return num_free; 1115} 1116 1117template <class Impl> 1118inline int 1119DefaultRename<Impl>::calcFreeLSQEntries(unsigned tid) 1120{ 1121 int num_free = freeEntries[tid].lsqEntries - 1122 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ); 1123 1124 //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free); 1125 1126 return num_free; 1127} 1128 1129template <class Impl> 1130unsigned 1131DefaultRename<Impl>::validInsts() 1132{ 1133 unsigned inst_count = 0; 1134 1135 for (int i=0; i<fromDecode->size; i++) { 1136 if (!fromDecode->insts[i]->isSquashed()) 1137 inst_count++; 1138 } 1139 1140 return inst_count; 1141} 1142 1143template <class Impl> 1144void 1145DefaultRename<Impl>::readStallSignals(unsigned tid) 1146{ 1147 if (fromIEW->iewBlock[tid]) { 1148 stalls[tid].iew = true; 1149 } 1150 1151 if (fromIEW->iewUnblock[tid]) { 1152 assert(stalls[tid].iew); 1153 stalls[tid].iew = false; 1154 } 1155 1156 if (fromCommit->commitBlock[tid]) { 1157 stalls[tid].commit = true; 1158 } 1159 1160 if (fromCommit->commitUnblock[tid]) { 1161 assert(stalls[tid].commit); 1162 stalls[tid].commit = false; 1163 } 1164} 1165 1166template <class Impl> 1167bool 1168DefaultRename<Impl>::checkStall(unsigned tid) 1169{ 1170 bool ret_val = false; 1171 1172 if (stalls[tid].iew) { 1173 DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid); 1174 ret_val = true; 1175 } else if (stalls[tid].commit) { 1176 DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid); 1177 ret_val = true; 1178 } else if (calcFreeROBEntries(tid) <= 0) { 1179 DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid); 1180 ret_val = true; 1181 } else if (calcFreeIQEntries(tid) <= 0) { 1182 DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid); 1183 ret_val = true; 1184 } else if (calcFreeLSQEntries(tid) <= 0) { 1185 DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid); 1186 ret_val = true; 1187 } else if (renameMap[tid]->numFreeEntries() <= 0) { 1188 DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid); 1189 ret_val = true; 1190 } else if (renameStatus[tid] == SerializeStall && 1191 (!emptyROB[tid] || instsInProgress[tid])) { 1192 DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not " 1193 "empty.\n", 1194 tid); 1195 ret_val = true; 1196 } 1197 1198 return ret_val; 1199} 1200 1201template <class Impl> 1202void 1203DefaultRename<Impl>::readFreeEntries(unsigned tid) 1204{ 1205 bool updated = false; 1206 if (fromIEW->iewInfo[tid].usedIQ) { 1207 freeEntries[tid].iqEntries = 1208 fromIEW->iewInfo[tid].freeIQEntries; 1209 updated = true; 1210 } 1211 1212 if (fromIEW->iewInfo[tid].usedLSQ) { 1213 freeEntries[tid].lsqEntries = 1214 fromIEW->iewInfo[tid].freeLSQEntries; 1215 updated = true; 1216 } 1217 1218 if (fromCommit->commitInfo[tid].usedROB) { 1219 freeEntries[tid].robEntries = 1220 fromCommit->commitInfo[tid].freeROBEntries; 1221 emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB; 1222 updated = true; 1223 } 1224 1225 DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n", 1226 tid, 1227 freeEntries[tid].iqEntries, 1228 freeEntries[tid].robEntries, 1229 freeEntries[tid].lsqEntries); 1230 1231 DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n", 1232 tid, instsInProgress[tid]); 1233} 1234 1235template <class Impl> 1236bool 1237DefaultRename<Impl>::checkSignalsAndUpdate(unsigned tid) 1238{ 1239 // Check if there's a squash signal, squash if there is 1240 // Check stall signals, block if necessary. 1241 // If status was blocked 1242 // check if stall conditions have passed 1243 // if so then go to unblocking 1244 // If status was Squashing 1245 // check if squashing is not high. Switch to running this cycle. 1246 // If status was serialize stall 1247 // check if ROB is empty and no insts are in flight to the ROB 1248 1249 readFreeEntries(tid); 1250 readStallSignals(tid); 1251 1252 if (fromCommit->commitInfo[tid].squash) { 1253 DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from " 1254 "commit.\n", tid); 1255 1256#if ISA_HAS_DELAY_SLOT 1257 InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].bdelayDoneSeqNum; 1258#else 1259 InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].doneSeqNum; 1260#endif 1261 1262 squash(squashed_seq_num, tid); 1263 1264 return true; 1265 } 1266 1267 if (fromCommit->commitInfo[tid].robSquashing) { 1268 DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid); 1269 1270 renameStatus[tid] = Squashing; 1271 1272 return true; 1273 } 1274 1275 if (checkStall(tid)) { 1276 return block(tid); 1277 } 1278 1279 if (renameStatus[tid] == Blocked) { 1280 DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n", 1281 tid); 1282 1283 renameStatus[tid] = Unblocking; 1284 1285 unblock(tid); 1286 1287 return true; 1288 } 1289 1290 if (renameStatus[tid] == Squashing) { 1291 // Switch status to running if rename isn't being told to block or 1292 // squash this cycle.
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1236 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n", 1237 tid);
| 1293 if (resumeSerialize) { 1294 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n", 1295 tid);
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1238
| 1296
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1239 renameStatus[tid] = Running;
| 1297 renameStatus[tid] = SerializeStall; 1298 return true; 1299 } else if (resumeUnblocking) { 1300 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n", 1301 tid); 1302 renameStatus[tid] = Unblocking; 1303 return true; 1304 } else { 1305 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n", 1306 tid);
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1240
| 1307
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1241 return false;
| 1308 renameStatus[tid] = Running; 1309 return false; 1310 }
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1242 } 1243 1244 if (renameStatus[tid] == SerializeStall) { 1245 // Stall ends once the ROB is free. 1246 DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to " 1247 "unblocking.\n", tid); 1248 1249 DynInstPtr serial_inst = serializeInst[tid]; 1250 1251 renameStatus[tid] = Unblocking; 1252 1253 unblock(tid); 1254 1255 DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with " 1256 "PC %#x.\n", 1257 tid, serial_inst->seqNum, serial_inst->readPC()); 1258 1259 // Put instruction into queue here. 1260 serial_inst->clearSerializeBefore(); 1261 1262 if (!skidBuffer[tid].empty()) { 1263 skidBuffer[tid].push_front(serial_inst); 1264 } else { 1265 insts[tid].push_front(serial_inst); 1266 } 1267 1268 DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename." 1269 " Adding to front of list.\n", tid); 1270 1271 serializeInst[tid] = NULL; 1272 1273 return true; 1274 } 1275 1276 // If we've reached this point, we have not gotten any signals that 1277 // cause rename to change its status. Rename remains the same as before. 1278 return false; 1279} 1280 1281template<class Impl> 1282void 1283DefaultRename<Impl>::serializeAfter(InstQueue &inst_list, 1284 unsigned tid) 1285{ 1286 if (inst_list.empty()) { 1287 // Mark a bit to say that I must serialize on the next instruction. 1288 serializeOnNextInst[tid] = true; 1289 return; 1290 } 1291 1292 // Set the next instruction as serializing. 1293 inst_list.front()->setSerializeBefore(); 1294} 1295 1296template <class Impl> 1297inline void 1298DefaultRename<Impl>::incrFullStat(const FullSource &source) 1299{ 1300 switch (source) { 1301 case ROB: 1302 ++renameROBFullEvents; 1303 break; 1304 case IQ: 1305 ++renameIQFullEvents; 1306 break; 1307 case LSQ: 1308 ++renameLSQFullEvents; 1309 break; 1310 default: 1311 panic("Rename full stall stat should be incremented for a reason!"); 1312 break; 1313 } 1314} 1315 1316template <class Impl> 1317void 1318DefaultRename<Impl>::dumpHistory() 1319{ 1320 typename std::list<RenameHistory>::iterator buf_it; 1321 1322 for (int i = 0; i < numThreads; i++) { 1323 1324 buf_it = historyBuffer[i].begin(); 1325 1326 while (buf_it != historyBuffer[i].end()) { 1327 cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys " 1328 "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg, 1329 (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg); 1330 1331 buf_it++; 1332 } 1333 } 1334}
| 1311 } 1312 1313 if (renameStatus[tid] == SerializeStall) { 1314 // Stall ends once the ROB is free. 1315 DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to " 1316 "unblocking.\n", tid); 1317 1318 DynInstPtr serial_inst = serializeInst[tid]; 1319 1320 renameStatus[tid] = Unblocking; 1321 1322 unblock(tid); 1323 1324 DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with " 1325 "PC %#x.\n", 1326 tid, serial_inst->seqNum, serial_inst->readPC()); 1327 1328 // Put instruction into queue here. 1329 serial_inst->clearSerializeBefore(); 1330 1331 if (!skidBuffer[tid].empty()) { 1332 skidBuffer[tid].push_front(serial_inst); 1333 } else { 1334 insts[tid].push_front(serial_inst); 1335 } 1336 1337 DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename." 1338 " Adding to front of list.\n", tid); 1339 1340 serializeInst[tid] = NULL; 1341 1342 return true; 1343 } 1344 1345 // If we've reached this point, we have not gotten any signals that 1346 // cause rename to change its status. Rename remains the same as before. 1347 return false; 1348} 1349 1350template<class Impl> 1351void 1352DefaultRename<Impl>::serializeAfter(InstQueue &inst_list, 1353 unsigned tid) 1354{ 1355 if (inst_list.empty()) { 1356 // Mark a bit to say that I must serialize on the next instruction. 1357 serializeOnNextInst[tid] = true; 1358 return; 1359 } 1360 1361 // Set the next instruction as serializing. 1362 inst_list.front()->setSerializeBefore(); 1363} 1364 1365template <class Impl> 1366inline void 1367DefaultRename<Impl>::incrFullStat(const FullSource &source) 1368{ 1369 switch (source) { 1370 case ROB: 1371 ++renameROBFullEvents; 1372 break; 1373 case IQ: 1374 ++renameIQFullEvents; 1375 break; 1376 case LSQ: 1377 ++renameLSQFullEvents; 1378 break; 1379 default: 1380 panic("Rename full stall stat should be incremented for a reason!"); 1381 break; 1382 } 1383} 1384 1385template <class Impl> 1386void 1387DefaultRename<Impl>::dumpHistory() 1388{ 1389 typename std::list<RenameHistory>::iterator buf_it; 1390 1391 for (int i = 0; i < numThreads; i++) { 1392 1393 buf_it = historyBuffer[i].begin(); 1394 1395 while (buf_it != historyBuffer[i].end()) { 1396 cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys " 1397 "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg, 1398 (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg); 1399 1400 buf_it++; 1401 } 1402 } 1403}
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