1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#include <list>
33
| 1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#include <list>
33
|
34#include "arch/isa_traits.hh"
35#include "arch/regfile.hh"
| |
36#include "config/full_system.hh"
37#include "cpu/o3/rename.hh"
38
39template <class Impl>
40DefaultRename<Impl>::DefaultRename(Params *params)
41 : iewToRenameDelay(params->iewToRenameDelay),
42 decodeToRenameDelay(params->decodeToRenameDelay),
43 commitToRenameDelay(params->commitToRenameDelay),
44 renameWidth(params->renameWidth),
45 commitWidth(params->commitWidth),
| 34#include "config/full_system.hh"
35#include "cpu/o3/rename.hh"
36
37template <class Impl>
38DefaultRename<Impl>::DefaultRename(Params *params)
39 : iewToRenameDelay(params->iewToRenameDelay),
40 decodeToRenameDelay(params->decodeToRenameDelay),
41 commitToRenameDelay(params->commitToRenameDelay),
42 renameWidth(params->renameWidth),
43 commitWidth(params->commitWidth),
|
46 resumeSerialize(false),
47 resumeUnblocking(false),
| |
48 numThreads(params->numberOfThreads),
49 maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs)
50{
51 _status = Inactive;
52
53 for (int i=0; i< numThreads; i++) {
54 renameStatus[i] = Idle;
55
56 freeEntries[i].iqEntries = 0;
57 freeEntries[i].lsqEntries = 0;
58 freeEntries[i].robEntries = 0;
59
60 stalls[i].iew = false;
61 stalls[i].commit = false;
62 serializeInst[i] = NULL;
63
64 instsInProgress[i] = 0;
65
66 emptyROB[i] = true;
67
68 serializeOnNextInst[i] = false;
69 }
70
71 // @todo: Make into a parameter.
72 skidBufferMax = (2 * (iewToRenameDelay * params->decodeWidth)) + renameWidth;
73}
74
75template <class Impl>
76std::string
77DefaultRename<Impl>::name() const
78{
79 return cpu->name() + ".rename";
80}
81
82template <class Impl>
83void
84DefaultRename<Impl>::regStats()
85{
86 renameSquashCycles
87 .name(name() + ".RENAME:SquashCycles")
88 .desc("Number of cycles rename is squashing")
89 .prereq(renameSquashCycles);
90 renameIdleCycles
91 .name(name() + ".RENAME:IdleCycles")
92 .desc("Number of cycles rename is idle")
93 .prereq(renameIdleCycles);
94 renameBlockCycles
95 .name(name() + ".RENAME:BlockCycles")
96 .desc("Number of cycles rename is blocking")
97 .prereq(renameBlockCycles);
98 renameSerializeStallCycles
99 .name(name() + ".RENAME:serializeStallCycles")
100 .desc("count of cycles rename stalled for serializing inst")
101 .flags(Stats::total);
102 renameRunCycles
103 .name(name() + ".RENAME:RunCycles")
104 .desc("Number of cycles rename is running")
105 .prereq(renameIdleCycles);
106 renameUnblockCycles
107 .name(name() + ".RENAME:UnblockCycles")
108 .desc("Number of cycles rename is unblocking")
109 .prereq(renameUnblockCycles);
110 renameRenamedInsts
111 .name(name() + ".RENAME:RenamedInsts")
112 .desc("Number of instructions processed by rename")
113 .prereq(renameRenamedInsts);
114 renameSquashedInsts
115 .name(name() + ".RENAME:SquashedInsts")
116 .desc("Number of squashed instructions processed by rename")
117 .prereq(renameSquashedInsts);
118 renameROBFullEvents
119 .name(name() + ".RENAME:ROBFullEvents")
120 .desc("Number of times rename has blocked due to ROB full")
121 .prereq(renameROBFullEvents);
122 renameIQFullEvents
123 .name(name() + ".RENAME:IQFullEvents")
124 .desc("Number of times rename has blocked due to IQ full")
125 .prereq(renameIQFullEvents);
126 renameLSQFullEvents
127 .name(name() + ".RENAME:LSQFullEvents")
128 .desc("Number of times rename has blocked due to LSQ full")
129 .prereq(renameLSQFullEvents);
130 renameFullRegistersEvents
131 .name(name() + ".RENAME:FullRegisterEvents")
132 .desc("Number of times there has been no free registers")
133 .prereq(renameFullRegistersEvents);
134 renameRenamedOperands
135 .name(name() + ".RENAME:RenamedOperands")
136 .desc("Number of destination operands rename has renamed")
137 .prereq(renameRenamedOperands);
138 renameRenameLookups
139 .name(name() + ".RENAME:RenameLookups")
140 .desc("Number of register rename lookups that rename has made")
141 .prereq(renameRenameLookups);
142 renameCommittedMaps
143 .name(name() + ".RENAME:CommittedMaps")
144 .desc("Number of HB maps that are committed")
145 .prereq(renameCommittedMaps);
146 renameUndoneMaps
147 .name(name() + ".RENAME:UndoneMaps")
148 .desc("Number of HB maps that are undone due to squashing")
149 .prereq(renameUndoneMaps);
150 renamedSerializing
151 .name(name() + ".RENAME:serializingInsts")
152 .desc("count of serializing insts renamed")
153 .flags(Stats::total)
154 ;
155 renamedTempSerializing
156 .name(name() + ".RENAME:tempSerializingInsts")
157 .desc("count of temporary serializing insts renamed")
158 .flags(Stats::total)
159 ;
160 renameSkidInsts
161 .name(name() + ".RENAME:skidInsts")
162 .desc("count of insts added to the skid buffer")
163 .flags(Stats::total)
164 ;
165}
166
167template <class Impl>
168void
169DefaultRename<Impl>::setCPU(O3CPU *cpu_ptr)
170{
171 DPRINTF(Rename, "Setting CPU pointer.\n");
172 cpu = cpu_ptr;
173}
174
175template <class Impl>
176void
177DefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
178{
179 DPRINTF(Rename, "Setting time buffer pointer.\n");
180 timeBuffer = tb_ptr;
181
182 // Setup wire to read information from time buffer, from IEW stage.
183 fromIEW = timeBuffer->getWire(-iewToRenameDelay);
184
185 // Setup wire to read infromation from time buffer, from commit stage.
186 fromCommit = timeBuffer->getWire(-commitToRenameDelay);
187
188 // Setup wire to write information to previous stages.
189 toDecode = timeBuffer->getWire(0);
190}
191
192template <class Impl>
193void
194DefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
195{
196 DPRINTF(Rename, "Setting rename queue pointer.\n");
197 renameQueue = rq_ptr;
198
199 // Setup wire to write information to future stages.
200 toIEW = renameQueue->getWire(0);
201}
202
203template <class Impl>
204void
205DefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
206{
207 DPRINTF(Rename, "Setting decode queue pointer.\n");
208 decodeQueue = dq_ptr;
209
210 // Setup wire to get information from decode.
211 fromDecode = decodeQueue->getWire(-decodeToRenameDelay);
212}
213
214template <class Impl>
215void
216DefaultRename<Impl>::initStage()
217{
218 // Grab the number of free entries directly from the stages.
219 for (int tid=0; tid < numThreads; tid++) {
220 freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid);
221 freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid);
222 freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid);
223 emptyROB[tid] = true;
224 }
225}
226
227template<class Impl>
228void
229DefaultRename<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
230{
231 DPRINTF(Rename, "Setting active threads list pointer.\n");
232 activeThreads = at_ptr;
233}
234
235
236template <class Impl>
237void
238DefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[])
239{
240 DPRINTF(Rename, "Setting rename map pointers.\n");
241
242 for (int i=0; i<numThreads; i++) {
243 renameMap[i] = &rm_ptr[i];
244 }
245}
246
247template <class Impl>
248void
249DefaultRename<Impl>::setFreeList(FreeList *fl_ptr)
250{
251 DPRINTF(Rename, "Setting free list pointer.\n");
252 freeList = fl_ptr;
253}
254
255template<class Impl>
256void
257DefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard)
258{
259 DPRINTF(Rename, "Setting scoreboard pointer.\n");
260 scoreboard = _scoreboard;
261}
262
263template <class Impl>
264bool
265DefaultRename<Impl>::drain()
266{
267 // Rename is ready to switch out at any time.
268 cpu->signalDrained();
269 return true;
270}
271
272template <class Impl>
273void
274DefaultRename<Impl>::switchOut()
275{
276 // Clear any state, fix up the rename map.
277 for (int i = 0; i < numThreads; i++) {
278 typename std::list<RenameHistory>::iterator hb_it =
279 historyBuffer[i].begin();
280
281 while (!historyBuffer[i].empty()) {
282 assert(hb_it != historyBuffer[i].end());
283
284 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
285 "number %i.\n", i, (*hb_it).instSeqNum);
286
287 // Tell the rename map to set the architected register to the
288 // previous physical register that it was renamed to.
289 renameMap[i]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
290
291 // Put the renamed physical register back on the free list.
292 freeList->addReg(hb_it->newPhysReg);
293
294 // Be sure to mark its register as ready if it's a misc register.
295 if (hb_it->newPhysReg >= maxPhysicalRegs) {
296 scoreboard->setReg(hb_it->newPhysReg);
297 }
298
299 historyBuffer[i].erase(hb_it++);
300 }
301 insts[i].clear();
302 skidBuffer[i].clear();
303 }
304}
305
306template <class Impl>
307void
308DefaultRename<Impl>::takeOverFrom()
309{
310 _status = Inactive;
311 initStage();
312
313 // Reset all state prior to taking over from the other CPU.
314 for (int i=0; i< numThreads; i++) {
315 renameStatus[i] = Idle;
316
317 stalls[i].iew = false;
318 stalls[i].commit = false;
319 serializeInst[i] = NULL;
320
321 instsInProgress[i] = 0;
322
323 emptyROB[i] = true;
324
325 serializeOnNextInst[i] = false;
326 }
327}
328
329template <class Impl>
330void
331DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, unsigned tid)
332{
333 DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid);
334
335 // Clear the stall signal if rename was blocked or unblocking before.
336 // If it still needs to block, the blocking should happen the next
337 // cycle and there should be space to hold everything due to the squash.
338 if (renameStatus[tid] == Blocked ||
| 44 numThreads(params->numberOfThreads),
45 maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs)
46{
47 _status = Inactive;
48
49 for (int i=0; i< numThreads; i++) {
50 renameStatus[i] = Idle;
51
52 freeEntries[i].iqEntries = 0;
53 freeEntries[i].lsqEntries = 0;
54 freeEntries[i].robEntries = 0;
55
56 stalls[i].iew = false;
57 stalls[i].commit = false;
58 serializeInst[i] = NULL;
59
60 instsInProgress[i] = 0;
61
62 emptyROB[i] = true;
63
64 serializeOnNextInst[i] = false;
65 }
66
67 // @todo: Make into a parameter.
68 skidBufferMax = (2 * (iewToRenameDelay * params->decodeWidth)) + renameWidth;
69}
70
71template <class Impl>
72std::string
73DefaultRename<Impl>::name() const
74{
75 return cpu->name() + ".rename";
76}
77
78template <class Impl>
79void
80DefaultRename<Impl>::regStats()
81{
82 renameSquashCycles
83 .name(name() + ".RENAME:SquashCycles")
84 .desc("Number of cycles rename is squashing")
85 .prereq(renameSquashCycles);
86 renameIdleCycles
87 .name(name() + ".RENAME:IdleCycles")
88 .desc("Number of cycles rename is idle")
89 .prereq(renameIdleCycles);
90 renameBlockCycles
91 .name(name() + ".RENAME:BlockCycles")
92 .desc("Number of cycles rename is blocking")
93 .prereq(renameBlockCycles);
94 renameSerializeStallCycles
95 .name(name() + ".RENAME:serializeStallCycles")
96 .desc("count of cycles rename stalled for serializing inst")
97 .flags(Stats::total);
98 renameRunCycles
99 .name(name() + ".RENAME:RunCycles")
100 .desc("Number of cycles rename is running")
101 .prereq(renameIdleCycles);
102 renameUnblockCycles
103 .name(name() + ".RENAME:UnblockCycles")
104 .desc("Number of cycles rename is unblocking")
105 .prereq(renameUnblockCycles);
106 renameRenamedInsts
107 .name(name() + ".RENAME:RenamedInsts")
108 .desc("Number of instructions processed by rename")
109 .prereq(renameRenamedInsts);
110 renameSquashedInsts
111 .name(name() + ".RENAME:SquashedInsts")
112 .desc("Number of squashed instructions processed by rename")
113 .prereq(renameSquashedInsts);
114 renameROBFullEvents
115 .name(name() + ".RENAME:ROBFullEvents")
116 .desc("Number of times rename has blocked due to ROB full")
117 .prereq(renameROBFullEvents);
118 renameIQFullEvents
119 .name(name() + ".RENAME:IQFullEvents")
120 .desc("Number of times rename has blocked due to IQ full")
121 .prereq(renameIQFullEvents);
122 renameLSQFullEvents
123 .name(name() + ".RENAME:LSQFullEvents")
124 .desc("Number of times rename has blocked due to LSQ full")
125 .prereq(renameLSQFullEvents);
126 renameFullRegistersEvents
127 .name(name() + ".RENAME:FullRegisterEvents")
128 .desc("Number of times there has been no free registers")
129 .prereq(renameFullRegistersEvents);
130 renameRenamedOperands
131 .name(name() + ".RENAME:RenamedOperands")
132 .desc("Number of destination operands rename has renamed")
133 .prereq(renameRenamedOperands);
134 renameRenameLookups
135 .name(name() + ".RENAME:RenameLookups")
136 .desc("Number of register rename lookups that rename has made")
137 .prereq(renameRenameLookups);
138 renameCommittedMaps
139 .name(name() + ".RENAME:CommittedMaps")
140 .desc("Number of HB maps that are committed")
141 .prereq(renameCommittedMaps);
142 renameUndoneMaps
143 .name(name() + ".RENAME:UndoneMaps")
144 .desc("Number of HB maps that are undone due to squashing")
145 .prereq(renameUndoneMaps);
146 renamedSerializing
147 .name(name() + ".RENAME:serializingInsts")
148 .desc("count of serializing insts renamed")
149 .flags(Stats::total)
150 ;
151 renamedTempSerializing
152 .name(name() + ".RENAME:tempSerializingInsts")
153 .desc("count of temporary serializing insts renamed")
154 .flags(Stats::total)
155 ;
156 renameSkidInsts
157 .name(name() + ".RENAME:skidInsts")
158 .desc("count of insts added to the skid buffer")
159 .flags(Stats::total)
160 ;
161}
162
163template <class Impl>
164void
165DefaultRename<Impl>::setCPU(O3CPU *cpu_ptr)
166{
167 DPRINTF(Rename, "Setting CPU pointer.\n");
168 cpu = cpu_ptr;
169}
170
171template <class Impl>
172void
173DefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
174{
175 DPRINTF(Rename, "Setting time buffer pointer.\n");
176 timeBuffer = tb_ptr;
177
178 // Setup wire to read information from time buffer, from IEW stage.
179 fromIEW = timeBuffer->getWire(-iewToRenameDelay);
180
181 // Setup wire to read infromation from time buffer, from commit stage.
182 fromCommit = timeBuffer->getWire(-commitToRenameDelay);
183
184 // Setup wire to write information to previous stages.
185 toDecode = timeBuffer->getWire(0);
186}
187
188template <class Impl>
189void
190DefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
191{
192 DPRINTF(Rename, "Setting rename queue pointer.\n");
193 renameQueue = rq_ptr;
194
195 // Setup wire to write information to future stages.
196 toIEW = renameQueue->getWire(0);
197}
198
199template <class Impl>
200void
201DefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
202{
203 DPRINTF(Rename, "Setting decode queue pointer.\n");
204 decodeQueue = dq_ptr;
205
206 // Setup wire to get information from decode.
207 fromDecode = decodeQueue->getWire(-decodeToRenameDelay);
208}
209
210template <class Impl>
211void
212DefaultRename<Impl>::initStage()
213{
214 // Grab the number of free entries directly from the stages.
215 for (int tid=0; tid < numThreads; tid++) {
216 freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid);
217 freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid);
218 freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid);
219 emptyROB[tid] = true;
220 }
221}
222
223template<class Impl>
224void
225DefaultRename<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
226{
227 DPRINTF(Rename, "Setting active threads list pointer.\n");
228 activeThreads = at_ptr;
229}
230
231
232template <class Impl>
233void
234DefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[])
235{
236 DPRINTF(Rename, "Setting rename map pointers.\n");
237
238 for (int i=0; i<numThreads; i++) {
239 renameMap[i] = &rm_ptr[i];
240 }
241}
242
243template <class Impl>
244void
245DefaultRename<Impl>::setFreeList(FreeList *fl_ptr)
246{
247 DPRINTF(Rename, "Setting free list pointer.\n");
248 freeList = fl_ptr;
249}
250
251template<class Impl>
252void
253DefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard)
254{
255 DPRINTF(Rename, "Setting scoreboard pointer.\n");
256 scoreboard = _scoreboard;
257}
258
259template <class Impl>
260bool
261DefaultRename<Impl>::drain()
262{
263 // Rename is ready to switch out at any time.
264 cpu->signalDrained();
265 return true;
266}
267
268template <class Impl>
269void
270DefaultRename<Impl>::switchOut()
271{
272 // Clear any state, fix up the rename map.
273 for (int i = 0; i < numThreads; i++) {
274 typename std::list<RenameHistory>::iterator hb_it =
275 historyBuffer[i].begin();
276
277 while (!historyBuffer[i].empty()) {
278 assert(hb_it != historyBuffer[i].end());
279
280 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
281 "number %i.\n", i, (*hb_it).instSeqNum);
282
283 // Tell the rename map to set the architected register to the
284 // previous physical register that it was renamed to.
285 renameMap[i]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
286
287 // Put the renamed physical register back on the free list.
288 freeList->addReg(hb_it->newPhysReg);
289
290 // Be sure to mark its register as ready if it's a misc register.
291 if (hb_it->newPhysReg >= maxPhysicalRegs) {
292 scoreboard->setReg(hb_it->newPhysReg);
293 }
294
295 historyBuffer[i].erase(hb_it++);
296 }
297 insts[i].clear();
298 skidBuffer[i].clear();
299 }
300}
301
302template <class Impl>
303void
304DefaultRename<Impl>::takeOverFrom()
305{
306 _status = Inactive;
307 initStage();
308
309 // Reset all state prior to taking over from the other CPU.
310 for (int i=0; i< numThreads; i++) {
311 renameStatus[i] = Idle;
312
313 stalls[i].iew = false;
314 stalls[i].commit = false;
315 serializeInst[i] = NULL;
316
317 instsInProgress[i] = 0;
318
319 emptyROB[i] = true;
320
321 serializeOnNextInst[i] = false;
322 }
323}
324
325template <class Impl>
326void
327DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, unsigned tid)
328{
329 DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid);
330
331 // Clear the stall signal if rename was blocked or unblocking before.
332 // If it still needs to block, the blocking should happen the next
333 // cycle and there should be space to hold everything due to the squash.
334 if (renameStatus[tid] == Blocked ||
|
339 renameStatus[tid] == Unblocking) {
| 335 renameStatus[tid] == Unblocking ||
336 renameStatus[tid] == SerializeStall) {
337
|
340 toDecode->renameUnblock[tid] = 1;
341
| 338 toDecode->renameUnblock[tid] = 1;
339
|
342 resumeSerialize = false;
| |
343 serializeInst[tid] = NULL;
| 340 serializeInst[tid] = NULL;
|
344 } else if (renameStatus[tid] == SerializeStall) {
345 if (serializeInst[tid]->seqNum <= squash_seq_num) {
346 DPRINTF(Rename, "Rename will resume serializing after squash\n");
347 resumeSerialize = true;
348 assert(serializeInst[tid]);
349 } else {
350 resumeSerialize = false;
351 toDecode->renameUnblock[tid] = 1;
352
353 serializeInst[tid] = NULL;
354 }
| |
355 }
356
357 // Set the status to Squashing.
358 renameStatus[tid] = Squashing;
359
360 // Squash any instructions from decode.
361 unsigned squashCount = 0;
362
363 for (int i=0; i<fromDecode->size; i++) {
364 if (fromDecode->insts[i]->threadNumber == tid &&
365 fromDecode->insts[i]->seqNum > squash_seq_num) {
366 fromDecode->insts[i]->setSquashed();
367 wroteToTimeBuffer = true;
368 squashCount++;
369 }
370
371 }
372
373 // Clear the instruction list and skid buffer in case they have any
374 // insts in them. Since we support multiple ISAs, we cant just:
375 // "insts[tid].clear();" or "skidBuffer[tid].clear()" since there is
376 // a possible delay slot inst for different architectures
377 // insts[tid].clear();
378#if ISA_HAS_DELAY_SLOT
379 DPRINTF(Rename, "[tid:%i] Squashing incoming decode instructions until "
380 "[sn:%i].\n",tid, squash_seq_num);
381 ListIt ilist_it = insts[tid].begin();
382 while (ilist_it != insts[tid].end()) {
383 if ((*ilist_it)->seqNum > squash_seq_num) {
384 (*ilist_it)->setSquashed();
385 DPRINTF(Rename, "Squashing incoming decode instruction, "
386 "[tid:%i] [sn:%i] PC %08p.\n", tid, (*ilist_it)->seqNum, (*ilist_it)->PC);
387 }
388 ilist_it++;
389 }
390#else
391 insts[tid].clear();
392#endif
393
394 // Clear the skid buffer in case it has any data in it.
395 // See comments above.
396 // skidBuffer[tid].clear();
397#if ISA_HAS_DELAY_SLOT
398 DPRINTF(Rename, "[tid:%i] Squashing incoming skidbuffer instructions "
399 "until [sn:%i].\n", tid, squash_seq_num);
400 ListIt slist_it = skidBuffer[tid].begin();
401 while (slist_it != skidBuffer[tid].end()) {
402 if ((*slist_it)->seqNum > squash_seq_num) {
403 (*slist_it)->setSquashed();
404 DPRINTF(Rename, "Squashing skidbuffer instruction, [tid:%i] [sn:%i]"
405 "PC %08p.\n", tid, (*slist_it)->seqNum, (*slist_it)->PC);
406 }
407 slist_it++;
408 }
| 341 }
342
343 // Set the status to Squashing.
344 renameStatus[tid] = Squashing;
345
346 // Squash any instructions from decode.
347 unsigned squashCount = 0;
348
349 for (int i=0; i<fromDecode->size; i++) {
350 if (fromDecode->insts[i]->threadNumber == tid &&
351 fromDecode->insts[i]->seqNum > squash_seq_num) {
352 fromDecode->insts[i]->setSquashed();
353 wroteToTimeBuffer = true;
354 squashCount++;
355 }
356
357 }
358
359 // Clear the instruction list and skid buffer in case they have any
360 // insts in them. Since we support multiple ISAs, we cant just:
361 // "insts[tid].clear();" or "skidBuffer[tid].clear()" since there is
362 // a possible delay slot inst for different architectures
363 // insts[tid].clear();
364#if ISA_HAS_DELAY_SLOT
365 DPRINTF(Rename, "[tid:%i] Squashing incoming decode instructions until "
366 "[sn:%i].\n",tid, squash_seq_num);
367 ListIt ilist_it = insts[tid].begin();
368 while (ilist_it != insts[tid].end()) {
369 if ((*ilist_it)->seqNum > squash_seq_num) {
370 (*ilist_it)->setSquashed();
371 DPRINTF(Rename, "Squashing incoming decode instruction, "
372 "[tid:%i] [sn:%i] PC %08p.\n", tid, (*ilist_it)->seqNum, (*ilist_it)->PC);
373 }
374 ilist_it++;
375 }
376#else
377 insts[tid].clear();
378#endif
379
380 // Clear the skid buffer in case it has any data in it.
381 // See comments above.
382 // skidBuffer[tid].clear();
383#if ISA_HAS_DELAY_SLOT
384 DPRINTF(Rename, "[tid:%i] Squashing incoming skidbuffer instructions "
385 "until [sn:%i].\n", tid, squash_seq_num);
386 ListIt slist_it = skidBuffer[tid].begin();
387 while (slist_it != skidBuffer[tid].end()) {
388 if ((*slist_it)->seqNum > squash_seq_num) {
389 (*slist_it)->setSquashed();
390 DPRINTF(Rename, "Squashing skidbuffer instruction, [tid:%i] [sn:%i]"
391 "PC %08p.\n", tid, (*slist_it)->seqNum, (*slist_it)->PC);
392 }
393 slist_it++;
394 }
|
409 resumeUnblocking = (skidBuffer[tid].size() != 0);
410 DPRINTF(Rename, "Resume unblocking set to %s\n",
411 resumeUnblocking ? "true" : "false");
| |
412#else
413 skidBuffer[tid].clear();
414#endif
415 doSquash(squash_seq_num, tid);
416}
417
418template <class Impl>
419void
420DefaultRename<Impl>::tick()
421{
422 wroteToTimeBuffer = false;
423
424 blockThisCycle = false;
425
426 bool status_change = false;
427
428 toIEWIndex = 0;
429
430 sortInsts();
431
| 395#else
396 skidBuffer[tid].clear();
397#endif
398 doSquash(squash_seq_num, tid);
399}
400
401template <class Impl>
402void
403DefaultRename<Impl>::tick()
404{
405 wroteToTimeBuffer = false;
406
407 blockThisCycle = false;
408
409 bool status_change = false;
410
411 toIEWIndex = 0;
412
413 sortInsts();
414
|
432 std::list<unsigned>::iterator threads = (*activeThreads).begin();
| 415 std::list<unsigned>::iterator threads = activeThreads->begin();
416 std::list<unsigned>::iterator end = activeThreads->end();
|
433
434 // Check stall and squash signals.
| 417
418 // Check stall and squash signals.
|
435 while (threads != (*activeThreads).end()) {
| 419 while (threads != end) {
|
436 unsigned tid = *threads++;
437
438 DPRINTF(Rename, "Processing [tid:%i]\n", tid);
439
440 status_change = checkSignalsAndUpdate(tid) || status_change;
441
442 rename(status_change, tid);
443 }
444
445 if (status_change) {
446 updateStatus();
447 }
448
449 if (wroteToTimeBuffer) {
450 DPRINTF(Activity, "Activity this cycle.\n");
451 cpu->activityThisCycle();
452 }
453
| 420 unsigned tid = *threads++;
421
422 DPRINTF(Rename, "Processing [tid:%i]\n", tid);
423
424 status_change = checkSignalsAndUpdate(tid) || status_change;
425
426 rename(status_change, tid);
427 }
428
429 if (status_change) {
430 updateStatus();
431 }
432
433 if (wroteToTimeBuffer) {
434 DPRINTF(Activity, "Activity this cycle.\n");
435 cpu->activityThisCycle();
436 }
437
|
454 threads = (*activeThreads).begin();
| 438 threads = activeThreads->begin();
|
455
| 439
|
456 while (threads != (*activeThreads).end()) {
| 440 while (threads != end) {
|
457 unsigned tid = *threads++;
458
459 // If we committed this cycle then doneSeqNum will be > 0
460 if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
461 !fromCommit->commitInfo[tid].squash &&
462 renameStatus[tid] != Squashing) {
463
464 removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum,
465 tid);
466 }
467 }
468
469 // @todo: make into updateProgress function
470 for (int tid=0; tid < numThreads; tid++) {
471 instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched;
472
473 assert(instsInProgress[tid] >=0);
474 }
475
476}
477
478template<class Impl>
479void
480DefaultRename<Impl>::rename(bool &status_change, unsigned tid)
481{
482 // If status is Running or idle,
483 // call renameInsts()
484 // If status is Unblocking,
485 // buffer any instructions coming from decode
486 // continue trying to empty skid buffer
487 // check if stall conditions have passed
488
489 if (renameStatus[tid] == Blocked) {
490 ++renameBlockCycles;
491 } else if (renameStatus[tid] == Squashing) {
492 ++renameSquashCycles;
493 } else if (renameStatus[tid] == SerializeStall) {
494 ++renameSerializeStallCycles;
| 441 unsigned tid = *threads++;
442
443 // If we committed this cycle then doneSeqNum will be > 0
444 if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
445 !fromCommit->commitInfo[tid].squash &&
446 renameStatus[tid] != Squashing) {
447
448 removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum,
449 tid);
450 }
451 }
452
453 // @todo: make into updateProgress function
454 for (int tid=0; tid < numThreads; tid++) {
455 instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched;
456
457 assert(instsInProgress[tid] >=0);
458 }
459
460}
461
462template<class Impl>
463void
464DefaultRename<Impl>::rename(bool &status_change, unsigned tid)
465{
466 // If status is Running or idle,
467 // call renameInsts()
468 // If status is Unblocking,
469 // buffer any instructions coming from decode
470 // continue trying to empty skid buffer
471 // check if stall conditions have passed
472
473 if (renameStatus[tid] == Blocked) {
474 ++renameBlockCycles;
475 } else if (renameStatus[tid] == Squashing) {
476 ++renameSquashCycles;
477 } else if (renameStatus[tid] == SerializeStall) {
478 ++renameSerializeStallCycles;
|
495 // If we are currently in SerializeStall and resumeSerialize
496 // was set, then that means that we are resuming serializing
497 // this cycle. Tell the previous stages to block.
498 if (resumeSerialize) {
499 resumeSerialize = false;
500 block(tid);
501 toDecode->renameUnblock[tid] = false;
502 }
503 } else if (renameStatus[tid] == Unblocking) {
504 if (resumeUnblocking) {
505 block(tid);
506 resumeUnblocking = false;
507 toDecode->renameUnblock[tid] = false;
508 }
| |
509 }
510
511 if (renameStatus[tid] == Running ||
512 renameStatus[tid] == Idle) {
513 DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run "
514 "stage.\n", tid);
515
516 renameInsts(tid);
517 } else if (renameStatus[tid] == Unblocking) {
518 renameInsts(tid);
519
520 if (validInsts()) {
521 // Add the current inputs to the skid buffer so they can be
522 // reprocessed when this stage unblocks.
523 skidInsert(tid);
524 }
525
526 // If we switched over to blocking, then there's a potential for
527 // an overall status change.
528 status_change = unblock(tid) || status_change || blockThisCycle;
529 }
530}
531
532template <class Impl>
533void
534DefaultRename<Impl>::renameInsts(unsigned tid)
535{
536 // Instructions can be either in the skid buffer or the queue of
537 // instructions coming from decode, depending on the status.
538 int insts_available = renameStatus[tid] == Unblocking ?
539 skidBuffer[tid].size() : insts[tid].size();
540
541 // Check the decode queue to see if instructions are available.
542 // If there are no available instructions to rename, then do nothing.
543 if (insts_available == 0) {
544 DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n",
545 tid);
546 // Should I change status to idle?
547 ++renameIdleCycles;
548 return;
549 } else if (renameStatus[tid] == Unblocking) {
550 ++renameUnblockCycles;
551 } else if (renameStatus[tid] == Running) {
552 ++renameRunCycles;
553 }
554
555 DynInstPtr inst;
556
557 // Will have to do a different calculation for the number of free
558 // entries.
559 int free_rob_entries = calcFreeROBEntries(tid);
560 int free_iq_entries = calcFreeIQEntries(tid);
561 int free_lsq_entries = calcFreeLSQEntries(tid);
562 int min_free_entries = free_rob_entries;
563
564 FullSource source = ROB;
565
566 if (free_iq_entries < min_free_entries) {
567 min_free_entries = free_iq_entries;
568 source = IQ;
569 }
570
571 if (free_lsq_entries < min_free_entries) {
572 min_free_entries = free_lsq_entries;
573 source = LSQ;
574 }
575
576 // Check if there's any space left.
577 if (min_free_entries <= 0) {
578 DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ "
579 "entries.\n"
580 "ROB has %i free entries.\n"
581 "IQ has %i free entries.\n"
582 "LSQ has %i free entries.\n",
583 tid,
584 free_rob_entries,
585 free_iq_entries,
586 free_lsq_entries);
587
588 blockThisCycle = true;
589
590 block(tid);
591
592 incrFullStat(source);
593
594 return;
595 } else if (min_free_entries < insts_available) {
596 DPRINTF(Rename, "[tid:%u]: Will have to block this cycle."
597 "%i insts available, but only %i insts can be "
598 "renamed due to ROB/IQ/LSQ limits.\n",
599 tid, insts_available, min_free_entries);
600
601 insts_available = min_free_entries;
602
603 blockThisCycle = true;
604
605 incrFullStat(source);
606 }
607
608 InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ?
609 skidBuffer[tid] : insts[tid];
610
611 DPRINTF(Rename, "[tid:%u]: %i available instructions to "
612 "send iew.\n", tid, insts_available);
613
614 DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts "
615 "dispatched to IQ last cycle.\n",
616 tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched);
617
618 // Handle serializing the next instruction if necessary.
619 if (serializeOnNextInst[tid]) {
620 if (emptyROB[tid] && instsInProgress[tid] == 0) {
621 // ROB already empty; no need to serialize.
622 serializeOnNextInst[tid] = false;
623 } else if (!insts_to_rename.empty()) {
624 insts_to_rename.front()->setSerializeBefore();
625 }
626 }
627
628 int renamed_insts = 0;
629
630 while (insts_available > 0 && toIEWIndex < renameWidth) {
631 DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid);
632
633 assert(!insts_to_rename.empty());
634
635 inst = insts_to_rename.front();
636
637 insts_to_rename.pop_front();
638
639 if (renameStatus[tid] == Unblocking) {
640 DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%#x from rename "
641 "skidBuffer\n",
642 tid, inst->seqNum, inst->readPC());
643 }
644
645 if (inst->isSquashed()) {
646 DPRINTF(Rename, "[tid:%u]: instruction %i with PC %#x is "
647 "squashed, skipping.\n",
648 tid, inst->seqNum, inst->readPC());
649
650 ++renameSquashedInsts;
651
652 // Decrement how many instructions are available.
653 --insts_available;
654
655 continue;
656 }
657
658 DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with "
659 "PC %#x.\n",
660 tid, inst->seqNum, inst->readPC());
661
662 // Handle serializeAfter/serializeBefore instructions.
663 // serializeAfter marks the next instruction as serializeBefore.
664 // serializeBefore makes the instruction wait in rename until the ROB
665 // is empty.
666
667 // In this model, IPR accesses are serialize before
668 // instructions, and store conditionals are serialize after
669 // instructions. This is mainly due to lack of support for
670 // out-of-order operations of either of those classes of
671 // instructions.
672 if ((inst->isIprAccess() || inst->isSerializeBefore()) &&
673 !inst->isSerializeHandled()) {
674 DPRINTF(Rename, "Serialize before instruction encountered.\n");
675
676 if (!inst->isTempSerializeBefore()) {
677 renamedSerializing++;
678 inst->setSerializeHandled();
679 } else {
680 renamedTempSerializing++;
681 }
682
683 // Change status over to SerializeStall so that other stages know
684 // what this is blocked on.
685 renameStatus[tid] = SerializeStall;
686
687 serializeInst[tid] = inst;
688
689 blockThisCycle = true;
690
691 break;
692 } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) &&
693 !inst->isSerializeHandled()) {
694 DPRINTF(Rename, "Serialize after instruction encountered.\n");
695
696 renamedSerializing++;
697
698 inst->setSerializeHandled();
699
700 serializeAfter(insts_to_rename, tid);
701 }
702
703 // Check here to make sure there are enough destination registers
704 // to rename to. Otherwise block.
705 if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) {
706 DPRINTF(Rename, "Blocking due to lack of free "
707 "physical registers to rename to.\n");
708 blockThisCycle = true;
709
710 ++renameFullRegistersEvents;
711
712 break;
713 }
714
715 renameSrcRegs(inst, inst->threadNumber);
716
717 renameDestRegs(inst, inst->threadNumber);
718
719 ++renamed_insts;
720
721 // Put instruction in rename queue.
722 toIEW->insts[toIEWIndex] = inst;
723 ++(toIEW->size);
724
725 // Increment which instruction we're on.
726 ++toIEWIndex;
727
728 // Decrement how many instructions are available.
729 --insts_available;
730 }
731
732 instsInProgress[tid] += renamed_insts;
733 renameRenamedInsts += renamed_insts;
734
735 // If we wrote to the time buffer, record this.
736 if (toIEWIndex) {
737 wroteToTimeBuffer = true;
738 }
739
740 // Check if there's any instructions left that haven't yet been renamed.
741 // If so then block.
742 if (insts_available) {
743 blockThisCycle = true;
744 }
745
746 if (blockThisCycle) {
747 block(tid);
748 toDecode->renameUnblock[tid] = false;
749 }
750}
751
752template<class Impl>
753void
754DefaultRename<Impl>::skidInsert(unsigned tid)
755{
756 DynInstPtr inst = NULL;
757
758 while (!insts[tid].empty()) {
759 inst = insts[tid].front();
760
761 insts[tid].pop_front();
762
763 assert(tid == inst->threadNumber);
764
765 DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC:%#x into Rename "
766 "skidBuffer\n", tid, inst->seqNum, inst->readPC());
767
768 ++renameSkidInsts;
769
770 skidBuffer[tid].push_back(inst);
771 }
772
773 if (skidBuffer[tid].size() > skidBufferMax)
| 479 }
480
481 if (renameStatus[tid] == Running ||
482 renameStatus[tid] == Idle) {
483 DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run "
484 "stage.\n", tid);
485
486 renameInsts(tid);
487 } else if (renameStatus[tid] == Unblocking) {
488 renameInsts(tid);
489
490 if (validInsts()) {
491 // Add the current inputs to the skid buffer so they can be
492 // reprocessed when this stage unblocks.
493 skidInsert(tid);
494 }
495
496 // If we switched over to blocking, then there's a potential for
497 // an overall status change.
498 status_change = unblock(tid) || status_change || blockThisCycle;
499 }
500}
501
502template <class Impl>
503void
504DefaultRename<Impl>::renameInsts(unsigned tid)
505{
506 // Instructions can be either in the skid buffer or the queue of
507 // instructions coming from decode, depending on the status.
508 int insts_available = renameStatus[tid] == Unblocking ?
509 skidBuffer[tid].size() : insts[tid].size();
510
511 // Check the decode queue to see if instructions are available.
512 // If there are no available instructions to rename, then do nothing.
513 if (insts_available == 0) {
514 DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n",
515 tid);
516 // Should I change status to idle?
517 ++renameIdleCycles;
518 return;
519 } else if (renameStatus[tid] == Unblocking) {
520 ++renameUnblockCycles;
521 } else if (renameStatus[tid] == Running) {
522 ++renameRunCycles;
523 }
524
525 DynInstPtr inst;
526
527 // Will have to do a different calculation for the number of free
528 // entries.
529 int free_rob_entries = calcFreeROBEntries(tid);
530 int free_iq_entries = calcFreeIQEntries(tid);
531 int free_lsq_entries = calcFreeLSQEntries(tid);
532 int min_free_entries = free_rob_entries;
533
534 FullSource source = ROB;
535
536 if (free_iq_entries < min_free_entries) {
537 min_free_entries = free_iq_entries;
538 source = IQ;
539 }
540
541 if (free_lsq_entries < min_free_entries) {
542 min_free_entries = free_lsq_entries;
543 source = LSQ;
544 }
545
546 // Check if there's any space left.
547 if (min_free_entries <= 0) {
548 DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ "
549 "entries.\n"
550 "ROB has %i free entries.\n"
551 "IQ has %i free entries.\n"
552 "LSQ has %i free entries.\n",
553 tid,
554 free_rob_entries,
555 free_iq_entries,
556 free_lsq_entries);
557
558 blockThisCycle = true;
559
560 block(tid);
561
562 incrFullStat(source);
563
564 return;
565 } else if (min_free_entries < insts_available) {
566 DPRINTF(Rename, "[tid:%u]: Will have to block this cycle."
567 "%i insts available, but only %i insts can be "
568 "renamed due to ROB/IQ/LSQ limits.\n",
569 tid, insts_available, min_free_entries);
570
571 insts_available = min_free_entries;
572
573 blockThisCycle = true;
574
575 incrFullStat(source);
576 }
577
578 InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ?
579 skidBuffer[tid] : insts[tid];
580
581 DPRINTF(Rename, "[tid:%u]: %i available instructions to "
582 "send iew.\n", tid, insts_available);
583
584 DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts "
585 "dispatched to IQ last cycle.\n",
586 tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched);
587
588 // Handle serializing the next instruction if necessary.
589 if (serializeOnNextInst[tid]) {
590 if (emptyROB[tid] && instsInProgress[tid] == 0) {
591 // ROB already empty; no need to serialize.
592 serializeOnNextInst[tid] = false;
593 } else if (!insts_to_rename.empty()) {
594 insts_to_rename.front()->setSerializeBefore();
595 }
596 }
597
598 int renamed_insts = 0;
599
600 while (insts_available > 0 && toIEWIndex < renameWidth) {
601 DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid);
602
603 assert(!insts_to_rename.empty());
604
605 inst = insts_to_rename.front();
606
607 insts_to_rename.pop_front();
608
609 if (renameStatus[tid] == Unblocking) {
610 DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%#x from rename "
611 "skidBuffer\n",
612 tid, inst->seqNum, inst->readPC());
613 }
614
615 if (inst->isSquashed()) {
616 DPRINTF(Rename, "[tid:%u]: instruction %i with PC %#x is "
617 "squashed, skipping.\n",
618 tid, inst->seqNum, inst->readPC());
619
620 ++renameSquashedInsts;
621
622 // Decrement how many instructions are available.
623 --insts_available;
624
625 continue;
626 }
627
628 DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with "
629 "PC %#x.\n",
630 tid, inst->seqNum, inst->readPC());
631
632 // Handle serializeAfter/serializeBefore instructions.
633 // serializeAfter marks the next instruction as serializeBefore.
634 // serializeBefore makes the instruction wait in rename until the ROB
635 // is empty.
636
637 // In this model, IPR accesses are serialize before
638 // instructions, and store conditionals are serialize after
639 // instructions. This is mainly due to lack of support for
640 // out-of-order operations of either of those classes of
641 // instructions.
642 if ((inst->isIprAccess() || inst->isSerializeBefore()) &&
643 !inst->isSerializeHandled()) {
644 DPRINTF(Rename, "Serialize before instruction encountered.\n");
645
646 if (!inst->isTempSerializeBefore()) {
647 renamedSerializing++;
648 inst->setSerializeHandled();
649 } else {
650 renamedTempSerializing++;
651 }
652
653 // Change status over to SerializeStall so that other stages know
654 // what this is blocked on.
655 renameStatus[tid] = SerializeStall;
656
657 serializeInst[tid] = inst;
658
659 blockThisCycle = true;
660
661 break;
662 } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) &&
663 !inst->isSerializeHandled()) {
664 DPRINTF(Rename, "Serialize after instruction encountered.\n");
665
666 renamedSerializing++;
667
668 inst->setSerializeHandled();
669
670 serializeAfter(insts_to_rename, tid);
671 }
672
673 // Check here to make sure there are enough destination registers
674 // to rename to. Otherwise block.
675 if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) {
676 DPRINTF(Rename, "Blocking due to lack of free "
677 "physical registers to rename to.\n");
678 blockThisCycle = true;
679
680 ++renameFullRegistersEvents;
681
682 break;
683 }
684
685 renameSrcRegs(inst, inst->threadNumber);
686
687 renameDestRegs(inst, inst->threadNumber);
688
689 ++renamed_insts;
690
691 // Put instruction in rename queue.
692 toIEW->insts[toIEWIndex] = inst;
693 ++(toIEW->size);
694
695 // Increment which instruction we're on.
696 ++toIEWIndex;
697
698 // Decrement how many instructions are available.
699 --insts_available;
700 }
701
702 instsInProgress[tid] += renamed_insts;
703 renameRenamedInsts += renamed_insts;
704
705 // If we wrote to the time buffer, record this.
706 if (toIEWIndex) {
707 wroteToTimeBuffer = true;
708 }
709
710 // Check if there's any instructions left that haven't yet been renamed.
711 // If so then block.
712 if (insts_available) {
713 blockThisCycle = true;
714 }
715
716 if (blockThisCycle) {
717 block(tid);
718 toDecode->renameUnblock[tid] = false;
719 }
720}
721
722template<class Impl>
723void
724DefaultRename<Impl>::skidInsert(unsigned tid)
725{
726 DynInstPtr inst = NULL;
727
728 while (!insts[tid].empty()) {
729 inst = insts[tid].front();
730
731 insts[tid].pop_front();
732
733 assert(tid == inst->threadNumber);
734
735 DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC:%#x into Rename "
736 "skidBuffer\n", tid, inst->seqNum, inst->readPC());
737
738 ++renameSkidInsts;
739
740 skidBuffer[tid].push_back(inst);
741 }
742
743 if (skidBuffer[tid].size() > skidBufferMax)
|
774 {
775 typename InstQueue::iterator it;
776 warn("Skidbuffer contents:\n");
777 for(it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++)
778 {
779 warn("[tid:%u]: %s [sn:%i].\n", tid,
780 (*it)->staticInst->disassemble(inst->readPC()),
781 (*it)->seqNum);
782 }
| |
783 panic("Skidbuffer Exceeded Max Size");
| 744 panic("Skidbuffer Exceeded Max Size");
|
784 }
| |
785}
786
787template <class Impl>
788void
789DefaultRename<Impl>::sortInsts()
790{
791 int insts_from_decode = fromDecode->size;
792#ifdef DEBUG
793#if !ISA_HAS_DELAY_SLOT
794 for (int i=0; i < numThreads; i++)
795 assert(insts[i].empty());
796#endif
797#endif
798 for (int i = 0; i < insts_from_decode; ++i) {
799 DynInstPtr inst = fromDecode->insts[i];
800 insts[inst->threadNumber].push_back(inst);
801 }
802}
803
804template<class Impl>
805bool
806DefaultRename<Impl>::skidsEmpty()
807{
| 745}
746
747template <class Impl>
748void
749DefaultRename<Impl>::sortInsts()
750{
751 int insts_from_decode = fromDecode->size;
752#ifdef DEBUG
753#if !ISA_HAS_DELAY_SLOT
754 for (int i=0; i < numThreads; i++)
755 assert(insts[i].empty());
756#endif
757#endif
758 for (int i = 0; i < insts_from_decode; ++i) {
759 DynInstPtr inst = fromDecode->insts[i];
760 insts[inst->threadNumber].push_back(inst);
761 }
762}
763
764template<class Impl>
765bool
766DefaultRename<Impl>::skidsEmpty()
767{
|
808 std::list<unsigned>::iterator threads = (*activeThreads).begin();
| 768 std::list<unsigned>::iterator threads = activeThreads->begin();
769 std::list<unsigned>::iterator end = activeThreads->end();
|
809
| 770
|
810 while (threads != (*activeThreads).end()) {
811 if (!skidBuffer[*threads++].empty())
| 771 while (threads != end) {
772 unsigned tid = *threads++;
773
774 if (!skidBuffer[tid].empty())
|
812 return false;
813 }
814
815 return true;
816}
817
818template<class Impl>
819void
820DefaultRename<Impl>::updateStatus()
821{
822 bool any_unblocking = false;
823
| 775 return false;
776 }
777
778 return true;
779}
780
781template<class Impl>
782void
783DefaultRename<Impl>::updateStatus()
784{
785 bool any_unblocking = false;
786
|
824 std::list<unsigned>::iterator threads = (*activeThreads).begin();
| 787 std::list<unsigned>::iterator threads = activeThreads->begin();
788 std::list<unsigned>::iterator end = activeThreads->end();
|
825
| 789
|
826 threads = (*activeThreads).begin();
827
828 while (threads != (*activeThreads).end()) {
| 790 while (threads != end) {
|
829 unsigned tid = *threads++;
830
831 if (renameStatus[tid] == Unblocking) {
832 any_unblocking = true;
833 break;
834 }
835 }
836
837 // Rename will have activity if it's unblocking.
838 if (any_unblocking) {
839 if (_status == Inactive) {
840 _status = Active;
841
842 DPRINTF(Activity, "Activating stage.\n");
843
844 cpu->activateStage(O3CPU::RenameIdx);
845 }
846 } else {
847 // If it's not unblocking, then rename will not have any internal
848 // activity. Switch it to inactive.
849 if (_status == Active) {
850 _status = Inactive;
851 DPRINTF(Activity, "Deactivating stage.\n");
852
853 cpu->deactivateStage(O3CPU::RenameIdx);
854 }
855 }
856}
857
858template <class Impl>
859bool
860DefaultRename<Impl>::block(unsigned tid)
861{
862 DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid);
863
864 // Add the current inputs onto the skid buffer, so they can be
865 // reprocessed when this stage unblocks.
866 skidInsert(tid);
867
868 // Only signal backwards to block if the previous stages do not think
869 // rename is already blocked.
870 if (renameStatus[tid] != Blocked) {
| 791 unsigned tid = *threads++;
792
793 if (renameStatus[tid] == Unblocking) {
794 any_unblocking = true;
795 break;
796 }
797 }
798
799 // Rename will have activity if it's unblocking.
800 if (any_unblocking) {
801 if (_status == Inactive) {
802 _status = Active;
803
804 DPRINTF(Activity, "Activating stage.\n");
805
806 cpu->activateStage(O3CPU::RenameIdx);
807 }
808 } else {
809 // If it's not unblocking, then rename will not have any internal
810 // activity. Switch it to inactive.
811 if (_status == Active) {
812 _status = Inactive;
813 DPRINTF(Activity, "Deactivating stage.\n");
814
815 cpu->deactivateStage(O3CPU::RenameIdx);
816 }
817 }
818}
819
820template <class Impl>
821bool
822DefaultRename<Impl>::block(unsigned tid)
823{
824 DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid);
825
826 // Add the current inputs onto the skid buffer, so they can be
827 // reprocessed when this stage unblocks.
828 skidInsert(tid);
829
830 // Only signal backwards to block if the previous stages do not think
831 // rename is already blocked.
832 if (renameStatus[tid] != Blocked) {
|
871 // If resumeUnblocking is set, we unblocked during the squash,
872 // but now we're have unblocking status. We need to tell earlier
873 // stages to block.
874 if (resumeUnblocking || renameStatus[tid] != Unblocking) {
| 833 if (renameStatus[tid] != Unblocking) {
|
875 toDecode->renameBlock[tid] = true;
876 toDecode->renameUnblock[tid] = false;
877 wroteToTimeBuffer = true;
878 }
879
880 // Rename can not go from SerializeStall to Blocked, otherwise
881 // it would not know to complete the serialize stall.
882 if (renameStatus[tid] != SerializeStall) {
883 // Set status to Blocked.
884 renameStatus[tid] = Blocked;
885 return true;
886 }
887 }
888
889 return false;
890}
891
892template <class Impl>
893bool
894DefaultRename<Impl>::unblock(unsigned tid)
895{
896 DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid);
897
898 // Rename is done unblocking if the skid buffer is empty.
899 if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) {
900
901 DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid);
902
903 toDecode->renameUnblock[tid] = true;
904 wroteToTimeBuffer = true;
905
906 renameStatus[tid] = Running;
907 return true;
908 }
909
910 return false;
911}
912
913template <class Impl>
914void
915DefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, unsigned tid)
916{
917 typename std::list<RenameHistory>::iterator hb_it =
918 historyBuffer[tid].begin();
919
920 // After a syscall squashes everything, the history buffer may be empty
921 // but the ROB may still be squashing instructions.
922 if (historyBuffer[tid].empty()) {
923 return;
924 }
925
926 // Go through the most recent instructions, undoing the mappings
927 // they did and freeing up the registers.
928 while (!historyBuffer[tid].empty() &&
929 (*hb_it).instSeqNum > squashed_seq_num) {
930 assert(hb_it != historyBuffer[tid].end());
931
932 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
933 "number %i.\n", tid, (*hb_it).instSeqNum);
934
935 // Tell the rename map to set the architected register to the
936 // previous physical register that it was renamed to.
937 renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
938
939 // Put the renamed physical register back on the free list.
940 freeList->addReg(hb_it->newPhysReg);
941
942 // Be sure to mark its register as ready if it's a misc register.
943 if (hb_it->newPhysReg >= maxPhysicalRegs) {
944 scoreboard->setReg(hb_it->newPhysReg);
945 }
946
947 historyBuffer[tid].erase(hb_it++);
948
949 ++renameUndoneMaps;
950 }
951}
952
953template<class Impl>
954void
955DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, unsigned tid)
956{
957 DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the "
958 "history buffer %u (size=%i), until [sn:%lli].\n",
959 tid, tid, historyBuffer[tid].size(), inst_seq_num);
960
961 typename std::list<RenameHistory>::iterator hb_it =
962 historyBuffer[tid].end();
963
964 --hb_it;
965
966 if (historyBuffer[tid].empty()) {
967 DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid);
968 return;
969 } else if (hb_it->instSeqNum > inst_seq_num) {
970 DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure "
971 "that a syscall happened recently.\n", tid);
972 return;
973 }
974
975 // Commit all the renames up until (and including) the committed sequence
976 // number. Some or even all of the committed instructions may not have
977 // rename histories if they did not have destination registers that were
978 // renamed.
979 while (!historyBuffer[tid].empty() &&
980 hb_it != historyBuffer[tid].end() &&
981 (*hb_it).instSeqNum <= inst_seq_num) {
982
983 DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, "
984 "[sn:%lli].\n",
985 tid, (*hb_it).prevPhysReg, (*hb_it).instSeqNum);
986
987 freeList->addReg((*hb_it).prevPhysReg);
988 ++renameCommittedMaps;
989
990 historyBuffer[tid].erase(hb_it--);
991 }
992}
993
994template <class Impl>
995inline void
996DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst,unsigned tid)
997{
998 assert(renameMap[tid] != 0);
999
1000 unsigned num_src_regs = inst->numSrcRegs();
1001
1002 // Get the architectual register numbers from the source and
1003 // destination operands, and redirect them to the right register.
1004 // Will need to mark dependencies though.
1005 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) {
1006 RegIndex src_reg = inst->srcRegIdx(src_idx);
| 834 toDecode->renameBlock[tid] = true;
835 toDecode->renameUnblock[tid] = false;
836 wroteToTimeBuffer = true;
837 }
838
839 // Rename can not go from SerializeStall to Blocked, otherwise
840 // it would not know to complete the serialize stall.
841 if (renameStatus[tid] != SerializeStall) {
842 // Set status to Blocked.
843 renameStatus[tid] = Blocked;
844 return true;
845 }
846 }
847
848 return false;
849}
850
851template <class Impl>
852bool
853DefaultRename<Impl>::unblock(unsigned tid)
854{
855 DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid);
856
857 // Rename is done unblocking if the skid buffer is empty.
858 if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) {
859
860 DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid);
861
862 toDecode->renameUnblock[tid] = true;
863 wroteToTimeBuffer = true;
864
865 renameStatus[tid] = Running;
866 return true;
867 }
868
869 return false;
870}
871
872template <class Impl>
873void
874DefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, unsigned tid)
875{
876 typename std::list<RenameHistory>::iterator hb_it =
877 historyBuffer[tid].begin();
878
879 // After a syscall squashes everything, the history buffer may be empty
880 // but the ROB may still be squashing instructions.
881 if (historyBuffer[tid].empty()) {
882 return;
883 }
884
885 // Go through the most recent instructions, undoing the mappings
886 // they did and freeing up the registers.
887 while (!historyBuffer[tid].empty() &&
888 (*hb_it).instSeqNum > squashed_seq_num) {
889 assert(hb_it != historyBuffer[tid].end());
890
891 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
892 "number %i.\n", tid, (*hb_it).instSeqNum);
893
894 // Tell the rename map to set the architected register to the
895 // previous physical register that it was renamed to.
896 renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
897
898 // Put the renamed physical register back on the free list.
899 freeList->addReg(hb_it->newPhysReg);
900
901 // Be sure to mark its register as ready if it's a misc register.
902 if (hb_it->newPhysReg >= maxPhysicalRegs) {
903 scoreboard->setReg(hb_it->newPhysReg);
904 }
905
906 historyBuffer[tid].erase(hb_it++);
907
908 ++renameUndoneMaps;
909 }
910}
911
912template<class Impl>
913void
914DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, unsigned tid)
915{
916 DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the "
917 "history buffer %u (size=%i), until [sn:%lli].\n",
918 tid, tid, historyBuffer[tid].size(), inst_seq_num);
919
920 typename std::list<RenameHistory>::iterator hb_it =
921 historyBuffer[tid].end();
922
923 --hb_it;
924
925 if (historyBuffer[tid].empty()) {
926 DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid);
927 return;
928 } else if (hb_it->instSeqNum > inst_seq_num) {
929 DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure "
930 "that a syscall happened recently.\n", tid);
931 return;
932 }
933
934 // Commit all the renames up until (and including) the committed sequence
935 // number. Some or even all of the committed instructions may not have
936 // rename histories if they did not have destination registers that were
937 // renamed.
938 while (!historyBuffer[tid].empty() &&
939 hb_it != historyBuffer[tid].end() &&
940 (*hb_it).instSeqNum <= inst_seq_num) {
941
942 DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, "
943 "[sn:%lli].\n",
944 tid, (*hb_it).prevPhysReg, (*hb_it).instSeqNum);
945
946 freeList->addReg((*hb_it).prevPhysReg);
947 ++renameCommittedMaps;
948
949 historyBuffer[tid].erase(hb_it--);
950 }
951}
952
953template <class Impl>
954inline void
955DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst,unsigned tid)
956{
957 assert(renameMap[tid] != 0);
958
959 unsigned num_src_regs = inst->numSrcRegs();
960
961 // Get the architectual register numbers from the source and
962 // destination operands, and redirect them to the right register.
963 // Will need to mark dependencies though.
964 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) {
965 RegIndex src_reg = inst->srcRegIdx(src_idx);
|
1007 RegIndex flat_src_reg = src_reg;
1008 if (src_reg < TheISA::FP_Base_DepTag) {
1009 flat_src_reg = TheISA::flattenIntIndex(inst->tcBase(), src_reg);
1010 DPRINTF(Rename, "Flattening index %d to %d.\n", (int)src_reg, (int)flat_src_reg);
1011 }
1012 inst->flattenSrcReg(src_idx, flat_src_reg);
| |
1013
1014 // Look up the source registers to get the phys. register they've
1015 // been renamed to, and set the sources to those registers.
| 966
967 // Look up the source registers to get the phys. register they've
968 // been renamed to, and set the sources to those registers.
|
1016 PhysRegIndex renamed_reg = renameMap[tid]->lookup(flat_src_reg);
| 969 PhysRegIndex renamed_reg = renameMap[tid]->lookup(src_reg);
|
1017
1018 DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got "
| 970
971 DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got "
|
1019 "physical reg %i.\n", tid, (int)flat_src_reg,
| 972 "physical reg %i.\n", tid, (int)src_reg,
|
1020 (int)renamed_reg);
1021
1022 inst->renameSrcReg(src_idx, renamed_reg);
1023
1024 // See if the register is ready or not.
1025 if (scoreboard->getReg(renamed_reg) == true) {
1026 DPRINTF(Rename, "[tid:%u]: Register is ready.\n", tid);
1027
1028 inst->markSrcRegReady(src_idx);
1029 }
1030
1031 ++renameRenameLookups;
1032 }
1033}
1034
1035template <class Impl>
1036inline void
1037DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst,unsigned tid)
1038{
1039 typename RenameMap::RenameInfo rename_result;
1040
1041 unsigned num_dest_regs = inst->numDestRegs();
1042
1043 // Rename the destination registers.
1044 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) {
1045 RegIndex dest_reg = inst->destRegIdx(dest_idx);
| 973 (int)renamed_reg);
974
975 inst->renameSrcReg(src_idx, renamed_reg);
976
977 // See if the register is ready or not.
978 if (scoreboard->getReg(renamed_reg) == true) {
979 DPRINTF(Rename, "[tid:%u]: Register is ready.\n", tid);
980
981 inst->markSrcRegReady(src_idx);
982 }
983
984 ++renameRenameLookups;
985 }
986}
987
988template <class Impl>
989inline void
990DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst,unsigned tid)
991{
992 typename RenameMap::RenameInfo rename_result;
993
994 unsigned num_dest_regs = inst->numDestRegs();
995
996 // Rename the destination registers.
997 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) {
998 RegIndex dest_reg = inst->destRegIdx(dest_idx);
|
1046 RegIndex flat_dest_reg = dest_reg;
1047 if (dest_reg < TheISA::FP_Base_DepTag) {
1048 flat_dest_reg = TheISA::flattenIntIndex(inst->tcBase(), dest_reg);
1049 DPRINTF(Rename, "Flattening index %d to %d.\n", (int)dest_reg, (int)flat_dest_reg);
1050 }
| |
1051
| 999
|
1052 inst->flattenDestReg(dest_idx, flat_dest_reg);
1053
| |
1054 // Get the physical register that the destination will be
1055 // renamed to.
| 1000 // Get the physical register that the destination will be
1001 // renamed to.
|
1056 rename_result = renameMap[tid]->rename(flat_dest_reg);
| 1002 rename_result = renameMap[tid]->rename(dest_reg);
|
1057
1058 //Mark Scoreboard entry as not ready
1059 scoreboard->unsetReg(rename_result.first);
1060
1061 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical "
| 1003
1004 //Mark Scoreboard entry as not ready
1005 scoreboard->unsetReg(rename_result.first);
1006
1007 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical "
|
1062 "reg %i.\n", tid, (int)flat_dest_reg,
| 1008 "reg %i.\n", tid, (int)dest_reg,
|
1063 (int)rename_result.first);
1064
1065 // Record the rename information so that a history can be kept.
| 1009 (int)rename_result.first);
1010
1011 // Record the rename information so that a history can be kept.
|
1066 RenameHistory hb_entry(inst->seqNum, flat_dest_reg,
| 1012 RenameHistory hb_entry(inst->seqNum, dest_reg,
|
1067 rename_result.first,
1068 rename_result.second);
1069
1070 historyBuffer[tid].push_front(hb_entry);
1071
1072 DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer "
1073 "(size=%i), [sn:%lli].\n",tid,
1074 historyBuffer[tid].size(),
1075 (*historyBuffer[tid].begin()).instSeqNum);
1076
1077 // Tell the instruction to rename the appropriate destination
1078 // register (dest_idx) to the new physical register
1079 // (rename_result.first), and record the previous physical
1080 // register that the same logical register was renamed to
1081 // (rename_result.second).
1082 inst->renameDestReg(dest_idx,
1083 rename_result.first,
1084 rename_result.second);
1085
1086 ++renameRenamedOperands;
1087 }
1088}
1089
1090template <class Impl>
1091inline int
1092DefaultRename<Impl>::calcFreeROBEntries(unsigned tid)
1093{
1094 int num_free = freeEntries[tid].robEntries -
1095 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1096
1097 //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free);
1098
1099 return num_free;
1100}
1101
1102template <class Impl>
1103inline int
1104DefaultRename<Impl>::calcFreeIQEntries(unsigned tid)
1105{
1106 int num_free = freeEntries[tid].iqEntries -
1107 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1108
1109 //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free);
1110
1111 return num_free;
1112}
1113
1114template <class Impl>
1115inline int
1116DefaultRename<Impl>::calcFreeLSQEntries(unsigned tid)
1117{
1118 int num_free = freeEntries[tid].lsqEntries -
1119 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ);
1120
1121 //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free);
1122
1123 return num_free;
1124}
1125
1126template <class Impl>
1127unsigned
1128DefaultRename<Impl>::validInsts()
1129{
1130 unsigned inst_count = 0;
1131
1132 for (int i=0; i<fromDecode->size; i++) {
1133 if (!fromDecode->insts[i]->isSquashed())
1134 inst_count++;
1135 }
1136
1137 return inst_count;
1138}
1139
1140template <class Impl>
1141void
1142DefaultRename<Impl>::readStallSignals(unsigned tid)
1143{
1144 if (fromIEW->iewBlock[tid]) {
1145 stalls[tid].iew = true;
1146 }
1147
1148 if (fromIEW->iewUnblock[tid]) {
1149 assert(stalls[tid].iew);
1150 stalls[tid].iew = false;
1151 }
1152
1153 if (fromCommit->commitBlock[tid]) {
1154 stalls[tid].commit = true;
1155 }
1156
1157 if (fromCommit->commitUnblock[tid]) {
1158 assert(stalls[tid].commit);
1159 stalls[tid].commit = false;
1160 }
1161}
1162
1163template <class Impl>
1164bool
1165DefaultRename<Impl>::checkStall(unsigned tid)
1166{
1167 bool ret_val = false;
1168
1169 if (stalls[tid].iew) {
1170 DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid);
1171 ret_val = true;
1172 } else if (stalls[tid].commit) {
1173 DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid);
1174 ret_val = true;
1175 } else if (calcFreeROBEntries(tid) <= 0) {
1176 DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid);
1177 ret_val = true;
1178 } else if (calcFreeIQEntries(tid) <= 0) {
1179 DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid);
1180 ret_val = true;
1181 } else if (calcFreeLSQEntries(tid) <= 0) {
1182 DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid);
1183 ret_val = true;
1184 } else if (renameMap[tid]->numFreeEntries() <= 0) {
1185 DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid);
1186 ret_val = true;
1187 } else if (renameStatus[tid] == SerializeStall &&
1188 (!emptyROB[tid] || instsInProgress[tid])) {
1189 DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not "
1190 "empty.\n",
1191 tid);
1192 ret_val = true;
1193 }
1194
1195 return ret_val;
1196}
1197
1198template <class Impl>
1199void
1200DefaultRename<Impl>::readFreeEntries(unsigned tid)
1201{
1202 bool updated = false;
1203 if (fromIEW->iewInfo[tid].usedIQ) {
1204 freeEntries[tid].iqEntries =
1205 fromIEW->iewInfo[tid].freeIQEntries;
1206 updated = true;
1207 }
1208
1209 if (fromIEW->iewInfo[tid].usedLSQ) {
1210 freeEntries[tid].lsqEntries =
1211 fromIEW->iewInfo[tid].freeLSQEntries;
1212 updated = true;
1213 }
1214
1215 if (fromCommit->commitInfo[tid].usedROB) {
1216 freeEntries[tid].robEntries =
1217 fromCommit->commitInfo[tid].freeROBEntries;
1218 emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB;
1219 updated = true;
1220 }
1221
1222 DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n",
1223 tid,
1224 freeEntries[tid].iqEntries,
1225 freeEntries[tid].robEntries,
1226 freeEntries[tid].lsqEntries);
1227
1228 DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n",
1229 tid, instsInProgress[tid]);
1230}
1231
1232template <class Impl>
1233bool
1234DefaultRename<Impl>::checkSignalsAndUpdate(unsigned tid)
1235{
1236 // Check if there's a squash signal, squash if there is
1237 // Check stall signals, block if necessary.
1238 // If status was blocked
1239 // check if stall conditions have passed
1240 // if so then go to unblocking
1241 // If status was Squashing
1242 // check if squashing is not high. Switch to running this cycle.
1243 // If status was serialize stall
1244 // check if ROB is empty and no insts are in flight to the ROB
1245
1246 readFreeEntries(tid);
1247 readStallSignals(tid);
1248
1249 if (fromCommit->commitInfo[tid].squash) {
1250 DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from "
1251 "commit.\n", tid);
1252
1253#if ISA_HAS_DELAY_SLOT
1254 InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
1255#else
1256 InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].doneSeqNum;
1257#endif
1258
1259 squash(squashed_seq_num, tid);
1260
1261 return true;
1262 }
1263
1264 if (fromCommit->commitInfo[tid].robSquashing) {
1265 DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid);
1266
1267 renameStatus[tid] = Squashing;
1268
1269 return true;
1270 }
1271
1272 if (checkStall(tid)) {
1273 return block(tid);
1274 }
1275
1276 if (renameStatus[tid] == Blocked) {
1277 DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n",
1278 tid);
1279
1280 renameStatus[tid] = Unblocking;
1281
1282 unblock(tid);
1283
1284 return true;
1285 }
1286
1287 if (renameStatus[tid] == Squashing) {
1288 // Switch status to running if rename isn't being told to block or
1289 // squash this cycle.
| 1013 rename_result.first,
1014 rename_result.second);
1015
1016 historyBuffer[tid].push_front(hb_entry);
1017
1018 DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer "
1019 "(size=%i), [sn:%lli].\n",tid,
1020 historyBuffer[tid].size(),
1021 (*historyBuffer[tid].begin()).instSeqNum);
1022
1023 // Tell the instruction to rename the appropriate destination
1024 // register (dest_idx) to the new physical register
1025 // (rename_result.first), and record the previous physical
1026 // register that the same logical register was renamed to
1027 // (rename_result.second).
1028 inst->renameDestReg(dest_idx,
1029 rename_result.first,
1030 rename_result.second);
1031
1032 ++renameRenamedOperands;
1033 }
1034}
1035
1036template <class Impl>
1037inline int
1038DefaultRename<Impl>::calcFreeROBEntries(unsigned tid)
1039{
1040 int num_free = freeEntries[tid].robEntries -
1041 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1042
1043 //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free);
1044
1045 return num_free;
1046}
1047
1048template <class Impl>
1049inline int
1050DefaultRename<Impl>::calcFreeIQEntries(unsigned tid)
1051{
1052 int num_free = freeEntries[tid].iqEntries -
1053 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1054
1055 //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free);
1056
1057 return num_free;
1058}
1059
1060template <class Impl>
1061inline int
1062DefaultRename<Impl>::calcFreeLSQEntries(unsigned tid)
1063{
1064 int num_free = freeEntries[tid].lsqEntries -
1065 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ);
1066
1067 //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free);
1068
1069 return num_free;
1070}
1071
1072template <class Impl>
1073unsigned
1074DefaultRename<Impl>::validInsts()
1075{
1076 unsigned inst_count = 0;
1077
1078 for (int i=0; i<fromDecode->size; i++) {
1079 if (!fromDecode->insts[i]->isSquashed())
1080 inst_count++;
1081 }
1082
1083 return inst_count;
1084}
1085
1086template <class Impl>
1087void
1088DefaultRename<Impl>::readStallSignals(unsigned tid)
1089{
1090 if (fromIEW->iewBlock[tid]) {
1091 stalls[tid].iew = true;
1092 }
1093
1094 if (fromIEW->iewUnblock[tid]) {
1095 assert(stalls[tid].iew);
1096 stalls[tid].iew = false;
1097 }
1098
1099 if (fromCommit->commitBlock[tid]) {
1100 stalls[tid].commit = true;
1101 }
1102
1103 if (fromCommit->commitUnblock[tid]) {
1104 assert(stalls[tid].commit);
1105 stalls[tid].commit = false;
1106 }
1107}
1108
1109template <class Impl>
1110bool
1111DefaultRename<Impl>::checkStall(unsigned tid)
1112{
1113 bool ret_val = false;
1114
1115 if (stalls[tid].iew) {
1116 DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid);
1117 ret_val = true;
1118 } else if (stalls[tid].commit) {
1119 DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid);
1120 ret_val = true;
1121 } else if (calcFreeROBEntries(tid) <= 0) {
1122 DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid);
1123 ret_val = true;
1124 } else if (calcFreeIQEntries(tid) <= 0) {
1125 DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid);
1126 ret_val = true;
1127 } else if (calcFreeLSQEntries(tid) <= 0) {
1128 DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid);
1129 ret_val = true;
1130 } else if (renameMap[tid]->numFreeEntries() <= 0) {
1131 DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid);
1132 ret_val = true;
1133 } else if (renameStatus[tid] == SerializeStall &&
1134 (!emptyROB[tid] || instsInProgress[tid])) {
1135 DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not "
1136 "empty.\n",
1137 tid);
1138 ret_val = true;
1139 }
1140
1141 return ret_val;
1142}
1143
1144template <class Impl>
1145void
1146DefaultRename<Impl>::readFreeEntries(unsigned tid)
1147{
1148 bool updated = false;
1149 if (fromIEW->iewInfo[tid].usedIQ) {
1150 freeEntries[tid].iqEntries =
1151 fromIEW->iewInfo[tid].freeIQEntries;
1152 updated = true;
1153 }
1154
1155 if (fromIEW->iewInfo[tid].usedLSQ) {
1156 freeEntries[tid].lsqEntries =
1157 fromIEW->iewInfo[tid].freeLSQEntries;
1158 updated = true;
1159 }
1160
1161 if (fromCommit->commitInfo[tid].usedROB) {
1162 freeEntries[tid].robEntries =
1163 fromCommit->commitInfo[tid].freeROBEntries;
1164 emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB;
1165 updated = true;
1166 }
1167
1168 DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n",
1169 tid,
1170 freeEntries[tid].iqEntries,
1171 freeEntries[tid].robEntries,
1172 freeEntries[tid].lsqEntries);
1173
1174 DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n",
1175 tid, instsInProgress[tid]);
1176}
1177
1178template <class Impl>
1179bool
1180DefaultRename<Impl>::checkSignalsAndUpdate(unsigned tid)
1181{
1182 // Check if there's a squash signal, squash if there is
1183 // Check stall signals, block if necessary.
1184 // If status was blocked
1185 // check if stall conditions have passed
1186 // if so then go to unblocking
1187 // If status was Squashing
1188 // check if squashing is not high. Switch to running this cycle.
1189 // If status was serialize stall
1190 // check if ROB is empty and no insts are in flight to the ROB
1191
1192 readFreeEntries(tid);
1193 readStallSignals(tid);
1194
1195 if (fromCommit->commitInfo[tid].squash) {
1196 DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from "
1197 "commit.\n", tid);
1198
1199#if ISA_HAS_DELAY_SLOT
1200 InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
1201#else
1202 InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].doneSeqNum;
1203#endif
1204
1205 squash(squashed_seq_num, tid);
1206
1207 return true;
1208 }
1209
1210 if (fromCommit->commitInfo[tid].robSquashing) {
1211 DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid);
1212
1213 renameStatus[tid] = Squashing;
1214
1215 return true;
1216 }
1217
1218 if (checkStall(tid)) {
1219 return block(tid);
1220 }
1221
1222 if (renameStatus[tid] == Blocked) {
1223 DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n",
1224 tid);
1225
1226 renameStatus[tid] = Unblocking;
1227
1228 unblock(tid);
1229
1230 return true;
1231 }
1232
1233 if (renameStatus[tid] == Squashing) {
1234 // Switch status to running if rename isn't being told to block or
1235 // squash this cycle.
|
1290 if (resumeSerialize) {
1291 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n",
1292 tid);
| 1236 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n",
1237 tid);
|
1293
| 1238
|
1294 renameStatus[tid] = SerializeStall;
1295 return true;
1296 } else if (resumeUnblocking) {
1297 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n",
1298 tid);
1299 renameStatus[tid] = Unblocking;
1300 return true;
1301 } else {
1302 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n",
1303 tid);
| 1239 renameStatus[tid] = Running;
|
1304
| 1240
|
1305 renameStatus[tid] = Running;
1306 return false;
1307 }
| 1241 return false;
|
1308 }
1309
1310 if (renameStatus[tid] == SerializeStall) {
1311 // Stall ends once the ROB is free.
1312 DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to "
1313 "unblocking.\n", tid);
1314
1315 DynInstPtr serial_inst = serializeInst[tid];
1316
1317 renameStatus[tid] = Unblocking;
1318
1319 unblock(tid);
1320
1321 DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with "
1322 "PC %#x.\n",
1323 tid, serial_inst->seqNum, serial_inst->readPC());
1324
1325 // Put instruction into queue here.
1326 serial_inst->clearSerializeBefore();
1327
1328 if (!skidBuffer[tid].empty()) {
1329 skidBuffer[tid].push_front(serial_inst);
1330 } else {
1331 insts[tid].push_front(serial_inst);
1332 }
1333
1334 DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename."
1335 " Adding to front of list.\n", tid);
1336
1337 serializeInst[tid] = NULL;
1338
1339 return true;
1340 }
1341
1342 // If we've reached this point, we have not gotten any signals that
1343 // cause rename to change its status. Rename remains the same as before.
1344 return false;
1345}
1346
1347template<class Impl>
1348void
1349DefaultRename<Impl>::serializeAfter(InstQueue &inst_list,
1350 unsigned tid)
1351{
1352 if (inst_list.empty()) {
1353 // Mark a bit to say that I must serialize on the next instruction.
1354 serializeOnNextInst[tid] = true;
1355 return;
1356 }
1357
1358 // Set the next instruction as serializing.
1359 inst_list.front()->setSerializeBefore();
1360}
1361
1362template <class Impl>
1363inline void
1364DefaultRename<Impl>::incrFullStat(const FullSource &source)
1365{
1366 switch (source) {
1367 case ROB:
1368 ++renameROBFullEvents;
1369 break;
1370 case IQ:
1371 ++renameIQFullEvents;
1372 break;
1373 case LSQ:
1374 ++renameLSQFullEvents;
1375 break;
1376 default:
1377 panic("Rename full stall stat should be incremented for a reason!");
1378 break;
1379 }
1380}
1381
1382template <class Impl>
1383void
1384DefaultRename<Impl>::dumpHistory()
1385{
1386 typename std::list<RenameHistory>::iterator buf_it;
1387
1388 for (int i = 0; i < numThreads; i++) {
1389
1390 buf_it = historyBuffer[i].begin();
1391
1392 while (buf_it != historyBuffer[i].end()) {
1393 cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys "
1394 "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg,
1395 (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg);
1396
1397 buf_it++;
1398 }
1399 }
1400}
| 1242 }
1243
1244 if (renameStatus[tid] == SerializeStall) {
1245 // Stall ends once the ROB is free.
1246 DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to "
1247 "unblocking.\n", tid);
1248
1249 DynInstPtr serial_inst = serializeInst[tid];
1250
1251 renameStatus[tid] = Unblocking;
1252
1253 unblock(tid);
1254
1255 DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with "
1256 "PC %#x.\n",
1257 tid, serial_inst->seqNum, serial_inst->readPC());
1258
1259 // Put instruction into queue here.
1260 serial_inst->clearSerializeBefore();
1261
1262 if (!skidBuffer[tid].empty()) {
1263 skidBuffer[tid].push_front(serial_inst);
1264 } else {
1265 insts[tid].push_front(serial_inst);
1266 }
1267
1268 DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename."
1269 " Adding to front of list.\n", tid);
1270
1271 serializeInst[tid] = NULL;
1272
1273 return true;
1274 }
1275
1276 // If we've reached this point, we have not gotten any signals that
1277 // cause rename to change its status. Rename remains the same as before.
1278 return false;
1279}
1280
1281template<class Impl>
1282void
1283DefaultRename<Impl>::serializeAfter(InstQueue &inst_list,
1284 unsigned tid)
1285{
1286 if (inst_list.empty()) {
1287 // Mark a bit to say that I must serialize on the next instruction.
1288 serializeOnNextInst[tid] = true;
1289 return;
1290 }
1291
1292 // Set the next instruction as serializing.
1293 inst_list.front()->setSerializeBefore();
1294}
1295
1296template <class Impl>
1297inline void
1298DefaultRename<Impl>::incrFullStat(const FullSource &source)
1299{
1300 switch (source) {
1301 case ROB:
1302 ++renameROBFullEvents;
1303 break;
1304 case IQ:
1305 ++renameIQFullEvents;
1306 break;
1307 case LSQ:
1308 ++renameLSQFullEvents;
1309 break;
1310 default:
1311 panic("Rename full stall stat should be incremented for a reason!");
1312 break;
1313 }
1314}
1315
1316template <class Impl>
1317void
1318DefaultRename<Impl>::dumpHistory()
1319{
1320 typename std::list<RenameHistory>::iterator buf_it;
1321
1322 for (int i = 0; i < numThreads; i++) {
1323
1324 buf_it = historyBuffer[i].begin();
1325
1326 while (buf_it != historyBuffer[i].end()) {
1327 cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys "
1328 "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg,
1329 (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg);
1330
1331 buf_it++;
1332 }
1333 }
1334}
|