1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#include <list>
33
34#include "config/full_system.hh"
35#include "cpu/o3/rename.hh"
36
37template <class Impl>
38DefaultRename<Impl>::DefaultRename(Params *params)
39 : iewToRenameDelay(params->iewToRenameDelay),
40 decodeToRenameDelay(params->decodeToRenameDelay),
41 commitToRenameDelay(params->commitToRenameDelay),
42 renameWidth(params->renameWidth),
43 commitWidth(params->commitWidth),
44 numThreads(params->numberOfThreads)
45{
46 _status = Inactive;
47
48 for (int i=0; i< numThreads; i++) {
49 renameStatus[i] = Idle;
50
51 freeEntries[i].iqEntries = 0;
52 freeEntries[i].lsqEntries = 0;
53 freeEntries[i].robEntries = 0;
54
55 stalls[i].iew = false;
56 stalls[i].commit = false;
57 serializeInst[i] = NULL;
58
59 instsInProgress[i] = 0;
60
61 emptyROB[i] = true;
62
63 serializeOnNextInst[i] = false;
64 }
65
66 // @todo: Make into a parameter.
67 skidBufferMax = (2 * (iewToRenameDelay * params->decodeWidth)) + renameWidth;
68}
69
70template <class Impl>
71std::string
72DefaultRename<Impl>::name() const
73{
74 return cpu->name() + ".rename";
75}
76
77template <class Impl>
78void
79DefaultRename<Impl>::regStats()
80{
81 renameSquashCycles
82 .name(name() + ".RENAME:SquashCycles")
83 .desc("Number of cycles rename is squashing")
84 .prereq(renameSquashCycles);
85 renameIdleCycles
86 .name(name() + ".RENAME:IdleCycles")
87 .desc("Number of cycles rename is idle")
88 .prereq(renameIdleCycles);
89 renameBlockCycles
90 .name(name() + ".RENAME:BlockCycles")
91 .desc("Number of cycles rename is blocking")
92 .prereq(renameBlockCycles);
93 renameSerializeStallCycles
94 .name(name() + ".RENAME:serializeStallCycles")
95 .desc("count of cycles rename stalled for serializing inst")
96 .flags(Stats::total);
97 renameRunCycles
98 .name(name() + ".RENAME:RunCycles")
99 .desc("Number of cycles rename is running")
100 .prereq(renameIdleCycles);
101 renameUnblockCycles
102 .name(name() + ".RENAME:UnblockCycles")
103 .desc("Number of cycles rename is unblocking")
104 .prereq(renameUnblockCycles);
105 renameRenamedInsts
106 .name(name() + ".RENAME:RenamedInsts")
107 .desc("Number of instructions processed by rename")
108 .prereq(renameRenamedInsts);
109 renameSquashedInsts
110 .name(name() + ".RENAME:SquashedInsts")
111 .desc("Number of squashed instructions processed by rename")
112 .prereq(renameSquashedInsts);
113 renameROBFullEvents
114 .name(name() + ".RENAME:ROBFullEvents")
115 .desc("Number of times rename has blocked due to ROB full")
116 .prereq(renameROBFullEvents);
117 renameIQFullEvents
118 .name(name() + ".RENAME:IQFullEvents")
119 .desc("Number of times rename has blocked due to IQ full")
120 .prereq(renameIQFullEvents);
121 renameLSQFullEvents
122 .name(name() + ".RENAME:LSQFullEvents")
123 .desc("Number of times rename has blocked due to LSQ full")
124 .prereq(renameLSQFullEvents);
125 renameFullRegistersEvents
126 .name(name() + ".RENAME:FullRegisterEvents")
127 .desc("Number of times there has been no free registers")
128 .prereq(renameFullRegistersEvents);
129 renameRenamedOperands
130 .name(name() + ".RENAME:RenamedOperands")
131 .desc("Number of destination operands rename has renamed")
132 .prereq(renameRenamedOperands);
133 renameRenameLookups
134 .name(name() + ".RENAME:RenameLookups")
135 .desc("Number of register rename lookups that rename has made")
136 .prereq(renameRenameLookups);
137 renameCommittedMaps
138 .name(name() + ".RENAME:CommittedMaps")
139 .desc("Number of HB maps that are committed")
140 .prereq(renameCommittedMaps);
141 renameUndoneMaps
142 .name(name() + ".RENAME:UndoneMaps")
143 .desc("Number of HB maps that are undone due to squashing")
144 .prereq(renameUndoneMaps);
145 renamedSerializing
146 .name(name() + ".RENAME:serializingInsts")
147 .desc("count of serializing insts renamed")
148 .flags(Stats::total)
149 ;
150 renamedTempSerializing
151 .name(name() + ".RENAME:tempSerializingInsts")
152 .desc("count of temporary serializing insts renamed")
153 .flags(Stats::total)
154 ;
155 renameSkidInsts
156 .name(name() + ".RENAME:skidInsts")
157 .desc("count of insts added to the skid buffer")
158 .flags(Stats::total)
159 ;
160}
161
162template <class Impl>
163void
164DefaultRename<Impl>::setCPU(O3CPU *cpu_ptr)
165{
166 DPRINTF(Rename, "Setting CPU pointer.\n");
167 cpu = cpu_ptr;
168}
169
170template <class Impl>
171void
172DefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
173{
174 DPRINTF(Rename, "Setting time buffer pointer.\n");
175 timeBuffer = tb_ptr;
176
177 // Setup wire to read information from time buffer, from IEW stage.
178 fromIEW = timeBuffer->getWire(-iewToRenameDelay);
179
180 // Setup wire to read infromation from time buffer, from commit stage.
181 fromCommit = timeBuffer->getWire(-commitToRenameDelay);
182
183 // Setup wire to write information to previous stages.
184 toDecode = timeBuffer->getWire(0);
185}
186
187template <class Impl>
188void
189DefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
190{
191 DPRINTF(Rename, "Setting rename queue pointer.\n");
192 renameQueue = rq_ptr;
193
194 // Setup wire to write information to future stages.
195 toIEW = renameQueue->getWire(0);
196}
197
198template <class Impl>
199void
200DefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
201{
202 DPRINTF(Rename, "Setting decode queue pointer.\n");
203 decodeQueue = dq_ptr;
204
205 // Setup wire to get information from decode.
206 fromDecode = decodeQueue->getWire(-decodeToRenameDelay);
207}
208
209template <class Impl>
210void
211DefaultRename<Impl>::initStage()
212{
213 // Grab the number of free entries directly from the stages.
214 for (int tid=0; tid < numThreads; tid++) {
215 freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid);
216 freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid);
217 freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid);
218 emptyROB[tid] = true;
219 }
220}
221
222template<class Impl>
223void
224DefaultRename<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
225{
226 DPRINTF(Rename, "Setting active threads list pointer.\n");
227 activeThreads = at_ptr;
228}
229
230
231template <class Impl>
232void
233DefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[])
234{
235 DPRINTF(Rename, "Setting rename map pointers.\n");
236
237 for (int i=0; i<numThreads; i++) {
238 renameMap[i] = &rm_ptr[i];
239 }
240}
241
242template <class Impl>
243void
244DefaultRename<Impl>::setFreeList(FreeList *fl_ptr)
245{
246 DPRINTF(Rename, "Setting free list pointer.\n");
247 freeList = fl_ptr;
248}
249
250template<class Impl>
251void
252DefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard)
253{
254 DPRINTF(Rename, "Setting scoreboard pointer.\n");
255 scoreboard = _scoreboard;
256}
257
258template <class Impl>
259bool
260DefaultRename<Impl>::drain()
261{
262 // Rename is ready to switch out at any time.
263 cpu->signalDrained();
264 return true;
265}
266
267template <class Impl>
268void
269DefaultRename<Impl>::switchOut()
270{
271 // Clear any state, fix up the rename map.
272 for (int i = 0; i < numThreads; i++) {
273 typename std::list<RenameHistory>::iterator hb_it =
274 historyBuffer[i].begin();
275
276 while (!historyBuffer[i].empty()) {
277 assert(hb_it != historyBuffer[i].end());
278
279 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
280 "number %i.\n", i, (*hb_it).instSeqNum);
281
282 // Tell the rename map to set the architected register to the
283 // previous physical register that it was renamed to.
284 renameMap[i]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
285
286 // Put the renamed physical register back on the free list.
287 freeList->addReg(hb_it->newPhysReg);
288
289 historyBuffer[i].erase(hb_it++);
290 }
291 insts[i].clear();
292 skidBuffer[i].clear();
293 }
294}
295
296template <class Impl>
297void
298DefaultRename<Impl>::takeOverFrom()
299{
300 _status = Inactive;
301 initStage();
302
303 // Reset all state prior to taking over from the other CPU.
304 for (int i=0; i< numThreads; i++) {
305 renameStatus[i] = Idle;
306
307 stalls[i].iew = false;
308 stalls[i].commit = false;
309 serializeInst[i] = NULL;
310
311 instsInProgress[i] = 0;
312
313 emptyROB[i] = true;
314
315 serializeOnNextInst[i] = false;
316 }
317}
318
319template <class Impl>
320void
321DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, unsigned tid)
322{
323 DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid);
324
325 // Clear the stall signal if rename was blocked or unblocking before.
326 // If it still needs to block, the blocking should happen the next
327 // cycle and there should be space to hold everything due to the squash.
328 if (renameStatus[tid] == Blocked ||
329 renameStatus[tid] == Unblocking ||
330 renameStatus[tid] == SerializeStall) {
331
332 toDecode->renameUnblock[tid] = 1;
333
334 serializeInst[tid] = NULL;
335 }
336
337 // Set the status to Squashing.
338 renameStatus[tid] = Squashing;
339
340 // Squash any instructions from decode.
341 unsigned squashCount = 0;
342
343 for (int i=0; i<fromDecode->size; i++) {
344 if (fromDecode->insts[i]->threadNumber == tid &&
345 fromDecode->insts[i]->seqNum > squash_seq_num) {
346 fromDecode->insts[i]->setSquashed();
347 wroteToTimeBuffer = true;
348 squashCount++;
349 }
350
351 }
352
353 // Clear the instruction list and skid buffer in case they have any
354 // insts in them. Since we support multiple ISAs, we cant just:
355 // "insts[tid].clear();" or "skidBuffer[tid].clear()" since there is
356 // a possible delay slot inst for different architectures
357 // insts[tid].clear();
| 1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#include <list>
33
34#include "config/full_system.hh"
35#include "cpu/o3/rename.hh"
36
37template <class Impl>
38DefaultRename<Impl>::DefaultRename(Params *params)
39 : iewToRenameDelay(params->iewToRenameDelay),
40 decodeToRenameDelay(params->decodeToRenameDelay),
41 commitToRenameDelay(params->commitToRenameDelay),
42 renameWidth(params->renameWidth),
43 commitWidth(params->commitWidth),
44 numThreads(params->numberOfThreads)
45{
46 _status = Inactive;
47
48 for (int i=0; i< numThreads; i++) {
49 renameStatus[i] = Idle;
50
51 freeEntries[i].iqEntries = 0;
52 freeEntries[i].lsqEntries = 0;
53 freeEntries[i].robEntries = 0;
54
55 stalls[i].iew = false;
56 stalls[i].commit = false;
57 serializeInst[i] = NULL;
58
59 instsInProgress[i] = 0;
60
61 emptyROB[i] = true;
62
63 serializeOnNextInst[i] = false;
64 }
65
66 // @todo: Make into a parameter.
67 skidBufferMax = (2 * (iewToRenameDelay * params->decodeWidth)) + renameWidth;
68}
69
70template <class Impl>
71std::string
72DefaultRename<Impl>::name() const
73{
74 return cpu->name() + ".rename";
75}
76
77template <class Impl>
78void
79DefaultRename<Impl>::regStats()
80{
81 renameSquashCycles
82 .name(name() + ".RENAME:SquashCycles")
83 .desc("Number of cycles rename is squashing")
84 .prereq(renameSquashCycles);
85 renameIdleCycles
86 .name(name() + ".RENAME:IdleCycles")
87 .desc("Number of cycles rename is idle")
88 .prereq(renameIdleCycles);
89 renameBlockCycles
90 .name(name() + ".RENAME:BlockCycles")
91 .desc("Number of cycles rename is blocking")
92 .prereq(renameBlockCycles);
93 renameSerializeStallCycles
94 .name(name() + ".RENAME:serializeStallCycles")
95 .desc("count of cycles rename stalled for serializing inst")
96 .flags(Stats::total);
97 renameRunCycles
98 .name(name() + ".RENAME:RunCycles")
99 .desc("Number of cycles rename is running")
100 .prereq(renameIdleCycles);
101 renameUnblockCycles
102 .name(name() + ".RENAME:UnblockCycles")
103 .desc("Number of cycles rename is unblocking")
104 .prereq(renameUnblockCycles);
105 renameRenamedInsts
106 .name(name() + ".RENAME:RenamedInsts")
107 .desc("Number of instructions processed by rename")
108 .prereq(renameRenamedInsts);
109 renameSquashedInsts
110 .name(name() + ".RENAME:SquashedInsts")
111 .desc("Number of squashed instructions processed by rename")
112 .prereq(renameSquashedInsts);
113 renameROBFullEvents
114 .name(name() + ".RENAME:ROBFullEvents")
115 .desc("Number of times rename has blocked due to ROB full")
116 .prereq(renameROBFullEvents);
117 renameIQFullEvents
118 .name(name() + ".RENAME:IQFullEvents")
119 .desc("Number of times rename has blocked due to IQ full")
120 .prereq(renameIQFullEvents);
121 renameLSQFullEvents
122 .name(name() + ".RENAME:LSQFullEvents")
123 .desc("Number of times rename has blocked due to LSQ full")
124 .prereq(renameLSQFullEvents);
125 renameFullRegistersEvents
126 .name(name() + ".RENAME:FullRegisterEvents")
127 .desc("Number of times there has been no free registers")
128 .prereq(renameFullRegistersEvents);
129 renameRenamedOperands
130 .name(name() + ".RENAME:RenamedOperands")
131 .desc("Number of destination operands rename has renamed")
132 .prereq(renameRenamedOperands);
133 renameRenameLookups
134 .name(name() + ".RENAME:RenameLookups")
135 .desc("Number of register rename lookups that rename has made")
136 .prereq(renameRenameLookups);
137 renameCommittedMaps
138 .name(name() + ".RENAME:CommittedMaps")
139 .desc("Number of HB maps that are committed")
140 .prereq(renameCommittedMaps);
141 renameUndoneMaps
142 .name(name() + ".RENAME:UndoneMaps")
143 .desc("Number of HB maps that are undone due to squashing")
144 .prereq(renameUndoneMaps);
145 renamedSerializing
146 .name(name() + ".RENAME:serializingInsts")
147 .desc("count of serializing insts renamed")
148 .flags(Stats::total)
149 ;
150 renamedTempSerializing
151 .name(name() + ".RENAME:tempSerializingInsts")
152 .desc("count of temporary serializing insts renamed")
153 .flags(Stats::total)
154 ;
155 renameSkidInsts
156 .name(name() + ".RENAME:skidInsts")
157 .desc("count of insts added to the skid buffer")
158 .flags(Stats::total)
159 ;
160}
161
162template <class Impl>
163void
164DefaultRename<Impl>::setCPU(O3CPU *cpu_ptr)
165{
166 DPRINTF(Rename, "Setting CPU pointer.\n");
167 cpu = cpu_ptr;
168}
169
170template <class Impl>
171void
172DefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
173{
174 DPRINTF(Rename, "Setting time buffer pointer.\n");
175 timeBuffer = tb_ptr;
176
177 // Setup wire to read information from time buffer, from IEW stage.
178 fromIEW = timeBuffer->getWire(-iewToRenameDelay);
179
180 // Setup wire to read infromation from time buffer, from commit stage.
181 fromCommit = timeBuffer->getWire(-commitToRenameDelay);
182
183 // Setup wire to write information to previous stages.
184 toDecode = timeBuffer->getWire(0);
185}
186
187template <class Impl>
188void
189DefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
190{
191 DPRINTF(Rename, "Setting rename queue pointer.\n");
192 renameQueue = rq_ptr;
193
194 // Setup wire to write information to future stages.
195 toIEW = renameQueue->getWire(0);
196}
197
198template <class Impl>
199void
200DefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
201{
202 DPRINTF(Rename, "Setting decode queue pointer.\n");
203 decodeQueue = dq_ptr;
204
205 // Setup wire to get information from decode.
206 fromDecode = decodeQueue->getWire(-decodeToRenameDelay);
207}
208
209template <class Impl>
210void
211DefaultRename<Impl>::initStage()
212{
213 // Grab the number of free entries directly from the stages.
214 for (int tid=0; tid < numThreads; tid++) {
215 freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid);
216 freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid);
217 freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid);
218 emptyROB[tid] = true;
219 }
220}
221
222template<class Impl>
223void
224DefaultRename<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
225{
226 DPRINTF(Rename, "Setting active threads list pointer.\n");
227 activeThreads = at_ptr;
228}
229
230
231template <class Impl>
232void
233DefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[])
234{
235 DPRINTF(Rename, "Setting rename map pointers.\n");
236
237 for (int i=0; i<numThreads; i++) {
238 renameMap[i] = &rm_ptr[i];
239 }
240}
241
242template <class Impl>
243void
244DefaultRename<Impl>::setFreeList(FreeList *fl_ptr)
245{
246 DPRINTF(Rename, "Setting free list pointer.\n");
247 freeList = fl_ptr;
248}
249
250template<class Impl>
251void
252DefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard)
253{
254 DPRINTF(Rename, "Setting scoreboard pointer.\n");
255 scoreboard = _scoreboard;
256}
257
258template <class Impl>
259bool
260DefaultRename<Impl>::drain()
261{
262 // Rename is ready to switch out at any time.
263 cpu->signalDrained();
264 return true;
265}
266
267template <class Impl>
268void
269DefaultRename<Impl>::switchOut()
270{
271 // Clear any state, fix up the rename map.
272 for (int i = 0; i < numThreads; i++) {
273 typename std::list<RenameHistory>::iterator hb_it =
274 historyBuffer[i].begin();
275
276 while (!historyBuffer[i].empty()) {
277 assert(hb_it != historyBuffer[i].end());
278
279 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
280 "number %i.\n", i, (*hb_it).instSeqNum);
281
282 // Tell the rename map to set the architected register to the
283 // previous physical register that it was renamed to.
284 renameMap[i]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
285
286 // Put the renamed physical register back on the free list.
287 freeList->addReg(hb_it->newPhysReg);
288
289 historyBuffer[i].erase(hb_it++);
290 }
291 insts[i].clear();
292 skidBuffer[i].clear();
293 }
294}
295
296template <class Impl>
297void
298DefaultRename<Impl>::takeOverFrom()
299{
300 _status = Inactive;
301 initStage();
302
303 // Reset all state prior to taking over from the other CPU.
304 for (int i=0; i< numThreads; i++) {
305 renameStatus[i] = Idle;
306
307 stalls[i].iew = false;
308 stalls[i].commit = false;
309 serializeInst[i] = NULL;
310
311 instsInProgress[i] = 0;
312
313 emptyROB[i] = true;
314
315 serializeOnNextInst[i] = false;
316 }
317}
318
319template <class Impl>
320void
321DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, unsigned tid)
322{
323 DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid);
324
325 // Clear the stall signal if rename was blocked or unblocking before.
326 // If it still needs to block, the blocking should happen the next
327 // cycle and there should be space to hold everything due to the squash.
328 if (renameStatus[tid] == Blocked ||
329 renameStatus[tid] == Unblocking ||
330 renameStatus[tid] == SerializeStall) {
331
332 toDecode->renameUnblock[tid] = 1;
333
334 serializeInst[tid] = NULL;
335 }
336
337 // Set the status to Squashing.
338 renameStatus[tid] = Squashing;
339
340 // Squash any instructions from decode.
341 unsigned squashCount = 0;
342
343 for (int i=0; i<fromDecode->size; i++) {
344 if (fromDecode->insts[i]->threadNumber == tid &&
345 fromDecode->insts[i]->seqNum > squash_seq_num) {
346 fromDecode->insts[i]->setSquashed();
347 wroteToTimeBuffer = true;
348 squashCount++;
349 }
350
351 }
352
353 // Clear the instruction list and skid buffer in case they have any
354 // insts in them. Since we support multiple ISAs, we cant just:
355 // "insts[tid].clear();" or "skidBuffer[tid].clear()" since there is
356 // a possible delay slot inst for different architectures
357 // insts[tid].clear();
|
358#if THE_ISA == ALPHA_ISA
359 insts[tid].clear();
360#else
| 358#if ISA_HAS_DELAY_SLOT
|
361 DPRINTF(Rename, "[tid:%i] Squashing incoming decode instructions until "
362 "[sn:%i].\n",tid, squash_seq_num);
363 ListIt ilist_it = insts[tid].begin();
364 while (ilist_it != insts[tid].end()) {
365 if ((*ilist_it)->seqNum > squash_seq_num) {
366 (*ilist_it)->setSquashed();
367 DPRINTF(Rename, "Squashing incoming decode instruction, "
368 "[tid:%i] [sn:%i] PC %08p.\n", tid, (*ilist_it)->seqNum, (*ilist_it)->PC);
369 }
370 ilist_it++;
371 }
| 359 DPRINTF(Rename, "[tid:%i] Squashing incoming decode instructions until "
360 "[sn:%i].\n",tid, squash_seq_num);
361 ListIt ilist_it = insts[tid].begin();
362 while (ilist_it != insts[tid].end()) {
363 if ((*ilist_it)->seqNum > squash_seq_num) {
364 (*ilist_it)->setSquashed();
365 DPRINTF(Rename, "Squashing incoming decode instruction, "
366 "[tid:%i] [sn:%i] PC %08p.\n", tid, (*ilist_it)->seqNum, (*ilist_it)->PC);
367 }
368 ilist_it++;
369 }
|
| 370#else
371 insts[tid].clear();
|
372#endif
373
374 // Clear the skid buffer in case it has any data in it.
375 // See comments above.
376 // skidBuffer[tid].clear();
| 372#endif
373
374 // Clear the skid buffer in case it has any data in it.
375 // See comments above.
376 // skidBuffer[tid].clear();
|
377#if THE_ISA == ALPHA_ISA
378 skidBuffer[tid].clear();
379#else
| 377#if ISA_HAS_DELAY_SLOT
|
380 DPRINTF(Rename, "[tid:%i] Squashing incoming skidbuffer instructions "
381 "until [sn:%i].\n", tid, squash_seq_num);
382 ListIt slist_it = skidBuffer[tid].begin();
383 while (slist_it != skidBuffer[tid].end()) {
384 if ((*slist_it)->seqNum > squash_seq_num) {
385 (*slist_it)->setSquashed();
386 DPRINTF(Rename, "Squashing skidbuffer instruction, [tid:%i] [sn:%i]"
387 "PC %08p.\n", tid, (*slist_it)->seqNum, (*slist_it)->PC);
388 }
389 slist_it++;
390 }
| 378 DPRINTF(Rename, "[tid:%i] Squashing incoming skidbuffer instructions "
379 "until [sn:%i].\n", tid, squash_seq_num);
380 ListIt slist_it = skidBuffer[tid].begin();
381 while (slist_it != skidBuffer[tid].end()) {
382 if ((*slist_it)->seqNum > squash_seq_num) {
383 (*slist_it)->setSquashed();
384 DPRINTF(Rename, "Squashing skidbuffer instruction, [tid:%i] [sn:%i]"
385 "PC %08p.\n", tid, (*slist_it)->seqNum, (*slist_it)->PC);
386 }
387 slist_it++;
388 }
|
| 389#else
390 skidBuffer[tid].clear();
|
391#endif
392 doSquash(squash_seq_num, tid);
393}
394
395template <class Impl>
396void
397DefaultRename<Impl>::tick()
398{
399 wroteToTimeBuffer = false;
400
401 blockThisCycle = false;
402
403 bool status_change = false;
404
405 toIEWIndex = 0;
406
407 sortInsts();
408
409 std::list<unsigned>::iterator threads = (*activeThreads).begin();
410
411 // Check stall and squash signals.
412 while (threads != (*activeThreads).end()) {
413 unsigned tid = *threads++;
414
415 DPRINTF(Rename, "Processing [tid:%i]\n", tid);
416
417 status_change = checkSignalsAndUpdate(tid) || status_change;
418
419 rename(status_change, tid);
420 }
421
422 if (status_change) {
423 updateStatus();
424 }
425
426 if (wroteToTimeBuffer) {
427 DPRINTF(Activity, "Activity this cycle.\n");
428 cpu->activityThisCycle();
429 }
430
431 threads = (*activeThreads).begin();
432
433 while (threads != (*activeThreads).end()) {
434 unsigned tid = *threads++;
435
436 // If we committed this cycle then doneSeqNum will be > 0
437 if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
438 !fromCommit->commitInfo[tid].squash &&
439 renameStatus[tid] != Squashing) {
440
441 removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum,
442 tid);
443 }
444 }
445
446 // @todo: make into updateProgress function
447 for (int tid=0; tid < numThreads; tid++) {
448 instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched;
449
450 assert(instsInProgress[tid] >=0);
451 }
452
453}
454
455template<class Impl>
456void
457DefaultRename<Impl>::rename(bool &status_change, unsigned tid)
458{
459 // If status is Running or idle,
460 // call renameInsts()
461 // If status is Unblocking,
462 // buffer any instructions coming from decode
463 // continue trying to empty skid buffer
464 // check if stall conditions have passed
465
466 if (renameStatus[tid] == Blocked) {
467 ++renameBlockCycles;
468 } else if (renameStatus[tid] == Squashing) {
469 ++renameSquashCycles;
470 } else if (renameStatus[tid] == SerializeStall) {
471 ++renameSerializeStallCycles;
472 }
473
474 if (renameStatus[tid] == Running ||
475 renameStatus[tid] == Idle) {
476 DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run "
477 "stage.\n", tid);
478
479 renameInsts(tid);
480 } else if (renameStatus[tid] == Unblocking) {
481 renameInsts(tid);
482
483 if (validInsts()) {
484 // Add the current inputs to the skid buffer so they can be
485 // reprocessed when this stage unblocks.
486 skidInsert(tid);
487 }
488
489 // If we switched over to blocking, then there's a potential for
490 // an overall status change.
491 status_change = unblock(tid) || status_change || blockThisCycle;
492 }
493}
494
495template <class Impl>
496void
497DefaultRename<Impl>::renameInsts(unsigned tid)
498{
499 // Instructions can be either in the skid buffer or the queue of
500 // instructions coming from decode, depending on the status.
501 int insts_available = renameStatus[tid] == Unblocking ?
502 skidBuffer[tid].size() : insts[tid].size();
503
504 // Check the decode queue to see if instructions are available.
505 // If there are no available instructions to rename, then do nothing.
506 if (insts_available == 0) {
507 DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n",
508 tid);
509 // Should I change status to idle?
510 ++renameIdleCycles;
511 return;
512 } else if (renameStatus[tid] == Unblocking) {
513 ++renameUnblockCycles;
514 } else if (renameStatus[tid] == Running) {
515 ++renameRunCycles;
516 }
517
518 DynInstPtr inst;
519
520 // Will have to do a different calculation for the number of free
521 // entries.
522 int free_rob_entries = calcFreeROBEntries(tid);
523 int free_iq_entries = calcFreeIQEntries(tid);
524 int free_lsq_entries = calcFreeLSQEntries(tid);
525 int min_free_entries = free_rob_entries;
526
527 FullSource source = ROB;
528
529 if (free_iq_entries < min_free_entries) {
530 min_free_entries = free_iq_entries;
531 source = IQ;
532 }
533
534 if (free_lsq_entries < min_free_entries) {
535 min_free_entries = free_lsq_entries;
536 source = LSQ;
537 }
538
539 // Check if there's any space left.
540 if (min_free_entries <= 0) {
541 DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ "
542 "entries.\n"
543 "ROB has %i free entries.\n"
544 "IQ has %i free entries.\n"
545 "LSQ has %i free entries.\n",
546 tid,
547 free_rob_entries,
548 free_iq_entries,
549 free_lsq_entries);
550
551 blockThisCycle = true;
552
553 block(tid);
554
555 incrFullStat(source);
556
557 return;
558 } else if (min_free_entries < insts_available) {
559 DPRINTF(Rename, "[tid:%u]: Will have to block this cycle."
560 "%i insts available, but only %i insts can be "
561 "renamed due to ROB/IQ/LSQ limits.\n",
562 tid, insts_available, min_free_entries);
563
564 insts_available = min_free_entries;
565
566 blockThisCycle = true;
567
568 incrFullStat(source);
569 }
570
571 InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ?
572 skidBuffer[tid] : insts[tid];
573
574 DPRINTF(Rename, "[tid:%u]: %i available instructions to "
575 "send iew.\n", tid, insts_available);
576
577 DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts "
578 "dispatched to IQ last cycle.\n",
579 tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched);
580
581 // Handle serializing the next instruction if necessary.
582 if (serializeOnNextInst[tid]) {
583 if (emptyROB[tid] && instsInProgress[tid] == 0) {
584 // ROB already empty; no need to serialize.
585 serializeOnNextInst[tid] = false;
586 } else if (!insts_to_rename.empty()) {
587 insts_to_rename.front()->setSerializeBefore();
588 }
589 }
590
591 int renamed_insts = 0;
592
593 while (insts_available > 0 && toIEWIndex < renameWidth) {
594 DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid);
595
596 assert(!insts_to_rename.empty());
597
598 inst = insts_to_rename.front();
599
600 insts_to_rename.pop_front();
601
602 if (renameStatus[tid] == Unblocking) {
603 DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%#x from rename "
604 "skidBuffer\n",
605 tid, inst->seqNum, inst->readPC());
606 }
607
608 if (inst->isSquashed()) {
609 DPRINTF(Rename, "[tid:%u]: instruction %i with PC %#x is "
610 "squashed, skipping.\n",
611 tid, inst->seqNum, inst->readPC());
612
613 ++renameSquashedInsts;
614
615 // Decrement how many instructions are available.
616 --insts_available;
617
618 continue;
619 }
620
621 DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with "
622 "PC %#x.\n",
623 tid, inst->seqNum, inst->readPC());
624
625 // Handle serializeAfter/serializeBefore instructions.
626 // serializeAfter marks the next instruction as serializeBefore.
627 // serializeBefore makes the instruction wait in rename until the ROB
628 // is empty.
629
630 // In this model, IPR accesses are serialize before
631 // instructions, and store conditionals are serialize after
632 // instructions. This is mainly due to lack of support for
633 // out-of-order operations of either of those classes of
634 // instructions.
635 if ((inst->isIprAccess() || inst->isSerializeBefore()) &&
636 !inst->isSerializeHandled()) {
637 DPRINTF(Rename, "Serialize before instruction encountered.\n");
638
639 if (!inst->isTempSerializeBefore()) {
640 renamedSerializing++;
641 inst->setSerializeHandled();
642 } else {
643 renamedTempSerializing++;
644 }
645
646 // Change status over to SerializeStall so that other stages know
647 // what this is blocked on.
648 renameStatus[tid] = SerializeStall;
649
650 serializeInst[tid] = inst;
651
652 blockThisCycle = true;
653
654 break;
655 } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) &&
656 !inst->isSerializeHandled()) {
657 DPRINTF(Rename, "Serialize after instruction encountered.\n");
658
659 renamedSerializing++;
660
661 inst->setSerializeHandled();
662
663 serializeAfter(insts_to_rename, tid);
664 }
665
666 // Check here to make sure there are enough destination registers
667 // to rename to. Otherwise block.
668 if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) {
669 DPRINTF(Rename, "Blocking due to lack of free "
670 "physical registers to rename to.\n");
671 blockThisCycle = true;
672
673 ++renameFullRegistersEvents;
674
675 break;
676 }
677
678 renameSrcRegs(inst, inst->threadNumber);
679
680 renameDestRegs(inst, inst->threadNumber);
681
682 ++renamed_insts;
683
684 // Put instruction in rename queue.
685 toIEW->insts[toIEWIndex] = inst;
686 ++(toIEW->size);
687
688 // Increment which instruction we're on.
689 ++toIEWIndex;
690
691 // Decrement how many instructions are available.
692 --insts_available;
693 }
694
695 instsInProgress[tid] += renamed_insts;
696 renameRenamedInsts += renamed_insts;
697
698 // If we wrote to the time buffer, record this.
699 if (toIEWIndex) {
700 wroteToTimeBuffer = true;
701 }
702
703 // Check if there's any instructions left that haven't yet been renamed.
704 // If so then block.
705 if (insts_available) {
706 blockThisCycle = true;
707 }
708
709 if (blockThisCycle) {
710 block(tid);
711 toDecode->renameUnblock[tid] = false;
712 }
713}
714
715template<class Impl>
716void
717DefaultRename<Impl>::skidInsert(unsigned tid)
718{
719 DynInstPtr inst = NULL;
720
721 while (!insts[tid].empty()) {
722 inst = insts[tid].front();
723
724 insts[tid].pop_front();
725
726 assert(tid == inst->threadNumber);
727
728 DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC:%#x into Rename "
729 "skidBuffer\n", tid, inst->seqNum, inst->readPC());
730
731 ++renameSkidInsts;
732
733 skidBuffer[tid].push_back(inst);
734 }
735
736 if (skidBuffer[tid].size() > skidBufferMax)
737 panic("Skidbuffer Exceeded Max Size");
738}
739
740template <class Impl>
741void
742DefaultRename<Impl>::sortInsts()
743{
744 int insts_from_decode = fromDecode->size;
745#ifdef DEBUG
| 391#endif
392 doSquash(squash_seq_num, tid);
393}
394
395template <class Impl>
396void
397DefaultRename<Impl>::tick()
398{
399 wroteToTimeBuffer = false;
400
401 blockThisCycle = false;
402
403 bool status_change = false;
404
405 toIEWIndex = 0;
406
407 sortInsts();
408
409 std::list<unsigned>::iterator threads = (*activeThreads).begin();
410
411 // Check stall and squash signals.
412 while (threads != (*activeThreads).end()) {
413 unsigned tid = *threads++;
414
415 DPRINTF(Rename, "Processing [tid:%i]\n", tid);
416
417 status_change = checkSignalsAndUpdate(tid) || status_change;
418
419 rename(status_change, tid);
420 }
421
422 if (status_change) {
423 updateStatus();
424 }
425
426 if (wroteToTimeBuffer) {
427 DPRINTF(Activity, "Activity this cycle.\n");
428 cpu->activityThisCycle();
429 }
430
431 threads = (*activeThreads).begin();
432
433 while (threads != (*activeThreads).end()) {
434 unsigned tid = *threads++;
435
436 // If we committed this cycle then doneSeqNum will be > 0
437 if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
438 !fromCommit->commitInfo[tid].squash &&
439 renameStatus[tid] != Squashing) {
440
441 removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum,
442 tid);
443 }
444 }
445
446 // @todo: make into updateProgress function
447 for (int tid=0; tid < numThreads; tid++) {
448 instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched;
449
450 assert(instsInProgress[tid] >=0);
451 }
452
453}
454
455template<class Impl>
456void
457DefaultRename<Impl>::rename(bool &status_change, unsigned tid)
458{
459 // If status is Running or idle,
460 // call renameInsts()
461 // If status is Unblocking,
462 // buffer any instructions coming from decode
463 // continue trying to empty skid buffer
464 // check if stall conditions have passed
465
466 if (renameStatus[tid] == Blocked) {
467 ++renameBlockCycles;
468 } else if (renameStatus[tid] == Squashing) {
469 ++renameSquashCycles;
470 } else if (renameStatus[tid] == SerializeStall) {
471 ++renameSerializeStallCycles;
472 }
473
474 if (renameStatus[tid] == Running ||
475 renameStatus[tid] == Idle) {
476 DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run "
477 "stage.\n", tid);
478
479 renameInsts(tid);
480 } else if (renameStatus[tid] == Unblocking) {
481 renameInsts(tid);
482
483 if (validInsts()) {
484 // Add the current inputs to the skid buffer so they can be
485 // reprocessed when this stage unblocks.
486 skidInsert(tid);
487 }
488
489 // If we switched over to blocking, then there's a potential for
490 // an overall status change.
491 status_change = unblock(tid) || status_change || blockThisCycle;
492 }
493}
494
495template <class Impl>
496void
497DefaultRename<Impl>::renameInsts(unsigned tid)
498{
499 // Instructions can be either in the skid buffer or the queue of
500 // instructions coming from decode, depending on the status.
501 int insts_available = renameStatus[tid] == Unblocking ?
502 skidBuffer[tid].size() : insts[tid].size();
503
504 // Check the decode queue to see if instructions are available.
505 // If there are no available instructions to rename, then do nothing.
506 if (insts_available == 0) {
507 DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n",
508 tid);
509 // Should I change status to idle?
510 ++renameIdleCycles;
511 return;
512 } else if (renameStatus[tid] == Unblocking) {
513 ++renameUnblockCycles;
514 } else if (renameStatus[tid] == Running) {
515 ++renameRunCycles;
516 }
517
518 DynInstPtr inst;
519
520 // Will have to do a different calculation for the number of free
521 // entries.
522 int free_rob_entries = calcFreeROBEntries(tid);
523 int free_iq_entries = calcFreeIQEntries(tid);
524 int free_lsq_entries = calcFreeLSQEntries(tid);
525 int min_free_entries = free_rob_entries;
526
527 FullSource source = ROB;
528
529 if (free_iq_entries < min_free_entries) {
530 min_free_entries = free_iq_entries;
531 source = IQ;
532 }
533
534 if (free_lsq_entries < min_free_entries) {
535 min_free_entries = free_lsq_entries;
536 source = LSQ;
537 }
538
539 // Check if there's any space left.
540 if (min_free_entries <= 0) {
541 DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ "
542 "entries.\n"
543 "ROB has %i free entries.\n"
544 "IQ has %i free entries.\n"
545 "LSQ has %i free entries.\n",
546 tid,
547 free_rob_entries,
548 free_iq_entries,
549 free_lsq_entries);
550
551 blockThisCycle = true;
552
553 block(tid);
554
555 incrFullStat(source);
556
557 return;
558 } else if (min_free_entries < insts_available) {
559 DPRINTF(Rename, "[tid:%u]: Will have to block this cycle."
560 "%i insts available, but only %i insts can be "
561 "renamed due to ROB/IQ/LSQ limits.\n",
562 tid, insts_available, min_free_entries);
563
564 insts_available = min_free_entries;
565
566 blockThisCycle = true;
567
568 incrFullStat(source);
569 }
570
571 InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ?
572 skidBuffer[tid] : insts[tid];
573
574 DPRINTF(Rename, "[tid:%u]: %i available instructions to "
575 "send iew.\n", tid, insts_available);
576
577 DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts "
578 "dispatched to IQ last cycle.\n",
579 tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched);
580
581 // Handle serializing the next instruction if necessary.
582 if (serializeOnNextInst[tid]) {
583 if (emptyROB[tid] && instsInProgress[tid] == 0) {
584 // ROB already empty; no need to serialize.
585 serializeOnNextInst[tid] = false;
586 } else if (!insts_to_rename.empty()) {
587 insts_to_rename.front()->setSerializeBefore();
588 }
589 }
590
591 int renamed_insts = 0;
592
593 while (insts_available > 0 && toIEWIndex < renameWidth) {
594 DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid);
595
596 assert(!insts_to_rename.empty());
597
598 inst = insts_to_rename.front();
599
600 insts_to_rename.pop_front();
601
602 if (renameStatus[tid] == Unblocking) {
603 DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%#x from rename "
604 "skidBuffer\n",
605 tid, inst->seqNum, inst->readPC());
606 }
607
608 if (inst->isSquashed()) {
609 DPRINTF(Rename, "[tid:%u]: instruction %i with PC %#x is "
610 "squashed, skipping.\n",
611 tid, inst->seqNum, inst->readPC());
612
613 ++renameSquashedInsts;
614
615 // Decrement how many instructions are available.
616 --insts_available;
617
618 continue;
619 }
620
621 DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with "
622 "PC %#x.\n",
623 tid, inst->seqNum, inst->readPC());
624
625 // Handle serializeAfter/serializeBefore instructions.
626 // serializeAfter marks the next instruction as serializeBefore.
627 // serializeBefore makes the instruction wait in rename until the ROB
628 // is empty.
629
630 // In this model, IPR accesses are serialize before
631 // instructions, and store conditionals are serialize after
632 // instructions. This is mainly due to lack of support for
633 // out-of-order operations of either of those classes of
634 // instructions.
635 if ((inst->isIprAccess() || inst->isSerializeBefore()) &&
636 !inst->isSerializeHandled()) {
637 DPRINTF(Rename, "Serialize before instruction encountered.\n");
638
639 if (!inst->isTempSerializeBefore()) {
640 renamedSerializing++;
641 inst->setSerializeHandled();
642 } else {
643 renamedTempSerializing++;
644 }
645
646 // Change status over to SerializeStall so that other stages know
647 // what this is blocked on.
648 renameStatus[tid] = SerializeStall;
649
650 serializeInst[tid] = inst;
651
652 blockThisCycle = true;
653
654 break;
655 } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) &&
656 !inst->isSerializeHandled()) {
657 DPRINTF(Rename, "Serialize after instruction encountered.\n");
658
659 renamedSerializing++;
660
661 inst->setSerializeHandled();
662
663 serializeAfter(insts_to_rename, tid);
664 }
665
666 // Check here to make sure there are enough destination registers
667 // to rename to. Otherwise block.
668 if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) {
669 DPRINTF(Rename, "Blocking due to lack of free "
670 "physical registers to rename to.\n");
671 blockThisCycle = true;
672
673 ++renameFullRegistersEvents;
674
675 break;
676 }
677
678 renameSrcRegs(inst, inst->threadNumber);
679
680 renameDestRegs(inst, inst->threadNumber);
681
682 ++renamed_insts;
683
684 // Put instruction in rename queue.
685 toIEW->insts[toIEWIndex] = inst;
686 ++(toIEW->size);
687
688 // Increment which instruction we're on.
689 ++toIEWIndex;
690
691 // Decrement how many instructions are available.
692 --insts_available;
693 }
694
695 instsInProgress[tid] += renamed_insts;
696 renameRenamedInsts += renamed_insts;
697
698 // If we wrote to the time buffer, record this.
699 if (toIEWIndex) {
700 wroteToTimeBuffer = true;
701 }
702
703 // Check if there's any instructions left that haven't yet been renamed.
704 // If so then block.
705 if (insts_available) {
706 blockThisCycle = true;
707 }
708
709 if (blockThisCycle) {
710 block(tid);
711 toDecode->renameUnblock[tid] = false;
712 }
713}
714
715template<class Impl>
716void
717DefaultRename<Impl>::skidInsert(unsigned tid)
718{
719 DynInstPtr inst = NULL;
720
721 while (!insts[tid].empty()) {
722 inst = insts[tid].front();
723
724 insts[tid].pop_front();
725
726 assert(tid == inst->threadNumber);
727
728 DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC:%#x into Rename "
729 "skidBuffer\n", tid, inst->seqNum, inst->readPC());
730
731 ++renameSkidInsts;
732
733 skidBuffer[tid].push_back(inst);
734 }
735
736 if (skidBuffer[tid].size() > skidBufferMax)
737 panic("Skidbuffer Exceeded Max Size");
738}
739
740template <class Impl>
741void
742DefaultRename<Impl>::sortInsts()
743{
744 int insts_from_decode = fromDecode->size;
745#ifdef DEBUG
|
746#if THE_ISA == ALPHA_ISA
| 746#if !ISA_HAS_DELAY_SLOT
|
747 for (int i=0; i < numThreads; i++)
748 assert(insts[i].empty());
749#endif
750#endif
751 for (int i = 0; i < insts_from_decode; ++i) {
752 DynInstPtr inst = fromDecode->insts[i];
753 insts[inst->threadNumber].push_back(inst);
754 }
755}
756
757template<class Impl>
758bool
759DefaultRename<Impl>::skidsEmpty()
760{
761 std::list<unsigned>::iterator threads = (*activeThreads).begin();
762
763 while (threads != (*activeThreads).end()) {
764 if (!skidBuffer[*threads++].empty())
765 return false;
766 }
767
768 return true;
769}
770
771template<class Impl>
772void
773DefaultRename<Impl>::updateStatus()
774{
775 bool any_unblocking = false;
776
777 std::list<unsigned>::iterator threads = (*activeThreads).begin();
778
779 threads = (*activeThreads).begin();
780
781 while (threads != (*activeThreads).end()) {
782 unsigned tid = *threads++;
783
784 if (renameStatus[tid] == Unblocking) {
785 any_unblocking = true;
786 break;
787 }
788 }
789
790 // Rename will have activity if it's unblocking.
791 if (any_unblocking) {
792 if (_status == Inactive) {
793 _status = Active;
794
795 DPRINTF(Activity, "Activating stage.\n");
796
797 cpu->activateStage(O3CPU::RenameIdx);
798 }
799 } else {
800 // If it's not unblocking, then rename will not have any internal
801 // activity. Switch it to inactive.
802 if (_status == Active) {
803 _status = Inactive;
804 DPRINTF(Activity, "Deactivating stage.\n");
805
806 cpu->deactivateStage(O3CPU::RenameIdx);
807 }
808 }
809}
810
811template <class Impl>
812bool
813DefaultRename<Impl>::block(unsigned tid)
814{
815 DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid);
816
817 // Add the current inputs onto the skid buffer, so they can be
818 // reprocessed when this stage unblocks.
819 skidInsert(tid);
820
821 // Only signal backwards to block if the previous stages do not think
822 // rename is already blocked.
823 if (renameStatus[tid] != Blocked) {
824 if (renameStatus[tid] != Unblocking) {
825 toDecode->renameBlock[tid] = true;
826 toDecode->renameUnblock[tid] = false;
827 wroteToTimeBuffer = true;
828 }
829
830 // Rename can not go from SerializeStall to Blocked, otherwise
831 // it would not know to complete the serialize stall.
832 if (renameStatus[tid] != SerializeStall) {
833 // Set status to Blocked.
834 renameStatus[tid] = Blocked;
835 return true;
836 }
837 }
838
839 return false;
840}
841
842template <class Impl>
843bool
844DefaultRename<Impl>::unblock(unsigned tid)
845{
846 DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid);
847
848 // Rename is done unblocking if the skid buffer is empty.
849 if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) {
850
851 DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid);
852
853 toDecode->renameUnblock[tid] = true;
854 wroteToTimeBuffer = true;
855
856 renameStatus[tid] = Running;
857 return true;
858 }
859
860 return false;
861}
862
863template <class Impl>
864void
865DefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, unsigned tid)
866{
867 typename std::list<RenameHistory>::iterator hb_it =
868 historyBuffer[tid].begin();
869
870 // After a syscall squashes everything, the history buffer may be empty
871 // but the ROB may still be squashing instructions.
872 if (historyBuffer[tid].empty()) {
873 return;
874 }
875
876 // Go through the most recent instructions, undoing the mappings
877 // they did and freeing up the registers.
878 while (!historyBuffer[tid].empty() &&
879 (*hb_it).instSeqNum > squashed_seq_num) {
880 assert(hb_it != historyBuffer[tid].end());
881
882 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
883 "number %i.\n", tid, (*hb_it).instSeqNum);
884
885 // Tell the rename map to set the architected register to the
886 // previous physical register that it was renamed to.
887 renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
888
889 // Put the renamed physical register back on the free list.
890 freeList->addReg(hb_it->newPhysReg);
891
892 historyBuffer[tid].erase(hb_it++);
893
894 ++renameUndoneMaps;
895 }
896}
897
898template<class Impl>
899void
900DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, unsigned tid)
901{
902 DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the "
903 "history buffer %u (size=%i), until [sn:%lli].\n",
904 tid, tid, historyBuffer[tid].size(), inst_seq_num);
905
906 typename std::list<RenameHistory>::iterator hb_it =
907 historyBuffer[tid].end();
908
909 --hb_it;
910
911 if (historyBuffer[tid].empty()) {
912 DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid);
913 return;
914 } else if (hb_it->instSeqNum > inst_seq_num) {
915 DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure "
916 "that a syscall happened recently.\n", tid);
917 return;
918 }
919
920 // Commit all the renames up until (and including) the committed sequence
921 // number. Some or even all of the committed instructions may not have
922 // rename histories if they did not have destination registers that were
923 // renamed.
924 while (!historyBuffer[tid].empty() &&
925 hb_it != historyBuffer[tid].end() &&
926 (*hb_it).instSeqNum <= inst_seq_num) {
927
928 DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, "
929 "[sn:%lli].\n",
930 tid, (*hb_it).prevPhysReg, (*hb_it).instSeqNum);
931
932 freeList->addReg((*hb_it).prevPhysReg);
933 ++renameCommittedMaps;
934
935 historyBuffer[tid].erase(hb_it--);
936 }
937}
938
939template <class Impl>
940inline void
941DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst,unsigned tid)
942{
943 assert(renameMap[tid] != 0);
944
945 unsigned num_src_regs = inst->numSrcRegs();
946
947 // Get the architectual register numbers from the source and
948 // destination operands, and redirect them to the right register.
949 // Will need to mark dependencies though.
950 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) {
951 RegIndex src_reg = inst->srcRegIdx(src_idx);
952
953 // Look up the source registers to get the phys. register they've
954 // been renamed to, and set the sources to those registers.
955 PhysRegIndex renamed_reg = renameMap[tid]->lookup(src_reg);
956
957 DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got "
958 "physical reg %i.\n", tid, (int)src_reg,
959 (int)renamed_reg);
960
961 inst->renameSrcReg(src_idx, renamed_reg);
962
963 // See if the register is ready or not.
964 if (scoreboard->getReg(renamed_reg) == true) {
965 DPRINTF(Rename, "[tid:%u]: Register is ready.\n", tid);
966
967 inst->markSrcRegReady(src_idx);
968 }
969
970 ++renameRenameLookups;
971 }
972}
973
974template <class Impl>
975inline void
976DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst,unsigned tid)
977{
978 typename RenameMap::RenameInfo rename_result;
979
980 unsigned num_dest_regs = inst->numDestRegs();
981
982 // Rename the destination registers.
983 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) {
984 RegIndex dest_reg = inst->destRegIdx(dest_idx);
985
986 // Get the physical register that the destination will be
987 // renamed to.
988 rename_result = renameMap[tid]->rename(dest_reg);
989
990 //Mark Scoreboard entry as not ready
991 scoreboard->unsetReg(rename_result.first);
992
993 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical "
994 "reg %i.\n", tid, (int)dest_reg,
995 (int)rename_result.first);
996
997 // Record the rename information so that a history can be kept.
998 RenameHistory hb_entry(inst->seqNum, dest_reg,
999 rename_result.first,
1000 rename_result.second);
1001
1002 historyBuffer[tid].push_front(hb_entry);
1003
1004 DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer "
1005 "(size=%i), [sn:%lli].\n",tid,
1006 historyBuffer[tid].size(),
1007 (*historyBuffer[tid].begin()).instSeqNum);
1008
1009 // Tell the instruction to rename the appropriate destination
1010 // register (dest_idx) to the new physical register
1011 // (rename_result.first), and record the previous physical
1012 // register that the same logical register was renamed to
1013 // (rename_result.second).
1014 inst->renameDestReg(dest_idx,
1015 rename_result.first,
1016 rename_result.second);
1017
1018 ++renameRenamedOperands;
1019 }
1020}
1021
1022template <class Impl>
1023inline int
1024DefaultRename<Impl>::calcFreeROBEntries(unsigned tid)
1025{
1026 int num_free = freeEntries[tid].robEntries -
1027 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1028
1029 //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free);
1030
1031 return num_free;
1032}
1033
1034template <class Impl>
1035inline int
1036DefaultRename<Impl>::calcFreeIQEntries(unsigned tid)
1037{
1038 int num_free = freeEntries[tid].iqEntries -
1039 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1040
1041 //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free);
1042
1043 return num_free;
1044}
1045
1046template <class Impl>
1047inline int
1048DefaultRename<Impl>::calcFreeLSQEntries(unsigned tid)
1049{
1050 int num_free = freeEntries[tid].lsqEntries -
1051 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ);
1052
1053 //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free);
1054
1055 return num_free;
1056}
1057
1058template <class Impl>
1059unsigned
1060DefaultRename<Impl>::validInsts()
1061{
1062 unsigned inst_count = 0;
1063
1064 for (int i=0; i<fromDecode->size; i++) {
1065 if (!fromDecode->insts[i]->isSquashed())
1066 inst_count++;
1067 }
1068
1069 return inst_count;
1070}
1071
1072template <class Impl>
1073void
1074DefaultRename<Impl>::readStallSignals(unsigned tid)
1075{
1076 if (fromIEW->iewBlock[tid]) {
1077 stalls[tid].iew = true;
1078 }
1079
1080 if (fromIEW->iewUnblock[tid]) {
1081 assert(stalls[tid].iew);
1082 stalls[tid].iew = false;
1083 }
1084
1085 if (fromCommit->commitBlock[tid]) {
1086 stalls[tid].commit = true;
1087 }
1088
1089 if (fromCommit->commitUnblock[tid]) {
1090 assert(stalls[tid].commit);
1091 stalls[tid].commit = false;
1092 }
1093}
1094
1095template <class Impl>
1096bool
1097DefaultRename<Impl>::checkStall(unsigned tid)
1098{
1099 bool ret_val = false;
1100
1101 if (stalls[tid].iew) {
1102 DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid);
1103 ret_val = true;
1104 } else if (stalls[tid].commit) {
1105 DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid);
1106 ret_val = true;
1107 } else if (calcFreeROBEntries(tid) <= 0) {
1108 DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid);
1109 ret_val = true;
1110 } else if (calcFreeIQEntries(tid) <= 0) {
1111 DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid);
1112 ret_val = true;
1113 } else if (calcFreeLSQEntries(tid) <= 0) {
1114 DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid);
1115 ret_val = true;
1116 } else if (renameMap[tid]->numFreeEntries() <= 0) {
1117 DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid);
1118 ret_val = true;
1119 } else if (renameStatus[tid] == SerializeStall &&
1120 (!emptyROB[tid] || instsInProgress[tid])) {
1121 DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not "
1122 "empty.\n",
1123 tid);
1124 ret_val = true;
1125 }
1126
1127 return ret_val;
1128}
1129
1130template <class Impl>
1131void
1132DefaultRename<Impl>::readFreeEntries(unsigned tid)
1133{
1134 bool updated = false;
1135 if (fromIEW->iewInfo[tid].usedIQ) {
1136 freeEntries[tid].iqEntries =
1137 fromIEW->iewInfo[tid].freeIQEntries;
1138 updated = true;
1139 }
1140
1141 if (fromIEW->iewInfo[tid].usedLSQ) {
1142 freeEntries[tid].lsqEntries =
1143 fromIEW->iewInfo[tid].freeLSQEntries;
1144 updated = true;
1145 }
1146
1147 if (fromCommit->commitInfo[tid].usedROB) {
1148 freeEntries[tid].robEntries =
1149 fromCommit->commitInfo[tid].freeROBEntries;
1150 emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB;
1151 updated = true;
1152 }
1153
1154 DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n",
1155 tid,
1156 freeEntries[tid].iqEntries,
1157 freeEntries[tid].robEntries,
1158 freeEntries[tid].lsqEntries);
1159
1160 DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n",
1161 tid, instsInProgress[tid]);
1162}
1163
1164template <class Impl>
1165bool
1166DefaultRename<Impl>::checkSignalsAndUpdate(unsigned tid)
1167{
1168 // Check if there's a squash signal, squash if there is
1169 // Check stall signals, block if necessary.
1170 // If status was blocked
1171 // check if stall conditions have passed
1172 // if so then go to unblocking
1173 // If status was Squashing
1174 // check if squashing is not high. Switch to running this cycle.
1175 // If status was serialize stall
1176 // check if ROB is empty and no insts are in flight to the ROB
1177
1178 readFreeEntries(tid);
1179 readStallSignals(tid);
1180
1181 if (fromCommit->commitInfo[tid].squash) {
1182 DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from "
1183 "commit.\n", tid);
1184
| 747 for (int i=0; i < numThreads; i++)
748 assert(insts[i].empty());
749#endif
750#endif
751 for (int i = 0; i < insts_from_decode; ++i) {
752 DynInstPtr inst = fromDecode->insts[i];
753 insts[inst->threadNumber].push_back(inst);
754 }
755}
756
757template<class Impl>
758bool
759DefaultRename<Impl>::skidsEmpty()
760{
761 std::list<unsigned>::iterator threads = (*activeThreads).begin();
762
763 while (threads != (*activeThreads).end()) {
764 if (!skidBuffer[*threads++].empty())
765 return false;
766 }
767
768 return true;
769}
770
771template<class Impl>
772void
773DefaultRename<Impl>::updateStatus()
774{
775 bool any_unblocking = false;
776
777 std::list<unsigned>::iterator threads = (*activeThreads).begin();
778
779 threads = (*activeThreads).begin();
780
781 while (threads != (*activeThreads).end()) {
782 unsigned tid = *threads++;
783
784 if (renameStatus[tid] == Unblocking) {
785 any_unblocking = true;
786 break;
787 }
788 }
789
790 // Rename will have activity if it's unblocking.
791 if (any_unblocking) {
792 if (_status == Inactive) {
793 _status = Active;
794
795 DPRINTF(Activity, "Activating stage.\n");
796
797 cpu->activateStage(O3CPU::RenameIdx);
798 }
799 } else {
800 // If it's not unblocking, then rename will not have any internal
801 // activity. Switch it to inactive.
802 if (_status == Active) {
803 _status = Inactive;
804 DPRINTF(Activity, "Deactivating stage.\n");
805
806 cpu->deactivateStage(O3CPU::RenameIdx);
807 }
808 }
809}
810
811template <class Impl>
812bool
813DefaultRename<Impl>::block(unsigned tid)
814{
815 DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid);
816
817 // Add the current inputs onto the skid buffer, so they can be
818 // reprocessed when this stage unblocks.
819 skidInsert(tid);
820
821 // Only signal backwards to block if the previous stages do not think
822 // rename is already blocked.
823 if (renameStatus[tid] != Blocked) {
824 if (renameStatus[tid] != Unblocking) {
825 toDecode->renameBlock[tid] = true;
826 toDecode->renameUnblock[tid] = false;
827 wroteToTimeBuffer = true;
828 }
829
830 // Rename can not go from SerializeStall to Blocked, otherwise
831 // it would not know to complete the serialize stall.
832 if (renameStatus[tid] != SerializeStall) {
833 // Set status to Blocked.
834 renameStatus[tid] = Blocked;
835 return true;
836 }
837 }
838
839 return false;
840}
841
842template <class Impl>
843bool
844DefaultRename<Impl>::unblock(unsigned tid)
845{
846 DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid);
847
848 // Rename is done unblocking if the skid buffer is empty.
849 if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) {
850
851 DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid);
852
853 toDecode->renameUnblock[tid] = true;
854 wroteToTimeBuffer = true;
855
856 renameStatus[tid] = Running;
857 return true;
858 }
859
860 return false;
861}
862
863template <class Impl>
864void
865DefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, unsigned tid)
866{
867 typename std::list<RenameHistory>::iterator hb_it =
868 historyBuffer[tid].begin();
869
870 // After a syscall squashes everything, the history buffer may be empty
871 // but the ROB may still be squashing instructions.
872 if (historyBuffer[tid].empty()) {
873 return;
874 }
875
876 // Go through the most recent instructions, undoing the mappings
877 // they did and freeing up the registers.
878 while (!historyBuffer[tid].empty() &&
879 (*hb_it).instSeqNum > squashed_seq_num) {
880 assert(hb_it != historyBuffer[tid].end());
881
882 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
883 "number %i.\n", tid, (*hb_it).instSeqNum);
884
885 // Tell the rename map to set the architected register to the
886 // previous physical register that it was renamed to.
887 renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
888
889 // Put the renamed physical register back on the free list.
890 freeList->addReg(hb_it->newPhysReg);
891
892 historyBuffer[tid].erase(hb_it++);
893
894 ++renameUndoneMaps;
895 }
896}
897
898template<class Impl>
899void
900DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, unsigned tid)
901{
902 DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the "
903 "history buffer %u (size=%i), until [sn:%lli].\n",
904 tid, tid, historyBuffer[tid].size(), inst_seq_num);
905
906 typename std::list<RenameHistory>::iterator hb_it =
907 historyBuffer[tid].end();
908
909 --hb_it;
910
911 if (historyBuffer[tid].empty()) {
912 DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid);
913 return;
914 } else if (hb_it->instSeqNum > inst_seq_num) {
915 DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure "
916 "that a syscall happened recently.\n", tid);
917 return;
918 }
919
920 // Commit all the renames up until (and including) the committed sequence
921 // number. Some or even all of the committed instructions may not have
922 // rename histories if they did not have destination registers that were
923 // renamed.
924 while (!historyBuffer[tid].empty() &&
925 hb_it != historyBuffer[tid].end() &&
926 (*hb_it).instSeqNum <= inst_seq_num) {
927
928 DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, "
929 "[sn:%lli].\n",
930 tid, (*hb_it).prevPhysReg, (*hb_it).instSeqNum);
931
932 freeList->addReg((*hb_it).prevPhysReg);
933 ++renameCommittedMaps;
934
935 historyBuffer[tid].erase(hb_it--);
936 }
937}
938
939template <class Impl>
940inline void
941DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst,unsigned tid)
942{
943 assert(renameMap[tid] != 0);
944
945 unsigned num_src_regs = inst->numSrcRegs();
946
947 // Get the architectual register numbers from the source and
948 // destination operands, and redirect them to the right register.
949 // Will need to mark dependencies though.
950 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) {
951 RegIndex src_reg = inst->srcRegIdx(src_idx);
952
953 // Look up the source registers to get the phys. register they've
954 // been renamed to, and set the sources to those registers.
955 PhysRegIndex renamed_reg = renameMap[tid]->lookup(src_reg);
956
957 DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got "
958 "physical reg %i.\n", tid, (int)src_reg,
959 (int)renamed_reg);
960
961 inst->renameSrcReg(src_idx, renamed_reg);
962
963 // See if the register is ready or not.
964 if (scoreboard->getReg(renamed_reg) == true) {
965 DPRINTF(Rename, "[tid:%u]: Register is ready.\n", tid);
966
967 inst->markSrcRegReady(src_idx);
968 }
969
970 ++renameRenameLookups;
971 }
972}
973
974template <class Impl>
975inline void
976DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst,unsigned tid)
977{
978 typename RenameMap::RenameInfo rename_result;
979
980 unsigned num_dest_regs = inst->numDestRegs();
981
982 // Rename the destination registers.
983 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) {
984 RegIndex dest_reg = inst->destRegIdx(dest_idx);
985
986 // Get the physical register that the destination will be
987 // renamed to.
988 rename_result = renameMap[tid]->rename(dest_reg);
989
990 //Mark Scoreboard entry as not ready
991 scoreboard->unsetReg(rename_result.first);
992
993 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical "
994 "reg %i.\n", tid, (int)dest_reg,
995 (int)rename_result.first);
996
997 // Record the rename information so that a history can be kept.
998 RenameHistory hb_entry(inst->seqNum, dest_reg,
999 rename_result.first,
1000 rename_result.second);
1001
1002 historyBuffer[tid].push_front(hb_entry);
1003
1004 DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer "
1005 "(size=%i), [sn:%lli].\n",tid,
1006 historyBuffer[tid].size(),
1007 (*historyBuffer[tid].begin()).instSeqNum);
1008
1009 // Tell the instruction to rename the appropriate destination
1010 // register (dest_idx) to the new physical register
1011 // (rename_result.first), and record the previous physical
1012 // register that the same logical register was renamed to
1013 // (rename_result.second).
1014 inst->renameDestReg(dest_idx,
1015 rename_result.first,
1016 rename_result.second);
1017
1018 ++renameRenamedOperands;
1019 }
1020}
1021
1022template <class Impl>
1023inline int
1024DefaultRename<Impl>::calcFreeROBEntries(unsigned tid)
1025{
1026 int num_free = freeEntries[tid].robEntries -
1027 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1028
1029 //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free);
1030
1031 return num_free;
1032}
1033
1034template <class Impl>
1035inline int
1036DefaultRename<Impl>::calcFreeIQEntries(unsigned tid)
1037{
1038 int num_free = freeEntries[tid].iqEntries -
1039 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1040
1041 //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free);
1042
1043 return num_free;
1044}
1045
1046template <class Impl>
1047inline int
1048DefaultRename<Impl>::calcFreeLSQEntries(unsigned tid)
1049{
1050 int num_free = freeEntries[tid].lsqEntries -
1051 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ);
1052
1053 //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free);
1054
1055 return num_free;
1056}
1057
1058template <class Impl>
1059unsigned
1060DefaultRename<Impl>::validInsts()
1061{
1062 unsigned inst_count = 0;
1063
1064 for (int i=0; i<fromDecode->size; i++) {
1065 if (!fromDecode->insts[i]->isSquashed())
1066 inst_count++;
1067 }
1068
1069 return inst_count;
1070}
1071
1072template <class Impl>
1073void
1074DefaultRename<Impl>::readStallSignals(unsigned tid)
1075{
1076 if (fromIEW->iewBlock[tid]) {
1077 stalls[tid].iew = true;
1078 }
1079
1080 if (fromIEW->iewUnblock[tid]) {
1081 assert(stalls[tid].iew);
1082 stalls[tid].iew = false;
1083 }
1084
1085 if (fromCommit->commitBlock[tid]) {
1086 stalls[tid].commit = true;
1087 }
1088
1089 if (fromCommit->commitUnblock[tid]) {
1090 assert(stalls[tid].commit);
1091 stalls[tid].commit = false;
1092 }
1093}
1094
1095template <class Impl>
1096bool
1097DefaultRename<Impl>::checkStall(unsigned tid)
1098{
1099 bool ret_val = false;
1100
1101 if (stalls[tid].iew) {
1102 DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid);
1103 ret_val = true;
1104 } else if (stalls[tid].commit) {
1105 DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid);
1106 ret_val = true;
1107 } else if (calcFreeROBEntries(tid) <= 0) {
1108 DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid);
1109 ret_val = true;
1110 } else if (calcFreeIQEntries(tid) <= 0) {
1111 DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid);
1112 ret_val = true;
1113 } else if (calcFreeLSQEntries(tid) <= 0) {
1114 DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid);
1115 ret_val = true;
1116 } else if (renameMap[tid]->numFreeEntries() <= 0) {
1117 DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid);
1118 ret_val = true;
1119 } else if (renameStatus[tid] == SerializeStall &&
1120 (!emptyROB[tid] || instsInProgress[tid])) {
1121 DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not "
1122 "empty.\n",
1123 tid);
1124 ret_val = true;
1125 }
1126
1127 return ret_val;
1128}
1129
1130template <class Impl>
1131void
1132DefaultRename<Impl>::readFreeEntries(unsigned tid)
1133{
1134 bool updated = false;
1135 if (fromIEW->iewInfo[tid].usedIQ) {
1136 freeEntries[tid].iqEntries =
1137 fromIEW->iewInfo[tid].freeIQEntries;
1138 updated = true;
1139 }
1140
1141 if (fromIEW->iewInfo[tid].usedLSQ) {
1142 freeEntries[tid].lsqEntries =
1143 fromIEW->iewInfo[tid].freeLSQEntries;
1144 updated = true;
1145 }
1146
1147 if (fromCommit->commitInfo[tid].usedROB) {
1148 freeEntries[tid].robEntries =
1149 fromCommit->commitInfo[tid].freeROBEntries;
1150 emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB;
1151 updated = true;
1152 }
1153
1154 DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n",
1155 tid,
1156 freeEntries[tid].iqEntries,
1157 freeEntries[tid].robEntries,
1158 freeEntries[tid].lsqEntries);
1159
1160 DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n",
1161 tid, instsInProgress[tid]);
1162}
1163
1164template <class Impl>
1165bool
1166DefaultRename<Impl>::checkSignalsAndUpdate(unsigned tid)
1167{
1168 // Check if there's a squash signal, squash if there is
1169 // Check stall signals, block if necessary.
1170 // If status was blocked
1171 // check if stall conditions have passed
1172 // if so then go to unblocking
1173 // If status was Squashing
1174 // check if squashing is not high. Switch to running this cycle.
1175 // If status was serialize stall
1176 // check if ROB is empty and no insts are in flight to the ROB
1177
1178 readFreeEntries(tid);
1179 readStallSignals(tid);
1180
1181 if (fromCommit->commitInfo[tid].squash) {
1182 DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from "
1183 "commit.\n", tid);
1184
|
1185#if THE_ISA == ALPHA_ISA
1186 InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].doneSeqNum;
1187#else
| 1185#if ISA_HAS_DELAY_SLOT
|
1188 InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
| 1186 InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
|
| 1187#else
1188 InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].doneSeqNum;
|
1189#endif
1190
1191 squash(squashed_seq_num, tid);
1192
1193 return true;
1194 }
1195
1196 if (fromCommit->commitInfo[tid].robSquashing) {
1197 DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid);
1198
1199 renameStatus[tid] = Squashing;
1200
1201 return true;
1202 }
1203
1204 if (checkStall(tid)) {
1205 return block(tid);
1206 }
1207
1208 if (renameStatus[tid] == Blocked) {
1209 DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n",
1210 tid);
1211
1212 renameStatus[tid] = Unblocking;
1213
1214 unblock(tid);
1215
1216 return true;
1217 }
1218
1219 if (renameStatus[tid] == Squashing) {
1220 // Switch status to running if rename isn't being told to block or
1221 // squash this cycle.
1222 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n",
1223 tid);
1224
1225 renameStatus[tid] = Running;
1226
1227 return false;
1228 }
1229
1230 if (renameStatus[tid] == SerializeStall) {
1231 // Stall ends once the ROB is free.
1232 DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to "
1233 "unblocking.\n", tid);
1234
1235 DynInstPtr serial_inst = serializeInst[tid];
1236
1237 renameStatus[tid] = Unblocking;
1238
1239 unblock(tid);
1240
1241 DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with "
1242 "PC %#x.\n",
1243 tid, serial_inst->seqNum, serial_inst->readPC());
1244
1245 // Put instruction into queue here.
1246 serial_inst->clearSerializeBefore();
1247
1248 if (!skidBuffer[tid].empty()) {
1249 skidBuffer[tid].push_front(serial_inst);
1250 } else {
1251 insts[tid].push_front(serial_inst);
1252 }
1253
1254 DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename."
1255 " Adding to front of list.\n", tid);
1256
1257 serializeInst[tid] = NULL;
1258
1259 return true;
1260 }
1261
1262 // If we've reached this point, we have not gotten any signals that
1263 // cause rename to change its status. Rename remains the same as before.
1264 return false;
1265}
1266
1267template<class Impl>
1268void
1269DefaultRename<Impl>::serializeAfter(InstQueue &inst_list,
1270 unsigned tid)
1271{
1272 if (inst_list.empty()) {
1273 // Mark a bit to say that I must serialize on the next instruction.
1274 serializeOnNextInst[tid] = true;
1275 return;
1276 }
1277
1278 // Set the next instruction as serializing.
1279 inst_list.front()->setSerializeBefore();
1280}
1281
1282template <class Impl>
1283inline void
1284DefaultRename<Impl>::incrFullStat(const FullSource &source)
1285{
1286 switch (source) {
1287 case ROB:
1288 ++renameROBFullEvents;
1289 break;
1290 case IQ:
1291 ++renameIQFullEvents;
1292 break;
1293 case LSQ:
1294 ++renameLSQFullEvents;
1295 break;
1296 default:
1297 panic("Rename full stall stat should be incremented for a reason!");
1298 break;
1299 }
1300}
1301
1302template <class Impl>
1303void
1304DefaultRename<Impl>::dumpHistory()
1305{
1306 typename std::list<RenameHistory>::iterator buf_it;
1307
1308 for (int i = 0; i < numThreads; i++) {
1309
1310 buf_it = historyBuffer[i].begin();
1311
1312 while (buf_it != historyBuffer[i].end()) {
1313 cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys "
1314 "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg,
1315 (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg);
1316
1317 buf_it++;
1318 }
1319 }
1320}
| 1189#endif
1190
1191 squash(squashed_seq_num, tid);
1192
1193 return true;
1194 }
1195
1196 if (fromCommit->commitInfo[tid].robSquashing) {
1197 DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid);
1198
1199 renameStatus[tid] = Squashing;
1200
1201 return true;
1202 }
1203
1204 if (checkStall(tid)) {
1205 return block(tid);
1206 }
1207
1208 if (renameStatus[tid] == Blocked) {
1209 DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n",
1210 tid);
1211
1212 renameStatus[tid] = Unblocking;
1213
1214 unblock(tid);
1215
1216 return true;
1217 }
1218
1219 if (renameStatus[tid] == Squashing) {
1220 // Switch status to running if rename isn't being told to block or
1221 // squash this cycle.
1222 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n",
1223 tid);
1224
1225 renameStatus[tid] = Running;
1226
1227 return false;
1228 }
1229
1230 if (renameStatus[tid] == SerializeStall) {
1231 // Stall ends once the ROB is free.
1232 DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to "
1233 "unblocking.\n", tid);
1234
1235 DynInstPtr serial_inst = serializeInst[tid];
1236
1237 renameStatus[tid] = Unblocking;
1238
1239 unblock(tid);
1240
1241 DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with "
1242 "PC %#x.\n",
1243 tid, serial_inst->seqNum, serial_inst->readPC());
1244
1245 // Put instruction into queue here.
1246 serial_inst->clearSerializeBefore();
1247
1248 if (!skidBuffer[tid].empty()) {
1249 skidBuffer[tid].push_front(serial_inst);
1250 } else {
1251 insts[tid].push_front(serial_inst);
1252 }
1253
1254 DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename."
1255 " Adding to front of list.\n", tid);
1256
1257 serializeInst[tid] = NULL;
1258
1259 return true;
1260 }
1261
1262 // If we've reached this point, we have not gotten any signals that
1263 // cause rename to change its status. Rename remains the same as before.
1264 return false;
1265}
1266
1267template<class Impl>
1268void
1269DefaultRename<Impl>::serializeAfter(InstQueue &inst_list,
1270 unsigned tid)
1271{
1272 if (inst_list.empty()) {
1273 // Mark a bit to say that I must serialize on the next instruction.
1274 serializeOnNextInst[tid] = true;
1275 return;
1276 }
1277
1278 // Set the next instruction as serializing.
1279 inst_list.front()->setSerializeBefore();
1280}
1281
1282template <class Impl>
1283inline void
1284DefaultRename<Impl>::incrFullStat(const FullSource &source)
1285{
1286 switch (source) {
1287 case ROB:
1288 ++renameROBFullEvents;
1289 break;
1290 case IQ:
1291 ++renameIQFullEvents;
1292 break;
1293 case LSQ:
1294 ++renameLSQFullEvents;
1295 break;
1296 default:
1297 panic("Rename full stall stat should be incremented for a reason!");
1298 break;
1299 }
1300}
1301
1302template <class Impl>
1303void
1304DefaultRename<Impl>::dumpHistory()
1305{
1306 typename std::list<RenameHistory>::iterator buf_it;
1307
1308 for (int i = 0; i < numThreads; i++) {
1309
1310 buf_it = historyBuffer[i].begin();
1311
1312 while (buf_it != historyBuffer[i].end()) {
1313 cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys "
1314 "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg,
1315 (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg);
1316
1317 buf_it++;
1318 }
1319 }
1320}
|