rename_impl.hh (3125:febd811bccc6) | rename_impl.hh (3773:61c53465193d) |
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1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 17 unchanged lines hidden (view full) --- 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 * Korey Sewell 30 */ 31 32#include <list> 33 | 1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 17 unchanged lines hidden (view full) --- 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 * Korey Sewell 30 */ 31 32#include <list> 33 |
34#include "arch/isa_traits.hh" 35#include "arch/regfile.hh" |
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34#include "config/full_system.hh" 35#include "cpu/o3/rename.hh" 36 37template <class Impl> 38DefaultRename<Impl>::DefaultRename(Params *params) 39 : iewToRenameDelay(params->iewToRenameDelay), 40 decodeToRenameDelay(params->decodeToRenameDelay), 41 commitToRenameDelay(params->commitToRenameDelay), --- 913 unchanged lines hidden (view full) --- 955 956 unsigned num_src_regs = inst->numSrcRegs(); 957 958 // Get the architectual register numbers from the source and 959 // destination operands, and redirect them to the right register. 960 // Will need to mark dependencies though. 961 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) { 962 RegIndex src_reg = inst->srcRegIdx(src_idx); | 36#include "config/full_system.hh" 37#include "cpu/o3/rename.hh" 38 39template <class Impl> 40DefaultRename<Impl>::DefaultRename(Params *params) 41 : iewToRenameDelay(params->iewToRenameDelay), 42 decodeToRenameDelay(params->decodeToRenameDelay), 43 commitToRenameDelay(params->commitToRenameDelay), --- 913 unchanged lines hidden (view full) --- 957 958 unsigned num_src_regs = inst->numSrcRegs(); 959 960 // Get the architectual register numbers from the source and 961 // destination operands, and redirect them to the right register. 962 // Will need to mark dependencies though. 963 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) { 964 RegIndex src_reg = inst->srcRegIdx(src_idx); |
965 RegIndex flat_src_reg = src_reg; 966 if (src_reg < TheISA::FP_Base_DepTag) { 967 flat_src_reg = TheISA::flattenIntIndex(inst->tcBase(), src_reg); 968 DPRINTF(Rename, "Flattening index %d to %d.\n", (int)src_reg, (int)flat_src_reg); 969 } 970 inst->flattenSrcReg(src_idx, flat_src_reg); |
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963 964 // Look up the source registers to get the phys. register they've 965 // been renamed to, and set the sources to those registers. | 971 972 // Look up the source registers to get the phys. register they've 973 // been renamed to, and set the sources to those registers. |
966 PhysRegIndex renamed_reg = renameMap[tid]->lookup(src_reg); | 974 PhysRegIndex renamed_reg = renameMap[tid]->lookup(flat_src_reg); |
967 968 DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got " | 975 976 DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got " |
969 "physical reg %i.\n", tid, (int)src_reg, | 977 "physical reg %i.\n", tid, (int)flat_src_reg, |
970 (int)renamed_reg); 971 972 inst->renameSrcReg(src_idx, renamed_reg); 973 974 // See if the register is ready or not. 975 if (scoreboard->getReg(renamed_reg) == true) { 976 DPRINTF(Rename, "[tid:%u]: Register is ready.\n", tid); 977 --- 10 unchanged lines hidden (view full) --- 988{ 989 typename RenameMap::RenameInfo rename_result; 990 991 unsigned num_dest_regs = inst->numDestRegs(); 992 993 // Rename the destination registers. 994 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) { 995 RegIndex dest_reg = inst->destRegIdx(dest_idx); | 978 (int)renamed_reg); 979 980 inst->renameSrcReg(src_idx, renamed_reg); 981 982 // See if the register is ready or not. 983 if (scoreboard->getReg(renamed_reg) == true) { 984 DPRINTF(Rename, "[tid:%u]: Register is ready.\n", tid); 985 --- 10 unchanged lines hidden (view full) --- 996{ 997 typename RenameMap::RenameInfo rename_result; 998 999 unsigned num_dest_regs = inst->numDestRegs(); 1000 1001 // Rename the destination registers. 1002 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) { 1003 RegIndex dest_reg = inst->destRegIdx(dest_idx); |
1004 RegIndex flat_dest_reg = dest_reg; 1005 if (dest_reg < TheISA::FP_Base_DepTag) { 1006 flat_dest_reg = TheISA::flattenIntIndex(inst->tcBase(), dest_reg); 1007 DPRINTF(Rename, "Flattening index %d to %d.\n", (int)dest_reg, (int)flat_dest_reg); 1008 } |
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996 | 1009 |
1010 inst->flattenDestReg(dest_idx, flat_dest_reg); 1011 |
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997 // Get the physical register that the destination will be 998 // renamed to. | 1012 // Get the physical register that the destination will be 1013 // renamed to. |
999 rename_result = renameMap[tid]->rename(dest_reg); | 1014 rename_result = renameMap[tid]->rename(flat_dest_reg); |
1000 1001 //Mark Scoreboard entry as not ready 1002 scoreboard->unsetReg(rename_result.first); 1003 1004 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical " | 1015 1016 //Mark Scoreboard entry as not ready 1017 scoreboard->unsetReg(rename_result.first); 1018 1019 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical " |
1005 "reg %i.\n", tid, (int)dest_reg, | 1020 "reg %i.\n", tid, (int)flat_dest_reg, |
1006 (int)rename_result.first); 1007 1008 // Record the rename information so that a history can be kept. | 1021 (int)rename_result.first); 1022 1023 // Record the rename information so that a history can be kept. |
1009 RenameHistory hb_entry(inst->seqNum, dest_reg, | 1024 RenameHistory hb_entry(inst->seqNum, flat_dest_reg, |
1010 rename_result.first, 1011 rename_result.second); 1012 1013 historyBuffer[tid].push_front(hb_entry); 1014 1015 DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer " 1016 "(size=%i), [sn:%lli].\n",tid, 1017 historyBuffer[tid].size(), --- 314 unchanged lines hidden --- | 1025 rename_result.first, 1026 rename_result.second); 1027 1028 historyBuffer[tid].push_front(hb_entry); 1029 1030 DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer " 1031 "(size=%i), [sn:%lli].\n",tid, 1032 historyBuffer[tid].size(), --- 314 unchanged lines hidden --- |