rename_impl.hh (10172:790a214be1f4) | rename_impl.hh (10239:592f0bb6bd6f) |
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1/* 2 * Copyright (c) 2010-2012 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 117 unchanged lines hidden (view full) --- 126 renameROBFullEvents 127 .name(name() + ".ROBFullEvents") 128 .desc("Number of times rename has blocked due to ROB full") 129 .prereq(renameROBFullEvents); 130 renameIQFullEvents 131 .name(name() + ".IQFullEvents") 132 .desc("Number of times rename has blocked due to IQ full") 133 .prereq(renameIQFullEvents); | 1/* 2 * Copyright (c) 2010-2012 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 117 unchanged lines hidden (view full) --- 126 renameROBFullEvents 127 .name(name() + ".ROBFullEvents") 128 .desc("Number of times rename has blocked due to ROB full") 129 .prereq(renameROBFullEvents); 130 renameIQFullEvents 131 .name(name() + ".IQFullEvents") 132 .desc("Number of times rename has blocked due to IQ full") 133 .prereq(renameIQFullEvents); |
134 renameLSQFullEvents 135 .name(name() + ".LSQFullEvents") 136 .desc("Number of times rename has blocked due to LSQ full") 137 .prereq(renameLSQFullEvents); | 134 renameLQFullEvents 135 .name(name() + ".LQFullEvents") 136 .desc("Number of times rename has blocked due to LQ full") 137 .prereq(renameLQFullEvents); 138 renameSQFullEvents 139 .name(name() + ".SQFullEvents") 140 .desc("Number of times rename has blocked due to SQ full") 141 .prereq(renameSQFullEvents); |
138 renameFullRegistersEvents 139 .name(name() + ".FullRegisterEvents") 140 .desc("Number of times there has been no free registers") 141 .prereq(renameFullRegistersEvents); 142 renameRenamedOperands 143 .name(name() + ".RenamedOperands") 144 .desc("Number of destination operands rename has renamed") 145 .prereq(renameRenamedOperands); --- 86 unchanged lines hidden (view full) --- 232 resumeSerialize = false; 233 resumeUnblocking = false; 234 235 // Grab the number of free entries directly from the stages. 236 for (ThreadID tid = 0; tid < numThreads; tid++) { 237 renameStatus[tid] = Idle; 238 239 freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid); | 142 renameFullRegistersEvents 143 .name(name() + ".FullRegisterEvents") 144 .desc("Number of times there has been no free registers") 145 .prereq(renameFullRegistersEvents); 146 renameRenamedOperands 147 .name(name() + ".RenamedOperands") 148 .desc("Number of destination operands rename has renamed") 149 .prereq(renameRenamedOperands); --- 86 unchanged lines hidden (view full) --- 236 resumeSerialize = false; 237 resumeUnblocking = false; 238 239 // Grab the number of free entries directly from the stages. 240 for (ThreadID tid = 0; tid < numThreads; tid++) { 241 renameStatus[tid] = Idle; 242 243 freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid); |
240 freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid); | 244 freeEntries[tid].lqEntries = iew_ptr->ldstQueue.numFreeLoadEntries(tid); 245 freeEntries[tid].sqEntries = iew_ptr->ldstQueue.numFreeStoreEntries(tid); |
241 freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid); 242 emptyROB[tid] = true; 243 244 stalls[tid].iew = false; 245 stalls[tid].commit = false; 246 serializeInst[tid] = NULL; 247 248 instsInProgress[tid] = 0; | 246 freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid); 247 emptyROB[tid] = true; 248 249 stalls[tid].iew = false; 250 stalls[tid].commit = false; 251 serializeInst[tid] = NULL; 252 253 instsInProgress[tid] = 0; |
254 loadsInProgress[tid] = 0; 255 storesInProgress[tid] = 0; |
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249 250 serializeOnNextInst[tid] = false; 251 } 252} 253 254template<class Impl> 255void 256DefaultRename<Impl>::setActiveThreads(list<ThreadID> *at_ptr) --- 158 unchanged lines hidden (view full) --- 415 removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum, 416 tid); 417 } 418 } 419 420 // @todo: make into updateProgress function 421 for (ThreadID tid = 0; tid < numThreads; tid++) { 422 instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched; | 256 257 serializeOnNextInst[tid] = false; 258 } 259} 260 261template<class Impl> 262void 263DefaultRename<Impl>::setActiveThreads(list<ThreadID> *at_ptr) --- 158 unchanged lines hidden (view full) --- 422 removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum, 423 tid); 424 } 425 } 426 427 // @todo: make into updateProgress function 428 for (ThreadID tid = 0; tid < numThreads; tid++) { 429 instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched; |
423 | 430 loadsInProgress[tid] -= fromIEW->iewInfo[tid].dispatchedToLQ; 431 storesInProgress[tid] -= fromIEW->iewInfo[tid].dispatchedToSQ; 432 assert(loadsInProgress[tid] >= 0); 433 assert(storesInProgress[tid] >= 0); |
424 assert(instsInProgress[tid] >=0); 425 } 426 427} 428 429template<class Impl> 430void 431DefaultRename<Impl>::rename(bool &status_change, ThreadID tid) --- 72 unchanged lines hidden (view full) --- 504 } 505 506 DynInstPtr inst; 507 508 // Will have to do a different calculation for the number of free 509 // entries. 510 int free_rob_entries = calcFreeROBEntries(tid); 511 int free_iq_entries = calcFreeIQEntries(tid); | 434 assert(instsInProgress[tid] >=0); 435 } 436 437} 438 439template<class Impl> 440void 441DefaultRename<Impl>::rename(bool &status_change, ThreadID tid) --- 72 unchanged lines hidden (view full) --- 514 } 515 516 DynInstPtr inst; 517 518 // Will have to do a different calculation for the number of free 519 // entries. 520 int free_rob_entries = calcFreeROBEntries(tid); 521 int free_iq_entries = calcFreeIQEntries(tid); |
512 int free_lsq_entries = calcFreeLSQEntries(tid); | |
513 int min_free_entries = free_rob_entries; 514 515 FullSource source = ROB; 516 517 if (free_iq_entries < min_free_entries) { 518 min_free_entries = free_iq_entries; 519 source = IQ; 520 } 521 | 522 int min_free_entries = free_rob_entries; 523 524 FullSource source = ROB; 525 526 if (free_iq_entries < min_free_entries) { 527 min_free_entries = free_iq_entries; 528 source = IQ; 529 } 530 |
522 if (free_lsq_entries < min_free_entries) { 523 min_free_entries = free_lsq_entries; 524 source = LSQ; 525 } 526 | |
527 // Check if there's any space left. 528 if (min_free_entries <= 0) { | 531 // Check if there's any space left. 532 if (min_free_entries <= 0) { |
529 DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ " | 533 DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/ " |
530 "entries.\n" 531 "ROB has %i free entries.\n" | 534 "entries.\n" 535 "ROB has %i free entries.\n" |
532 "IQ has %i free entries.\n" 533 "LSQ has %i free entries.\n", | 536 "IQ has %i free entries.\n", |
534 tid, 535 free_rob_entries, | 537 tid, 538 free_rob_entries, |
536 free_iq_entries, 537 free_lsq_entries); | 539 free_iq_entries); |
538 539 blockThisCycle = true; 540 541 block(tid); 542 543 incrFullStat(source); 544 545 return; --- 34 unchanged lines hidden (view full) --- 580 581 while (insts_available > 0 && toIEWIndex < renameWidth) { 582 DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid); 583 584 assert(!insts_to_rename.empty()); 585 586 inst = insts_to_rename.front(); 587 | 540 541 blockThisCycle = true; 542 543 block(tid); 544 545 incrFullStat(source); 546 547 return; --- 34 unchanged lines hidden (view full) --- 582 583 while (insts_available > 0 && toIEWIndex < renameWidth) { 584 DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid); 585 586 assert(!insts_to_rename.empty()); 587 588 inst = insts_to_rename.front(); 589 |
590 //For all kind of instructions, check ROB and IQ first 591 //For load instruction, check LQ size and take into account the inflight loads 592 //For store instruction, check SQ size and take into account the inflight stores 593 594 if (inst->isLoad()) { 595 if(calcFreeLQEntries(tid) <= 0) { 596 DPRINTF(Rename, "[tid:%u]: Cannot rename due to no free LQ\n"); 597 source = LQ; 598 incrFullStat(source); 599 break; 600 } 601 } 602 603 if (inst->isStore()) { 604 if(calcFreeSQEntries(tid) <= 0) { 605 DPRINTF(Rename, "[tid:%u]: Cannot rename due to no free SQ\n"); 606 source = SQ; 607 incrFullStat(source); 608 break; 609 } 610 } 611 |
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588 insts_to_rename.pop_front(); 589 590 if (renameStatus[tid] == Unblocking) { 591 DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%s from rename " 592 "skidBuffer\n", tid, inst->seqNum, inst->pcState()); 593 } 594 595 if (inst->isSquashed()) { --- 64 unchanged lines hidden (view full) --- 660 661 serializeAfter(insts_to_rename, tid); 662 } 663 664 renameSrcRegs(inst, inst->threadNumber); 665 666 renameDestRegs(inst, inst->threadNumber); 667 | 612 insts_to_rename.pop_front(); 613 614 if (renameStatus[tid] == Unblocking) { 615 DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%s from rename " 616 "skidBuffer\n", tid, inst->seqNum, inst->pcState()); 617 } 618 619 if (inst->isSquashed()) { --- 64 unchanged lines hidden (view full) --- 684 685 serializeAfter(insts_to_rename, tid); 686 } 687 688 renameSrcRegs(inst, inst->threadNumber); 689 690 renameDestRegs(inst, inst->threadNumber); 691 |
692 if (inst->isLoad()) { 693 loadsInProgress[tid]++; 694 } 695 if (inst->isStore()) { 696 storesInProgress[tid]++; 697 } |
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668 ++renamed_insts; 669 670 671 // Put instruction in rename queue. 672 toIEW->insts[toIEWIndex] = inst; 673 ++(toIEW->size); 674 675 // Increment which instruction we're on. --- 441 unchanged lines hidden (view full) --- 1117 1118 //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free); 1119 1120 return num_free; 1121} 1122 1123template <class Impl> 1124inline int | 698 ++renamed_insts; 699 700 701 // Put instruction in rename queue. 702 toIEW->insts[toIEWIndex] = inst; 703 ++(toIEW->size); 704 705 // Increment which instruction we're on. --- 441 unchanged lines hidden (view full) --- 1147 1148 //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free); 1149 1150 return num_free; 1151} 1152 1153template <class Impl> 1154inline int |
1125DefaultRename<Impl>::calcFreeLSQEntries(ThreadID tid) | 1155DefaultRename |
1126{ | 1156{ |
1127 int num_free = freeEntries[tid].lsqEntries - 1128 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ); | 1157 int num_free = freeEntries[tid].lqEntries - 1158 (loadsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLQ); 1159 DPRINTF(Rename, "calcFreeLQEntries: free lqEntries: %d, loadsInProgress: %d, " 1160 "loads dispatchedToLQ: %d\n", freeEntries[tid].lqEntries, 1161 loadsInProgress[tid], fromIEW->iewInfo[tid].dispatchedToLQ); 1162 return num_free; 1163} |
1129 | 1164 |
1130 //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free); 1131 1132 return num_free; | 1165template <class Impl> 1166inline int 1167DefaultRename<Impl>::calcFreeSQEntries(ThreadID tid) 1168{ 1169 int num_free = freeEntries[tid].sqEntries - 1170 (storesInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToSQ); 1171 DPRINTF(Rename, "calcFreeSQEntries: free sqEntries: %d, storesInProgress: %d, " 1172 "stores dispatchedToSQ: %d\n", freeEntries[tid].sqEntries, 1173 storesInProgress[tid], fromIEW->iewInfo[tid].dispatchedToSQ); 1174 return num_free; |
1133} 1134 1135template <class Impl> 1136unsigned 1137DefaultRename<Impl>::validInsts() 1138{ 1139 unsigned inst_count = 0; 1140 --- 41 unchanged lines hidden (view full) --- 1182 DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid); 1183 ret_val = true; 1184 } else if (calcFreeROBEntries(tid) <= 0) { 1185 DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid); 1186 ret_val = true; 1187 } else if (calcFreeIQEntries(tid) <= 0) { 1188 DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid); 1189 ret_val = true; | 1175} 1176 1177template <class Impl> 1178unsigned 1179DefaultRename<Impl>::validInsts() 1180{ 1181 unsigned inst_count = 0; 1182 --- 41 unchanged lines hidden (view full) --- 1224 DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid); 1225 ret_val = true; 1226 } else if (calcFreeROBEntries(tid) <= 0) { 1227 DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid); 1228 ret_val = true; 1229 } else if (calcFreeIQEntries(tid) <= 0) { 1230 DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid); 1231 ret_val = true; |
1190 } else if (calcFreeLSQEntries(tid) <= 0) { | 1232 } else if (calcFreeLQEntries(tid) <= 0 && calcFreeSQEntries(tid) <= 0) { |
1191 DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid); 1192 ret_val = true; 1193 } else if (renameMap[tid]->numFreeEntries() <= 0) { 1194 DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid); 1195 ret_val = true; 1196 } else if (renameStatus[tid] == SerializeStall && 1197 (!emptyROB[tid] || instsInProgress[tid])) { 1198 DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not " --- 7 unchanged lines hidden (view full) --- 1206 1207template <class Impl> 1208void 1209DefaultRename<Impl>::readFreeEntries(ThreadID tid) 1210{ 1211 if (fromIEW->iewInfo[tid].usedIQ) 1212 freeEntries[tid].iqEntries = fromIEW->iewInfo[tid].freeIQEntries; 1213 | 1233 DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid); 1234 ret_val = true; 1235 } else if (renameMap[tid]->numFreeEntries() <= 0) { 1236 DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid); 1237 ret_val = true; 1238 } else if (renameStatus[tid] == SerializeStall && 1239 (!emptyROB[tid] || instsInProgress[tid])) { 1240 DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not " --- 7 unchanged lines hidden (view full) --- 1248 1249template <class Impl> 1250void 1251DefaultRename<Impl>::readFreeEntries(ThreadID tid) 1252{ 1253 if (fromIEW->iewInfo[tid].usedIQ) 1254 freeEntries[tid].iqEntries = fromIEW->iewInfo[tid].freeIQEntries; 1255 |
1214 if (fromIEW->iewInfo[tid].usedLSQ) 1215 freeEntries[tid].lsqEntries = fromIEW->iewInfo[tid].freeLSQEntries; | 1256 if (fromIEW->iewInfo[tid].usedLSQ) { 1257 freeEntries[tid].lqEntries = fromIEW->iewInfo[tid].freeLQEntries; 1258 freeEntries[tid].sqEntries = fromIEW->iewInfo[tid].freeSQEntries; 1259 } |
1216 1217 if (fromCommit->commitInfo[tid].usedROB) { 1218 freeEntries[tid].robEntries = 1219 fromCommit->commitInfo[tid].freeROBEntries; 1220 emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB; 1221 } 1222 | 1260 1261 if (fromCommit->commitInfo[tid].usedROB) { 1262 freeEntries[tid].robEntries = 1263 fromCommit->commitInfo[tid].freeROBEntries; 1264 emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB; 1265 } 1266 |
1223 DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n", | 1267 DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, " 1268 "Free LQ: %i, Free SQ: %i\n", |
1224 tid, 1225 freeEntries[tid].iqEntries, 1226 freeEntries[tid].robEntries, | 1269 tid, 1270 freeEntries[tid].iqEntries, 1271 freeEntries[tid].robEntries, |
1227 freeEntries[tid].lsqEntries); | 1272 freeEntries[tid].lqEntries, 1273 freeEntries[tid].sqEntries); |
1228 1229 DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n", 1230 tid, instsInProgress[tid]); 1231} 1232 1233template <class Impl> 1234bool 1235DefaultRename<Impl>::checkSignalsAndUpdate(ThreadID tid) --- 122 unchanged lines hidden (view full) --- 1358{ 1359 switch (source) { 1360 case ROB: 1361 ++renameROBFullEvents; 1362 break; 1363 case IQ: 1364 ++renameIQFullEvents; 1365 break; | 1274 1275 DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n", 1276 tid, instsInProgress[tid]); 1277} 1278 1279template <class Impl> 1280bool 1281DefaultRename<Impl>::checkSignalsAndUpdate(ThreadID tid) --- 122 unchanged lines hidden (view full) --- 1404{ 1405 switch (source) { 1406 case ROB: 1407 ++renameROBFullEvents; 1408 break; 1409 case IQ: 1410 ++renameIQFullEvents; 1411 break; |
1366 case LSQ: 1367 ++renameLSQFullEvents; | 1412 case LQ: 1413 ++renameLQFullEvents; |
1368 break; | 1414 break; |
1415 case SQ: 1416 ++renameSQFullEvents; 1417 break; |
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1369 default: 1370 panic("Rename full stall stat should be incremented for a reason!"); 1371 break; 1372 } 1373} 1374 1375template <class Impl> 1376void --- 19 unchanged lines hidden --- | 1418 default: 1419 panic("Rename full stall stat should be incremented for a reason!"); 1420 break; 1421 } 1422} 1423 1424template <class Impl> 1425void --- 19 unchanged lines hidden --- |