1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 * Korey Sewell
43 */
44
45#include <list>
46
47#include "arch/isa_traits.hh"
48#include "arch/registers.hh"
49#include "config/the_isa.hh"
50#include "cpu/o3/rename.hh"
51#include "cpu/reg_class.hh"
52#include "debug/Activity.hh"
53#include "debug/Rename.hh"
54#include "debug/O3PipeView.hh"
55#include "params/DerivO3CPU.hh"
56
57using namespace std;
58
59template <class Impl>
60DefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params)
61 : cpu(_cpu),
62 iewToRenameDelay(params->iewToRenameDelay),
63 decodeToRenameDelay(params->decodeToRenameDelay),
64 commitToRenameDelay(params->commitToRenameDelay),
65 renameWidth(params->renameWidth),
66 commitWidth(params->commitWidth),
67 numThreads(params->numThreads),
68 maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs
69 + params->numPhysCCRegs)
70{
71 // @todo: Make into a parameter.
72 skidBufferMax = (2 * (decodeToRenameDelay * params->decodeWidth)) + renameWidth;
73}
74
75template <class Impl>
76std::string
77DefaultRename<Impl>::name() const
78{
79 return cpu->name() + ".rename";
80}
81
82template <class Impl>
83void
84DefaultRename<Impl>::regStats()
85{
86 renameSquashCycles
87 .name(name() + ".SquashCycles")
88 .desc("Number of cycles rename is squashing")
89 .prereq(renameSquashCycles);
90 renameIdleCycles
91 .name(name() + ".IdleCycles")
92 .desc("Number of cycles rename is idle")
93 .prereq(renameIdleCycles);
94 renameBlockCycles
95 .name(name() + ".BlockCycles")
96 .desc("Number of cycles rename is blocking")
97 .prereq(renameBlockCycles);
98 renameSerializeStallCycles
99 .name(name() + ".serializeStallCycles")
100 .desc("count of cycles rename stalled for serializing inst")
101 .flags(Stats::total);
102 renameRunCycles
103 .name(name() + ".RunCycles")
104 .desc("Number of cycles rename is running")
105 .prereq(renameIdleCycles);
106 renameUnblockCycles
107 .name(name() + ".UnblockCycles")
108 .desc("Number of cycles rename is unblocking")
109 .prereq(renameUnblockCycles);
110 renameRenamedInsts
111 .name(name() + ".RenamedInsts")
112 .desc("Number of instructions processed by rename")
113 .prereq(renameRenamedInsts);
114 renameSquashedInsts
115 .name(name() + ".SquashedInsts")
116 .desc("Number of squashed instructions processed by rename")
117 .prereq(renameSquashedInsts);
118 renameROBFullEvents
119 .name(name() + ".ROBFullEvents")
120 .desc("Number of times rename has blocked due to ROB full")
121 .prereq(renameROBFullEvents);
122 renameIQFullEvents
123 .name(name() + ".IQFullEvents")
124 .desc("Number of times rename has blocked due to IQ full")
125 .prereq(renameIQFullEvents);
126 renameLSQFullEvents
127 .name(name() + ".LSQFullEvents")
128 .desc("Number of times rename has blocked due to LSQ full")
129 .prereq(renameLSQFullEvents);
130 renameFullRegistersEvents
131 .name(name() + ".FullRegisterEvents")
132 .desc("Number of times there has been no free registers")
133 .prereq(renameFullRegistersEvents);
134 renameRenamedOperands
135 .name(name() + ".RenamedOperands")
136 .desc("Number of destination operands rename has renamed")
137 .prereq(renameRenamedOperands);
138 renameRenameLookups
139 .name(name() + ".RenameLookups")
140 .desc("Number of register rename lookups that rename has made")
141 .prereq(renameRenameLookups);
142 renameCommittedMaps
143 .name(name() + ".CommittedMaps")
144 .desc("Number of HB maps that are committed")
145 .prereq(renameCommittedMaps);
146 renameUndoneMaps
147 .name(name() + ".UndoneMaps")
148 .desc("Number of HB maps that are undone due to squashing")
149 .prereq(renameUndoneMaps);
150 renamedSerializing
151 .name(name() + ".serializingInsts")
152 .desc("count of serializing insts renamed")
153 .flags(Stats::total)
154 ;
155 renamedTempSerializing
156 .name(name() + ".tempSerializingInsts")
157 .desc("count of temporary serializing insts renamed")
158 .flags(Stats::total)
159 ;
160 renameSkidInsts
161 .name(name() + ".skidInsts")
162 .desc("count of insts added to the skid buffer")
163 .flags(Stats::total)
164 ;
165 intRenameLookups
166 .name(name() + ".int_rename_lookups")
167 .desc("Number of integer rename lookups")
168 .prereq(intRenameLookups);
169 fpRenameLookups
170 .name(name() + ".fp_rename_lookups")
171 .desc("Number of floating rename lookups")
172 .prereq(fpRenameLookups);
173}
174
175template <class Impl>
176void
177DefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
178{
179 timeBuffer = tb_ptr;
180
181 // Setup wire to read information from time buffer, from IEW stage.
182 fromIEW = timeBuffer->getWire(-iewToRenameDelay);
183
184 // Setup wire to read infromation from time buffer, from commit stage.
185 fromCommit = timeBuffer->getWire(-commitToRenameDelay);
186
187 // Setup wire to write information to previous stages.
188 toDecode = timeBuffer->getWire(0);
189}
190
191template <class Impl>
192void
193DefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
194{
195 renameQueue = rq_ptr;
196
197 // Setup wire to write information to future stages.
198 toIEW = renameQueue->getWire(0);
199}
200
201template <class Impl>
202void
203DefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
204{
205 decodeQueue = dq_ptr;
206
207 // Setup wire to get information from decode.
208 fromDecode = decodeQueue->getWire(-decodeToRenameDelay);
209}
210
211template <class Impl>
212void
213DefaultRename<Impl>::startupStage()
214{
215 resetStage();
216}
217
218template <class Impl>
219void
220DefaultRename<Impl>::resetStage()
221{
222 _status = Inactive;
223
224 resumeSerialize = false;
225 resumeUnblocking = false;
226
227 // Grab the number of free entries directly from the stages.
228 for (ThreadID tid = 0; tid < numThreads; tid++) {
229 renameStatus[tid] = Idle;
230
231 freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid);
232 freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid);
233 freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid);
234 emptyROB[tid] = true;
235
236 stalls[tid].iew = false;
237 stalls[tid].commit = false;
238 serializeInst[tid] = NULL;
239
240 instsInProgress[tid] = 0;
241
242 serializeOnNextInst[tid] = false;
243 }
244}
245
246template<class Impl>
247void
248DefaultRename<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
249{
250 activeThreads = at_ptr;
251}
252
253
254template <class Impl>
255void
256DefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[])
257{
258 for (ThreadID tid = 0; tid < numThreads; tid++)
259 renameMap[tid] = &rm_ptr[tid];
260}
261
262template <class Impl>
263void
264DefaultRename<Impl>::setFreeList(FreeList *fl_ptr)
265{
266 freeList = fl_ptr;
267}
268
269template<class Impl>
270void
271DefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard)
272{
273 scoreboard = _scoreboard;
274}
275
276template <class Impl>
277bool
278DefaultRename<Impl>::isDrained() const
279{
280 for (ThreadID tid = 0; tid < numThreads; tid++) {
281 if (instsInProgress[tid] != 0 ||
282 !historyBuffer[tid].empty() ||
283 !skidBuffer[tid].empty() ||
284 !insts[tid].empty())
285 return false;
286 }
287 return true;
288}
289
290template <class Impl>
291void
292DefaultRename<Impl>::takeOverFrom()
293{
294 resetStage();
295}
296
297template <class Impl>
298void
299DefaultRename<Impl>::drainSanityCheck() const
300{
301 for (ThreadID tid = 0; tid < numThreads; tid++) {
302 assert(historyBuffer[tid].empty());
303 assert(insts[tid].empty());
304 assert(skidBuffer[tid].empty());
305 assert(instsInProgress[tid] == 0);
306 }
307}
308
309template <class Impl>
310void
311DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, ThreadID tid)
312{
313 DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid);
314
315 // Clear the stall signal if rename was blocked or unblocking before.
316 // If it still needs to block, the blocking should happen the next
317 // cycle and there should be space to hold everything due to the squash.
318 if (renameStatus[tid] == Blocked ||
319 renameStatus[tid] == Unblocking) {
320 toDecode->renameUnblock[tid] = 1;
321
322 resumeSerialize = false;
323 serializeInst[tid] = NULL;
324 } else if (renameStatus[tid] == SerializeStall) {
325 if (serializeInst[tid]->seqNum <= squash_seq_num) {
326 DPRINTF(Rename, "Rename will resume serializing after squash\n");
327 resumeSerialize = true;
328 assert(serializeInst[tid]);
329 } else {
330 resumeSerialize = false;
331 toDecode->renameUnblock[tid] = 1;
332
333 serializeInst[tid] = NULL;
334 }
335 }
336
337 // Set the status to Squashing.
338 renameStatus[tid] = Squashing;
339
340 // Squash any instructions from decode.
341 for (int i=0; i<fromDecode->size; i++) {
342 if (fromDecode->insts[i]->threadNumber == tid &&
343 fromDecode->insts[i]->seqNum > squash_seq_num) {
344 fromDecode->insts[i]->setSquashed();
345 wroteToTimeBuffer = true;
346 }
347
348 }
349
350 // Clear the instruction list and skid buffer in case they have any
351 // insts in them.
352 insts[tid].clear();
353
354 // Clear the skid buffer in case it has any data in it.
355 skidBuffer[tid].clear();
356
357 doSquash(squash_seq_num, tid);
358}
359
360template <class Impl>
361void
362DefaultRename<Impl>::tick()
363{
364 wroteToTimeBuffer = false;
365
366 blockThisCycle = false;
367
368 bool status_change = false;
369
370 toIEWIndex = 0;
371
372 sortInsts();
373
374 list<ThreadID>::iterator threads = activeThreads->begin();
375 list<ThreadID>::iterator end = activeThreads->end();
376
377 // Check stall and squash signals.
378 while (threads != end) {
379 ThreadID tid = *threads++;
380
381 DPRINTF(Rename, "Processing [tid:%i]\n", tid);
382
383 status_change = checkSignalsAndUpdate(tid) || status_change;
384
385 rename(status_change, tid);
386 }
387
388 if (status_change) {
389 updateStatus();
390 }
391
392 if (wroteToTimeBuffer) {
393 DPRINTF(Activity, "Activity this cycle.\n");
394 cpu->activityThisCycle();
395 }
396
397 threads = activeThreads->begin();
398
399 while (threads != end) {
400 ThreadID tid = *threads++;
401
402 // If we committed this cycle then doneSeqNum will be > 0
403 if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
404 !fromCommit->commitInfo[tid].squash &&
405 renameStatus[tid] != Squashing) {
406
407 removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum,
408 tid);
409 }
410 }
411
412 // @todo: make into updateProgress function
413 for (ThreadID tid = 0; tid < numThreads; tid++) {
414 instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched;
415
416 assert(instsInProgress[tid] >=0);
417 }
418
419}
420
421template<class Impl>
422void
423DefaultRename<Impl>::rename(bool &status_change, ThreadID tid)
424{
425 // If status is Running or idle,
426 // call renameInsts()
427 // If status is Unblocking,
428 // buffer any instructions coming from decode
429 // continue trying to empty skid buffer
430 // check if stall conditions have passed
431
432 if (renameStatus[tid] == Blocked) {
433 ++renameBlockCycles;
434 } else if (renameStatus[tid] == Squashing) {
435 ++renameSquashCycles;
436 } else if (renameStatus[tid] == SerializeStall) {
437 ++renameSerializeStallCycles;
438 // If we are currently in SerializeStall and resumeSerialize
439 // was set, then that means that we are resuming serializing
440 // this cycle. Tell the previous stages to block.
441 if (resumeSerialize) {
442 resumeSerialize = false;
443 block(tid);
444 toDecode->renameUnblock[tid] = false;
445 }
446 } else if (renameStatus[tid] == Unblocking) {
447 if (resumeUnblocking) {
448 block(tid);
449 resumeUnblocking = false;
450 toDecode->renameUnblock[tid] = false;
451 }
452 }
453
454 if (renameStatus[tid] == Running ||
455 renameStatus[tid] == Idle) {
456 DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run "
457 "stage.\n", tid);
458
459 renameInsts(tid);
460 } else if (renameStatus[tid] == Unblocking) {
461 renameInsts(tid);
462
463 if (validInsts()) {
464 // Add the current inputs to the skid buffer so they can be
465 // reprocessed when this stage unblocks.
466 skidInsert(tid);
467 }
468
469 // If we switched over to blocking, then there's a potential for
470 // an overall status change.
471 status_change = unblock(tid) || status_change || blockThisCycle;
472 }
473}
474
475template <class Impl>
476void
477DefaultRename<Impl>::renameInsts(ThreadID tid)
478{
479 // Instructions can be either in the skid buffer or the queue of
480 // instructions coming from decode, depending on the status.
481 int insts_available = renameStatus[tid] == Unblocking ?
482 skidBuffer[tid].size() : insts[tid].size();
483
484 // Check the decode queue to see if instructions are available.
485 // If there are no available instructions to rename, then do nothing.
486 if (insts_available == 0) {
487 DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n",
488 tid);
489 // Should I change status to idle?
490 ++renameIdleCycles;
491 return;
492 } else if (renameStatus[tid] == Unblocking) {
493 ++renameUnblockCycles;
494 } else if (renameStatus[tid] == Running) {
495 ++renameRunCycles;
496 }
497
498 DynInstPtr inst;
499
500 // Will have to do a different calculation for the number of free
501 // entries.
502 int free_rob_entries = calcFreeROBEntries(tid);
503 int free_iq_entries = calcFreeIQEntries(tid);
504 int free_lsq_entries = calcFreeLSQEntries(tid);
505 int min_free_entries = free_rob_entries;
506
507 FullSource source = ROB;
508
509 if (free_iq_entries < min_free_entries) {
510 min_free_entries = free_iq_entries;
511 source = IQ;
512 }
513
514 if (free_lsq_entries < min_free_entries) {
515 min_free_entries = free_lsq_entries;
516 source = LSQ;
517 }
518
519 // Check if there's any space left.
520 if (min_free_entries <= 0) {
521 DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ "
522 "entries.\n"
523 "ROB has %i free entries.\n"
524 "IQ has %i free entries.\n"
525 "LSQ has %i free entries.\n",
526 tid,
527 free_rob_entries,
528 free_iq_entries,
529 free_lsq_entries);
530
531 blockThisCycle = true;
532
533 block(tid);
534
535 incrFullStat(source);
536
537 return;
538 } else if (min_free_entries < insts_available) {
539 DPRINTF(Rename, "[tid:%u]: Will have to block this cycle."
540 "%i insts available, but only %i insts can be "
541 "renamed due to ROB/IQ/LSQ limits.\n",
542 tid, insts_available, min_free_entries);
543
544 insts_available = min_free_entries;
545
546 blockThisCycle = true;
547
548 incrFullStat(source);
549 }
550
551 InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ?
552 skidBuffer[tid] : insts[tid];
553
554 DPRINTF(Rename, "[tid:%u]: %i available instructions to "
555 "send iew.\n", tid, insts_available);
556
557 DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts "
558 "dispatched to IQ last cycle.\n",
559 tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched);
560
561 // Handle serializing the next instruction if necessary.
562 if (serializeOnNextInst[tid]) {
563 if (emptyROB[tid] && instsInProgress[tid] == 0) {
564 // ROB already empty; no need to serialize.
565 serializeOnNextInst[tid] = false;
566 } else if (!insts_to_rename.empty()) {
567 insts_to_rename.front()->setSerializeBefore();
568 }
569 }
570
571 int renamed_insts = 0;
572
573 while (insts_available > 0 && toIEWIndex < renameWidth) {
574 DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid);
575
576 assert(!insts_to_rename.empty());
577
578 inst = insts_to_rename.front();
579
580 insts_to_rename.pop_front();
581
582 if (renameStatus[tid] == Unblocking) {
583 DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%s from rename "
584 "skidBuffer\n", tid, inst->seqNum, inst->pcState());
585 }
586
587 if (inst->isSquashed()) {
588 DPRINTF(Rename, "[tid:%u]: instruction %i with PC %s is "
589 "squashed, skipping.\n", tid, inst->seqNum,
590 inst->pcState());
591
592 ++renameSquashedInsts;
593
594 // Decrement how many instructions are available.
595 --insts_available;
596
597 continue;
598 }
599
600 DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with "
601 "PC %s.\n", tid, inst->seqNum, inst->pcState());
602
603 // Check here to make sure there are enough destination registers
604 // to rename to. Otherwise block.
605 if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) {
606 DPRINTF(Rename, "Blocking due to lack of free "
607 "physical registers to rename to.\n");
608 blockThisCycle = true;
609 insts_to_rename.push_front(inst);
610 ++renameFullRegistersEvents;
611
612 break;
613 }
614
615 // Handle serializeAfter/serializeBefore instructions.
616 // serializeAfter marks the next instruction as serializeBefore.
617 // serializeBefore makes the instruction wait in rename until the ROB
618 // is empty.
619
620 // In this model, IPR accesses are serialize before
621 // instructions, and store conditionals are serialize after
622 // instructions. This is mainly due to lack of support for
623 // out-of-order operations of either of those classes of
624 // instructions.
625 if ((inst->isIprAccess() || inst->isSerializeBefore()) &&
626 !inst->isSerializeHandled()) {
627 DPRINTF(Rename, "Serialize before instruction encountered.\n");
628
629 if (!inst->isTempSerializeBefore()) {
630 renamedSerializing++;
631 inst->setSerializeHandled();
632 } else {
633 renamedTempSerializing++;
634 }
635
636 // Change status over to SerializeStall so that other stages know
637 // what this is blocked on.
638 renameStatus[tid] = SerializeStall;
639
640 serializeInst[tid] = inst;
641
642 blockThisCycle = true;
643
644 break;
645 } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) &&
646 !inst->isSerializeHandled()) {
647 DPRINTF(Rename, "Serialize after instruction encountered.\n");
648
649 renamedSerializing++;
650
651 inst->setSerializeHandled();
652
653 serializeAfter(insts_to_rename, tid);
654 }
655
656 renameSrcRegs(inst, inst->threadNumber);
657
658 renameDestRegs(inst, inst->threadNumber);
659
660 ++renamed_insts;
661
662
663 // Put instruction in rename queue.
664 toIEW->insts[toIEWIndex] = inst;
665 ++(toIEW->size);
666
667 // Increment which instruction we're on.
668 ++toIEWIndex;
669
670 // Decrement how many instructions are available.
671 --insts_available;
672 }
673
674 instsInProgress[tid] += renamed_insts;
675 renameRenamedInsts += renamed_insts;
676
677 // If we wrote to the time buffer, record this.
678 if (toIEWIndex) {
679 wroteToTimeBuffer = true;
680 }
681
682 // Check if there's any instructions left that haven't yet been renamed.
683 // If so then block.
684 if (insts_available) {
685 blockThisCycle = true;
686 }
687
688 if (blockThisCycle) {
689 block(tid);
690 toDecode->renameUnblock[tid] = false;
691 }
692}
693
694template<class Impl>
695void
696DefaultRename<Impl>::skidInsert(ThreadID tid)
697{
698 DynInstPtr inst = NULL;
699
700 while (!insts[tid].empty()) {
701 inst = insts[tid].front();
702
703 insts[tid].pop_front();
704
705 assert(tid == inst->threadNumber);
706
707 DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC: %s into Rename "
708 "skidBuffer\n", tid, inst->seqNum, inst->pcState());
709
710 ++renameSkidInsts;
711
712 skidBuffer[tid].push_back(inst);
713 }
714
715 if (skidBuffer[tid].size() > skidBufferMax)
716 {
717 typename InstQueue::iterator it;
718 warn("Skidbuffer contents:\n");
719 for(it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++)
720 {
721 warn("[tid:%u]: %s [sn:%i].\n", tid,
722 (*it)->staticInst->disassemble(inst->instAddr()),
723 (*it)->seqNum);
724 }
725 panic("Skidbuffer Exceeded Max Size");
726 }
727}
728
729template <class Impl>
730void
731DefaultRename<Impl>::sortInsts()
732{
733 int insts_from_decode = fromDecode->size;
734 for (int i = 0; i < insts_from_decode; ++i) {
735 DynInstPtr inst = fromDecode->insts[i];
736 insts[inst->threadNumber].push_back(inst);
737#if TRACING_ON
738 if (DTRACE(O3PipeView)) {
739 inst->renameTick = curTick() - inst->fetchTick;
740 }
741#endif
742 }
743}
744
745template<class Impl>
746bool
747DefaultRename<Impl>::skidsEmpty()
748{
749 list<ThreadID>::iterator threads = activeThreads->begin();
750 list<ThreadID>::iterator end = activeThreads->end();
751
752 while (threads != end) {
753 ThreadID tid = *threads++;
754
755 if (!skidBuffer[tid].empty())
756 return false;
757 }
758
759 return true;
760}
761
762template<class Impl>
763void
764DefaultRename<Impl>::updateStatus()
765{
766 bool any_unblocking = false;
767
768 list<ThreadID>::iterator threads = activeThreads->begin();
769 list<ThreadID>::iterator end = activeThreads->end();
770
771 while (threads != end) {
772 ThreadID tid = *threads++;
773
774 if (renameStatus[tid] == Unblocking) {
775 any_unblocking = true;
776 break;
777 }
778 }
779
780 // Rename will have activity if it's unblocking.
781 if (any_unblocking) {
782 if (_status == Inactive) {
783 _status = Active;
784
785 DPRINTF(Activity, "Activating stage.\n");
786
787 cpu->activateStage(O3CPU::RenameIdx);
788 }
789 } else {
790 // If it's not unblocking, then rename will not have any internal
791 // activity. Switch it to inactive.
792 if (_status == Active) {
793 _status = Inactive;
794 DPRINTF(Activity, "Deactivating stage.\n");
795
796 cpu->deactivateStage(O3CPU::RenameIdx);
797 }
798 }
799}
800
801template <class Impl>
802bool
803DefaultRename<Impl>::block(ThreadID tid)
804{
805 DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid);
806
807 // Add the current inputs onto the skid buffer, so they can be
808 // reprocessed when this stage unblocks.
809 skidInsert(tid);
810
811 // Only signal backwards to block if the previous stages do not think
812 // rename is already blocked.
813 if (renameStatus[tid] != Blocked) {
814 // If resumeUnblocking is set, we unblocked during the squash,
815 // but now we're have unblocking status. We need to tell earlier
816 // stages to block.
817 if (resumeUnblocking || renameStatus[tid] != Unblocking) {
818 toDecode->renameBlock[tid] = true;
819 toDecode->renameUnblock[tid] = false;
820 wroteToTimeBuffer = true;
821 }
822
823 // Rename can not go from SerializeStall to Blocked, otherwise
824 // it would not know to complete the serialize stall.
825 if (renameStatus[tid] != SerializeStall) {
826 // Set status to Blocked.
827 renameStatus[tid] = Blocked;
828 return true;
829 }
830 }
831
832 return false;
833}
834
835template <class Impl>
836bool
837DefaultRename<Impl>::unblock(ThreadID tid)
838{
839 DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid);
840
841 // Rename is done unblocking if the skid buffer is empty.
842 if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) {
843
844 DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid);
845
846 toDecode->renameUnblock[tid] = true;
847 wroteToTimeBuffer = true;
848
849 renameStatus[tid] = Running;
850 return true;
851 }
852
853 return false;
854}
855
856template <class Impl>
857void
858DefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, ThreadID tid)
859{
860 typename std::list<RenameHistory>::iterator hb_it =
861 historyBuffer[tid].begin();
862
863 // After a syscall squashes everything, the history buffer may be empty
864 // but the ROB may still be squashing instructions.
865 if (historyBuffer[tid].empty()) {
866 return;
867 }
868
869 // Go through the most recent instructions, undoing the mappings
870 // they did and freeing up the registers.
871 while (!historyBuffer[tid].empty() &&
872 hb_it->instSeqNum > squashed_seq_num) {
873 assert(hb_it != historyBuffer[tid].end());
874
875 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
876 "number %i.\n", tid, hb_it->instSeqNum);
877
878 // Undo the rename mapping only if it was really a change.
879 // Special regs that are not really renamed (like misc regs
880 // and the zero reg) can be recognized because the new mapping
881 // is the same as the old one. While it would be merely a
882 // waste of time to update the rename table, we definitely
883 // don't want to put these on the free list.
884 if (hb_it->newPhysReg != hb_it->prevPhysReg) {
885 // Tell the rename map to set the architected register to the
886 // previous physical register that it was renamed to.
887 renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
888
889 // Put the renamed physical register back on the free list.
890 freeList->addReg(hb_it->newPhysReg);
891 }
892
893 historyBuffer[tid].erase(hb_it++);
894
895 ++renameUndoneMaps;
896 }
897}
898
899template<class Impl>
900void
901DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid)
902{
903 DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the "
904 "history buffer %u (size=%i), until [sn:%lli].\n",
905 tid, tid, historyBuffer[tid].size(), inst_seq_num);
906
907 typename std::list<RenameHistory>::iterator hb_it =
908 historyBuffer[tid].end();
909
910 --hb_it;
911
912 if (historyBuffer[tid].empty()) {
913 DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid);
914 return;
915 } else if (hb_it->instSeqNum > inst_seq_num) {
916 DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure "
917 "that a syscall happened recently.\n", tid);
918 return;
919 }
920
921 // Commit all the renames up until (and including) the committed sequence
922 // number. Some or even all of the committed instructions may not have
923 // rename histories if they did not have destination registers that were
924 // renamed.
925 while (!historyBuffer[tid].empty() &&
926 hb_it != historyBuffer[tid].end() &&
927 hb_it->instSeqNum <= inst_seq_num) {
928
929 DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, "
930 "[sn:%lli].\n",
931 tid, hb_it->prevPhysReg, hb_it->instSeqNum);
932
933 // Don't free special phys regs like misc and zero regs, which
934 // can be recognized because the new mapping is the same as
935 // the old one.
936 if (hb_it->newPhysReg != hb_it->prevPhysReg) {
937 freeList->addReg(hb_it->prevPhysReg);
938 }
939
940 ++renameCommittedMaps;
941
942 historyBuffer[tid].erase(hb_it--);
943 }
944}
945
946template <class Impl>
947inline void
948DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid)
949{
950 ThreadContext *tc = inst->tcBase();
951 RenameMap *map = renameMap[tid];
952 unsigned num_src_regs = inst->numSrcRegs();
953
954 // Get the architectual register numbers from the source and
955 // operands, and redirect them to the right physical register.
956 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) {
957 RegIndex src_reg = inst->srcRegIdx(src_idx);
958 RegIndex rel_src_reg;
959 RegIndex flat_rel_src_reg;
960 PhysRegIndex renamed_reg;
961
962 switch (regIdxToClass(src_reg, &rel_src_reg)) {
963 case IntRegClass:
964 flat_rel_src_reg = tc->flattenIntIndex(rel_src_reg);
965 renamed_reg = map->lookupInt(flat_rel_src_reg);
966 intRenameLookups++;
967 break;
968
969 case FloatRegClass:
970 flat_rel_src_reg = tc->flattenFloatIndex(rel_src_reg);
971 renamed_reg = map->lookupFloat(flat_rel_src_reg);
972 fpRenameLookups++;
973 break;
974
975 case CCRegClass:
976 flat_rel_src_reg = tc->flattenCCIndex(rel_src_reg);
977 renamed_reg = map->lookupCC(flat_rel_src_reg);
978 break;
979
980 case MiscRegClass:
981 // misc regs don't get flattened
982 flat_rel_src_reg = rel_src_reg;
983 renamed_reg = map->lookupMisc(flat_rel_src_reg);
984 break;
985
986 default:
987 panic("Reg index is out of bound: %d.", src_reg);
988 }
989
990 DPRINTF(Rename, "[tid:%u]: Looking up %s arch reg %i (flattened %i), "
991 "got phys reg %i\n", tid, RegClassStrings[regIdxToClass(src_reg)],
992 (int)src_reg, (int)flat_rel_src_reg, (int)renamed_reg);
993
994 inst->renameSrcReg(src_idx, renamed_reg);
995
996 // See if the register is ready or not.
997 if (scoreboard->getReg(renamed_reg)) {
998 DPRINTF(Rename, "[tid:%u]: Register %d is ready.\n",
999 tid, renamed_reg);
1000
1001 inst->markSrcRegReady(src_idx);
1002 } else {
1003 DPRINTF(Rename, "[tid:%u]: Register %d is not ready.\n",
1004 tid, renamed_reg);
1005 }
1006
1007 ++renameRenameLookups;
1008 }
1009}
1010
1011template <class Impl>
1012inline void
1013DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid)
1014{
1015 ThreadContext *tc = inst->tcBase();
1016 RenameMap *map = renameMap[tid];
1017 unsigned num_dest_regs = inst->numDestRegs();
1018
1019 // Rename the destination registers.
1020 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) {
1021 RegIndex dest_reg = inst->destRegIdx(dest_idx);
1022 RegIndex rel_dest_reg;
1023 RegIndex flat_rel_dest_reg;
1024 RegIndex flat_uni_dest_reg;
1025 typename RenameMap::RenameInfo rename_result;
1026
1027 switch (regIdxToClass(dest_reg, &rel_dest_reg)) {
1028 case IntRegClass:
1029 flat_rel_dest_reg = tc->flattenIntIndex(rel_dest_reg);
1030 rename_result = map->renameInt(flat_rel_dest_reg);
1031 flat_uni_dest_reg = flat_rel_dest_reg; // 1:1 mapping
1032 break;
1033
1034 case FloatRegClass:
1035 flat_rel_dest_reg = tc->flattenFloatIndex(rel_dest_reg);
1036 rename_result = map->renameFloat(flat_rel_dest_reg);
1037 flat_uni_dest_reg = flat_rel_dest_reg + TheISA::FP_Reg_Base;
1038 break;
1039
1040 case CCRegClass:
1041 flat_rel_dest_reg = tc->flattenCCIndex(rel_dest_reg);
1042 rename_result = map->renameCC(flat_rel_dest_reg);
1043 flat_uni_dest_reg = flat_rel_dest_reg + TheISA::CC_Reg_Base;
1044 break;
1045
1046 case MiscRegClass:
1047 // misc regs don't get flattened
1048 flat_rel_dest_reg = rel_dest_reg;
1049 rename_result = map->renameMisc(flat_rel_dest_reg);
1050 flat_uni_dest_reg = flat_rel_dest_reg + TheISA::Misc_Reg_Base;
1051 break;
1052
1053 default:
1054 panic("Reg index is out of bound: %d.", dest_reg);
1055 }
1056
1057 inst->flattenDestReg(dest_idx, flat_uni_dest_reg);
1058
1059 // Mark Scoreboard entry as not ready
1060 scoreboard->unsetReg(rename_result.first);
1061
1062 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical "
1063 "reg %i.\n", tid, (int)flat_rel_dest_reg,
1064 (int)rename_result.first);
1065
1066 // Record the rename information so that a history can be kept.
1067 RenameHistory hb_entry(inst->seqNum, flat_uni_dest_reg,
1068 rename_result.first,
1069 rename_result.second);
1070
1071 historyBuffer[tid].push_front(hb_entry);
1072
1073 DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer "
1074 "(size=%i), [sn:%lli].\n",tid,
1075 historyBuffer[tid].size(),
1076 (*historyBuffer[tid].begin()).instSeqNum);
1077
1078 // Tell the instruction to rename the appropriate destination
1079 // register (dest_idx) to the new physical register
1080 // (rename_result.first), and record the previous physical
1081 // register that the same logical register was renamed to
1082 // (rename_result.second).
1083 inst->renameDestReg(dest_idx,
1084 rename_result.first,
1085 rename_result.second);
1086
1087 ++renameRenamedOperands;
1088 }
1089}
1090
1091template <class Impl>
1092inline int
1093DefaultRename<Impl>::calcFreeROBEntries(ThreadID tid)
1094{
1095 int num_free = freeEntries[tid].robEntries -
1096 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1097
1098 //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free);
1099
1100 return num_free;
1101}
1102
1103template <class Impl>
1104inline int
1105DefaultRename<Impl>::calcFreeIQEntries(ThreadID tid)
1106{
1107 int num_free = freeEntries[tid].iqEntries -
1108 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1109
1110 //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free);
1111
1112 return num_free;
1113}
1114
1115template <class Impl>
1116inline int
1117DefaultRename<Impl>::calcFreeLSQEntries(ThreadID tid)
1118{
1119 int num_free = freeEntries[tid].lsqEntries -
1120 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ);
1121
1122 //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free);
1123
1124 return num_free;
1125}
1126
1127template <class Impl>
1128unsigned
1129DefaultRename<Impl>::validInsts()
1130{
1131 unsigned inst_count = 0;
1132
1133 for (int i=0; i<fromDecode->size; i++) {
1134 if (!fromDecode->insts[i]->isSquashed())
1135 inst_count++;
1136 }
1137
1138 return inst_count;
1139}
1140
1141template <class Impl>
1142void
1143DefaultRename<Impl>::readStallSignals(ThreadID tid)
1144{
1145 if (fromIEW->iewBlock[tid]) {
1146 stalls[tid].iew = true;
1147 }
1148
1149 if (fromIEW->iewUnblock[tid]) {
1150 assert(stalls[tid].iew);
1151 stalls[tid].iew = false;
1152 }
1153
1154 if (fromCommit->commitBlock[tid]) {
1155 stalls[tid].commit = true;
1156 }
1157
1158 if (fromCommit->commitUnblock[tid]) {
1159 assert(stalls[tid].commit);
1160 stalls[tid].commit = false;
1161 }
1162}
1163
1164template <class Impl>
1165bool
1166DefaultRename<Impl>::checkStall(ThreadID tid)
1167{
1168 bool ret_val = false;
1169
1170 if (stalls[tid].iew) {
1171 DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid);
1172 ret_val = true;
1173 } else if (stalls[tid].commit) {
1174 DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid);
1175 ret_val = true;
1176 } else if (calcFreeROBEntries(tid) <= 0) {
1177 DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid);
1178 ret_val = true;
1179 } else if (calcFreeIQEntries(tid) <= 0) {
1180 DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid);
1181 ret_val = true;
1182 } else if (calcFreeLSQEntries(tid) <= 0) {
1183 DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid);
1184 ret_val = true;
1185 } else if (renameMap[tid]->numFreeEntries() <= 0) {
1186 DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid);
1187 ret_val = true;
1188 } else if (renameStatus[tid] == SerializeStall &&
1189 (!emptyROB[tid] || instsInProgress[tid])) {
1190 DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not "
1191 "empty.\n",
1192 tid);
1193 ret_val = true;
1194 }
1195
1196 return ret_val;
1197}
1198
1199template <class Impl>
1200void
1201DefaultRename<Impl>::readFreeEntries(ThreadID tid)
1202{
1203 if (fromIEW->iewInfo[tid].usedIQ)
1204 freeEntries[tid].iqEntries = fromIEW->iewInfo[tid].freeIQEntries;
1205
1206 if (fromIEW->iewInfo[tid].usedLSQ)
1207 freeEntries[tid].lsqEntries = fromIEW->iewInfo[tid].freeLSQEntries;
1208
1209 if (fromCommit->commitInfo[tid].usedROB) {
1210 freeEntries[tid].robEntries =
1211 fromCommit->commitInfo[tid].freeROBEntries;
1212 emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB;
1213 }
1214
1215 DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n",
1216 tid,
1217 freeEntries[tid].iqEntries,
1218 freeEntries[tid].robEntries,
1219 freeEntries[tid].lsqEntries);
1220
1221 DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n",
1222 tid, instsInProgress[tid]);
1223}
1224
1225template <class Impl>
1226bool
1227DefaultRename<Impl>::checkSignalsAndUpdate(ThreadID tid)
1228{
1229 // Check if there's a squash signal, squash if there is
1230 // Check stall signals, block if necessary.
1231 // If status was blocked
1232 // check if stall conditions have passed
1233 // if so then go to unblocking
1234 // If status was Squashing
1235 // check if squashing is not high. Switch to running this cycle.
1236 // If status was serialize stall
1237 // check if ROB is empty and no insts are in flight to the ROB
1238
1239 readFreeEntries(tid);
1240 readStallSignals(tid);
1241
1242 if (fromCommit->commitInfo[tid].squash) {
1243 DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from "
1244 "commit.\n", tid);
1245
1246 squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
1247
1248 return true;
1249 }
1250
1251 if (fromCommit->commitInfo[tid].robSquashing) {
1252 DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid);
1253
1254 renameStatus[tid] = Squashing;
1255
1256 return true;
1257 }
1258
1259 if (checkStall(tid)) {
1260 return block(tid);
1261 }
1262
1263 if (renameStatus[tid] == Blocked) {
1264 DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n",
1265 tid);
1266
1267 renameStatus[tid] = Unblocking;
1268
1269 unblock(tid);
1270
1271 return true;
1272 }
1273
1274 if (renameStatus[tid] == Squashing) {
1275 // Switch status to running if rename isn't being told to block or
1276 // squash this cycle.
1277 if (resumeSerialize) {
1278 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n",
1279 tid);
1280
1281 renameStatus[tid] = SerializeStall;
1282 return true;
1283 } else if (resumeUnblocking) {
1284 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n",
1285 tid);
1286 renameStatus[tid] = Unblocking;
1287 return true;
1288 } else {
1289 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n",
1290 tid);
1291
1292 renameStatus[tid] = Running;
1293 return false;
1294 }
1295 }
1296
1297 if (renameStatus[tid] == SerializeStall) {
1298 // Stall ends once the ROB is free.
1299 DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to "
1300 "unblocking.\n", tid);
1301
1302 DynInstPtr serial_inst = serializeInst[tid];
1303
1304 renameStatus[tid] = Unblocking;
1305
1306 unblock(tid);
1307
1308 DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with "
1309 "PC %s.\n", tid, serial_inst->seqNum, serial_inst->pcState());
1310
1311 // Put instruction into queue here.
1312 serial_inst->clearSerializeBefore();
1313
1314 if (!skidBuffer[tid].empty()) {
1315 skidBuffer[tid].push_front(serial_inst);
1316 } else {
1317 insts[tid].push_front(serial_inst);
1318 }
1319
1320 DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename."
1321 " Adding to front of list.\n", tid);
1322
1323 serializeInst[tid] = NULL;
1324
1325 return true;
1326 }
1327
1328 // If we've reached this point, we have not gotten any signals that
1329 // cause rename to change its status. Rename remains the same as before.
1330 return false;
1331}
1332
1333template<class Impl>
1334void
1335DefaultRename<Impl>::serializeAfter(InstQueue &inst_list, ThreadID tid)
1336{
1337 if (inst_list.empty()) {
1338 // Mark a bit to say that I must serialize on the next instruction.
1339 serializeOnNextInst[tid] = true;
1340 return;
1341 }
1342
1343 // Set the next instruction as serializing.
1344 inst_list.front()->setSerializeBefore();
1345}
1346
1347template <class Impl>
1348inline void
1349DefaultRename<Impl>::incrFullStat(const FullSource &source)
1350{
1351 switch (source) {
1352 case ROB:
1353 ++renameROBFullEvents;
1354 break;
1355 case IQ:
1356 ++renameIQFullEvents;
1357 break;
1358 case LSQ:
1359 ++renameLSQFullEvents;
1360 break;
1361 default:
1362 panic("Rename full stall stat should be incremented for a reason!");
1363 break;
1364 }
1365}
1366
1367template <class Impl>
1368void
1369DefaultRename<Impl>::dumpHistory()
1370{
1371 typename std::list<RenameHistory>::iterator buf_it;
1372
1373 for (ThreadID tid = 0; tid < numThreads; tid++) {
1374
1375 buf_it = historyBuffer[tid].begin();
1376
1377 while (buf_it != historyBuffer[tid].end()) {
1378 cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys "
1379 "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg,
1380 (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg);
1381
1382 buf_it++;
1383 }
1384 }
1385}
2 * Copyright (c) 2010-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 * Korey Sewell
43 */
44
45#include <list>
46
47#include "arch/isa_traits.hh"
48#include "arch/registers.hh"
49#include "config/the_isa.hh"
50#include "cpu/o3/rename.hh"
51#include "cpu/reg_class.hh"
52#include "debug/Activity.hh"
53#include "debug/Rename.hh"
54#include "debug/O3PipeView.hh"
55#include "params/DerivO3CPU.hh"
56
57using namespace std;
58
59template <class Impl>
60DefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params)
61 : cpu(_cpu),
62 iewToRenameDelay(params->iewToRenameDelay),
63 decodeToRenameDelay(params->decodeToRenameDelay),
64 commitToRenameDelay(params->commitToRenameDelay),
65 renameWidth(params->renameWidth),
66 commitWidth(params->commitWidth),
67 numThreads(params->numThreads),
68 maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs
69 + params->numPhysCCRegs)
70{
71 // @todo: Make into a parameter.
72 skidBufferMax = (2 * (decodeToRenameDelay * params->decodeWidth)) + renameWidth;
73}
74
75template <class Impl>
76std::string
77DefaultRename<Impl>::name() const
78{
79 return cpu->name() + ".rename";
80}
81
82template <class Impl>
83void
84DefaultRename<Impl>::regStats()
85{
86 renameSquashCycles
87 .name(name() + ".SquashCycles")
88 .desc("Number of cycles rename is squashing")
89 .prereq(renameSquashCycles);
90 renameIdleCycles
91 .name(name() + ".IdleCycles")
92 .desc("Number of cycles rename is idle")
93 .prereq(renameIdleCycles);
94 renameBlockCycles
95 .name(name() + ".BlockCycles")
96 .desc("Number of cycles rename is blocking")
97 .prereq(renameBlockCycles);
98 renameSerializeStallCycles
99 .name(name() + ".serializeStallCycles")
100 .desc("count of cycles rename stalled for serializing inst")
101 .flags(Stats::total);
102 renameRunCycles
103 .name(name() + ".RunCycles")
104 .desc("Number of cycles rename is running")
105 .prereq(renameIdleCycles);
106 renameUnblockCycles
107 .name(name() + ".UnblockCycles")
108 .desc("Number of cycles rename is unblocking")
109 .prereq(renameUnblockCycles);
110 renameRenamedInsts
111 .name(name() + ".RenamedInsts")
112 .desc("Number of instructions processed by rename")
113 .prereq(renameRenamedInsts);
114 renameSquashedInsts
115 .name(name() + ".SquashedInsts")
116 .desc("Number of squashed instructions processed by rename")
117 .prereq(renameSquashedInsts);
118 renameROBFullEvents
119 .name(name() + ".ROBFullEvents")
120 .desc("Number of times rename has blocked due to ROB full")
121 .prereq(renameROBFullEvents);
122 renameIQFullEvents
123 .name(name() + ".IQFullEvents")
124 .desc("Number of times rename has blocked due to IQ full")
125 .prereq(renameIQFullEvents);
126 renameLSQFullEvents
127 .name(name() + ".LSQFullEvents")
128 .desc("Number of times rename has blocked due to LSQ full")
129 .prereq(renameLSQFullEvents);
130 renameFullRegistersEvents
131 .name(name() + ".FullRegisterEvents")
132 .desc("Number of times there has been no free registers")
133 .prereq(renameFullRegistersEvents);
134 renameRenamedOperands
135 .name(name() + ".RenamedOperands")
136 .desc("Number of destination operands rename has renamed")
137 .prereq(renameRenamedOperands);
138 renameRenameLookups
139 .name(name() + ".RenameLookups")
140 .desc("Number of register rename lookups that rename has made")
141 .prereq(renameRenameLookups);
142 renameCommittedMaps
143 .name(name() + ".CommittedMaps")
144 .desc("Number of HB maps that are committed")
145 .prereq(renameCommittedMaps);
146 renameUndoneMaps
147 .name(name() + ".UndoneMaps")
148 .desc("Number of HB maps that are undone due to squashing")
149 .prereq(renameUndoneMaps);
150 renamedSerializing
151 .name(name() + ".serializingInsts")
152 .desc("count of serializing insts renamed")
153 .flags(Stats::total)
154 ;
155 renamedTempSerializing
156 .name(name() + ".tempSerializingInsts")
157 .desc("count of temporary serializing insts renamed")
158 .flags(Stats::total)
159 ;
160 renameSkidInsts
161 .name(name() + ".skidInsts")
162 .desc("count of insts added to the skid buffer")
163 .flags(Stats::total)
164 ;
165 intRenameLookups
166 .name(name() + ".int_rename_lookups")
167 .desc("Number of integer rename lookups")
168 .prereq(intRenameLookups);
169 fpRenameLookups
170 .name(name() + ".fp_rename_lookups")
171 .desc("Number of floating rename lookups")
172 .prereq(fpRenameLookups);
173}
174
175template <class Impl>
176void
177DefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
178{
179 timeBuffer = tb_ptr;
180
181 // Setup wire to read information from time buffer, from IEW stage.
182 fromIEW = timeBuffer->getWire(-iewToRenameDelay);
183
184 // Setup wire to read infromation from time buffer, from commit stage.
185 fromCommit = timeBuffer->getWire(-commitToRenameDelay);
186
187 // Setup wire to write information to previous stages.
188 toDecode = timeBuffer->getWire(0);
189}
190
191template <class Impl>
192void
193DefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
194{
195 renameQueue = rq_ptr;
196
197 // Setup wire to write information to future stages.
198 toIEW = renameQueue->getWire(0);
199}
200
201template <class Impl>
202void
203DefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
204{
205 decodeQueue = dq_ptr;
206
207 // Setup wire to get information from decode.
208 fromDecode = decodeQueue->getWire(-decodeToRenameDelay);
209}
210
211template <class Impl>
212void
213DefaultRename<Impl>::startupStage()
214{
215 resetStage();
216}
217
218template <class Impl>
219void
220DefaultRename<Impl>::resetStage()
221{
222 _status = Inactive;
223
224 resumeSerialize = false;
225 resumeUnblocking = false;
226
227 // Grab the number of free entries directly from the stages.
228 for (ThreadID tid = 0; tid < numThreads; tid++) {
229 renameStatus[tid] = Idle;
230
231 freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid);
232 freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid);
233 freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid);
234 emptyROB[tid] = true;
235
236 stalls[tid].iew = false;
237 stalls[tid].commit = false;
238 serializeInst[tid] = NULL;
239
240 instsInProgress[tid] = 0;
241
242 serializeOnNextInst[tid] = false;
243 }
244}
245
246template<class Impl>
247void
248DefaultRename<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
249{
250 activeThreads = at_ptr;
251}
252
253
254template <class Impl>
255void
256DefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[])
257{
258 for (ThreadID tid = 0; tid < numThreads; tid++)
259 renameMap[tid] = &rm_ptr[tid];
260}
261
262template <class Impl>
263void
264DefaultRename<Impl>::setFreeList(FreeList *fl_ptr)
265{
266 freeList = fl_ptr;
267}
268
269template<class Impl>
270void
271DefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard)
272{
273 scoreboard = _scoreboard;
274}
275
276template <class Impl>
277bool
278DefaultRename<Impl>::isDrained() const
279{
280 for (ThreadID tid = 0; tid < numThreads; tid++) {
281 if (instsInProgress[tid] != 0 ||
282 !historyBuffer[tid].empty() ||
283 !skidBuffer[tid].empty() ||
284 !insts[tid].empty())
285 return false;
286 }
287 return true;
288}
289
290template <class Impl>
291void
292DefaultRename<Impl>::takeOverFrom()
293{
294 resetStage();
295}
296
297template <class Impl>
298void
299DefaultRename<Impl>::drainSanityCheck() const
300{
301 for (ThreadID tid = 0; tid < numThreads; tid++) {
302 assert(historyBuffer[tid].empty());
303 assert(insts[tid].empty());
304 assert(skidBuffer[tid].empty());
305 assert(instsInProgress[tid] == 0);
306 }
307}
308
309template <class Impl>
310void
311DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, ThreadID tid)
312{
313 DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid);
314
315 // Clear the stall signal if rename was blocked or unblocking before.
316 // If it still needs to block, the blocking should happen the next
317 // cycle and there should be space to hold everything due to the squash.
318 if (renameStatus[tid] == Blocked ||
319 renameStatus[tid] == Unblocking) {
320 toDecode->renameUnblock[tid] = 1;
321
322 resumeSerialize = false;
323 serializeInst[tid] = NULL;
324 } else if (renameStatus[tid] == SerializeStall) {
325 if (serializeInst[tid]->seqNum <= squash_seq_num) {
326 DPRINTF(Rename, "Rename will resume serializing after squash\n");
327 resumeSerialize = true;
328 assert(serializeInst[tid]);
329 } else {
330 resumeSerialize = false;
331 toDecode->renameUnblock[tid] = 1;
332
333 serializeInst[tid] = NULL;
334 }
335 }
336
337 // Set the status to Squashing.
338 renameStatus[tid] = Squashing;
339
340 // Squash any instructions from decode.
341 for (int i=0; i<fromDecode->size; i++) {
342 if (fromDecode->insts[i]->threadNumber == tid &&
343 fromDecode->insts[i]->seqNum > squash_seq_num) {
344 fromDecode->insts[i]->setSquashed();
345 wroteToTimeBuffer = true;
346 }
347
348 }
349
350 // Clear the instruction list and skid buffer in case they have any
351 // insts in them.
352 insts[tid].clear();
353
354 // Clear the skid buffer in case it has any data in it.
355 skidBuffer[tid].clear();
356
357 doSquash(squash_seq_num, tid);
358}
359
360template <class Impl>
361void
362DefaultRename<Impl>::tick()
363{
364 wroteToTimeBuffer = false;
365
366 blockThisCycle = false;
367
368 bool status_change = false;
369
370 toIEWIndex = 0;
371
372 sortInsts();
373
374 list<ThreadID>::iterator threads = activeThreads->begin();
375 list<ThreadID>::iterator end = activeThreads->end();
376
377 // Check stall and squash signals.
378 while (threads != end) {
379 ThreadID tid = *threads++;
380
381 DPRINTF(Rename, "Processing [tid:%i]\n", tid);
382
383 status_change = checkSignalsAndUpdate(tid) || status_change;
384
385 rename(status_change, tid);
386 }
387
388 if (status_change) {
389 updateStatus();
390 }
391
392 if (wroteToTimeBuffer) {
393 DPRINTF(Activity, "Activity this cycle.\n");
394 cpu->activityThisCycle();
395 }
396
397 threads = activeThreads->begin();
398
399 while (threads != end) {
400 ThreadID tid = *threads++;
401
402 // If we committed this cycle then doneSeqNum will be > 0
403 if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
404 !fromCommit->commitInfo[tid].squash &&
405 renameStatus[tid] != Squashing) {
406
407 removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum,
408 tid);
409 }
410 }
411
412 // @todo: make into updateProgress function
413 for (ThreadID tid = 0; tid < numThreads; tid++) {
414 instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched;
415
416 assert(instsInProgress[tid] >=0);
417 }
418
419}
420
421template<class Impl>
422void
423DefaultRename<Impl>::rename(bool &status_change, ThreadID tid)
424{
425 // If status is Running or idle,
426 // call renameInsts()
427 // If status is Unblocking,
428 // buffer any instructions coming from decode
429 // continue trying to empty skid buffer
430 // check if stall conditions have passed
431
432 if (renameStatus[tid] == Blocked) {
433 ++renameBlockCycles;
434 } else if (renameStatus[tid] == Squashing) {
435 ++renameSquashCycles;
436 } else if (renameStatus[tid] == SerializeStall) {
437 ++renameSerializeStallCycles;
438 // If we are currently in SerializeStall and resumeSerialize
439 // was set, then that means that we are resuming serializing
440 // this cycle. Tell the previous stages to block.
441 if (resumeSerialize) {
442 resumeSerialize = false;
443 block(tid);
444 toDecode->renameUnblock[tid] = false;
445 }
446 } else if (renameStatus[tid] == Unblocking) {
447 if (resumeUnblocking) {
448 block(tid);
449 resumeUnblocking = false;
450 toDecode->renameUnblock[tid] = false;
451 }
452 }
453
454 if (renameStatus[tid] == Running ||
455 renameStatus[tid] == Idle) {
456 DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run "
457 "stage.\n", tid);
458
459 renameInsts(tid);
460 } else if (renameStatus[tid] == Unblocking) {
461 renameInsts(tid);
462
463 if (validInsts()) {
464 // Add the current inputs to the skid buffer so they can be
465 // reprocessed when this stage unblocks.
466 skidInsert(tid);
467 }
468
469 // If we switched over to blocking, then there's a potential for
470 // an overall status change.
471 status_change = unblock(tid) || status_change || blockThisCycle;
472 }
473}
474
475template <class Impl>
476void
477DefaultRename<Impl>::renameInsts(ThreadID tid)
478{
479 // Instructions can be either in the skid buffer or the queue of
480 // instructions coming from decode, depending on the status.
481 int insts_available = renameStatus[tid] == Unblocking ?
482 skidBuffer[tid].size() : insts[tid].size();
483
484 // Check the decode queue to see if instructions are available.
485 // If there are no available instructions to rename, then do nothing.
486 if (insts_available == 0) {
487 DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n",
488 tid);
489 // Should I change status to idle?
490 ++renameIdleCycles;
491 return;
492 } else if (renameStatus[tid] == Unblocking) {
493 ++renameUnblockCycles;
494 } else if (renameStatus[tid] == Running) {
495 ++renameRunCycles;
496 }
497
498 DynInstPtr inst;
499
500 // Will have to do a different calculation for the number of free
501 // entries.
502 int free_rob_entries = calcFreeROBEntries(tid);
503 int free_iq_entries = calcFreeIQEntries(tid);
504 int free_lsq_entries = calcFreeLSQEntries(tid);
505 int min_free_entries = free_rob_entries;
506
507 FullSource source = ROB;
508
509 if (free_iq_entries < min_free_entries) {
510 min_free_entries = free_iq_entries;
511 source = IQ;
512 }
513
514 if (free_lsq_entries < min_free_entries) {
515 min_free_entries = free_lsq_entries;
516 source = LSQ;
517 }
518
519 // Check if there's any space left.
520 if (min_free_entries <= 0) {
521 DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ "
522 "entries.\n"
523 "ROB has %i free entries.\n"
524 "IQ has %i free entries.\n"
525 "LSQ has %i free entries.\n",
526 tid,
527 free_rob_entries,
528 free_iq_entries,
529 free_lsq_entries);
530
531 blockThisCycle = true;
532
533 block(tid);
534
535 incrFullStat(source);
536
537 return;
538 } else if (min_free_entries < insts_available) {
539 DPRINTF(Rename, "[tid:%u]: Will have to block this cycle."
540 "%i insts available, but only %i insts can be "
541 "renamed due to ROB/IQ/LSQ limits.\n",
542 tid, insts_available, min_free_entries);
543
544 insts_available = min_free_entries;
545
546 blockThisCycle = true;
547
548 incrFullStat(source);
549 }
550
551 InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ?
552 skidBuffer[tid] : insts[tid];
553
554 DPRINTF(Rename, "[tid:%u]: %i available instructions to "
555 "send iew.\n", tid, insts_available);
556
557 DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts "
558 "dispatched to IQ last cycle.\n",
559 tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched);
560
561 // Handle serializing the next instruction if necessary.
562 if (serializeOnNextInst[tid]) {
563 if (emptyROB[tid] && instsInProgress[tid] == 0) {
564 // ROB already empty; no need to serialize.
565 serializeOnNextInst[tid] = false;
566 } else if (!insts_to_rename.empty()) {
567 insts_to_rename.front()->setSerializeBefore();
568 }
569 }
570
571 int renamed_insts = 0;
572
573 while (insts_available > 0 && toIEWIndex < renameWidth) {
574 DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid);
575
576 assert(!insts_to_rename.empty());
577
578 inst = insts_to_rename.front();
579
580 insts_to_rename.pop_front();
581
582 if (renameStatus[tid] == Unblocking) {
583 DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%s from rename "
584 "skidBuffer\n", tid, inst->seqNum, inst->pcState());
585 }
586
587 if (inst->isSquashed()) {
588 DPRINTF(Rename, "[tid:%u]: instruction %i with PC %s is "
589 "squashed, skipping.\n", tid, inst->seqNum,
590 inst->pcState());
591
592 ++renameSquashedInsts;
593
594 // Decrement how many instructions are available.
595 --insts_available;
596
597 continue;
598 }
599
600 DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with "
601 "PC %s.\n", tid, inst->seqNum, inst->pcState());
602
603 // Check here to make sure there are enough destination registers
604 // to rename to. Otherwise block.
605 if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) {
606 DPRINTF(Rename, "Blocking due to lack of free "
607 "physical registers to rename to.\n");
608 blockThisCycle = true;
609 insts_to_rename.push_front(inst);
610 ++renameFullRegistersEvents;
611
612 break;
613 }
614
615 // Handle serializeAfter/serializeBefore instructions.
616 // serializeAfter marks the next instruction as serializeBefore.
617 // serializeBefore makes the instruction wait in rename until the ROB
618 // is empty.
619
620 // In this model, IPR accesses are serialize before
621 // instructions, and store conditionals are serialize after
622 // instructions. This is mainly due to lack of support for
623 // out-of-order operations of either of those classes of
624 // instructions.
625 if ((inst->isIprAccess() || inst->isSerializeBefore()) &&
626 !inst->isSerializeHandled()) {
627 DPRINTF(Rename, "Serialize before instruction encountered.\n");
628
629 if (!inst->isTempSerializeBefore()) {
630 renamedSerializing++;
631 inst->setSerializeHandled();
632 } else {
633 renamedTempSerializing++;
634 }
635
636 // Change status over to SerializeStall so that other stages know
637 // what this is blocked on.
638 renameStatus[tid] = SerializeStall;
639
640 serializeInst[tid] = inst;
641
642 blockThisCycle = true;
643
644 break;
645 } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) &&
646 !inst->isSerializeHandled()) {
647 DPRINTF(Rename, "Serialize after instruction encountered.\n");
648
649 renamedSerializing++;
650
651 inst->setSerializeHandled();
652
653 serializeAfter(insts_to_rename, tid);
654 }
655
656 renameSrcRegs(inst, inst->threadNumber);
657
658 renameDestRegs(inst, inst->threadNumber);
659
660 ++renamed_insts;
661
662
663 // Put instruction in rename queue.
664 toIEW->insts[toIEWIndex] = inst;
665 ++(toIEW->size);
666
667 // Increment which instruction we're on.
668 ++toIEWIndex;
669
670 // Decrement how many instructions are available.
671 --insts_available;
672 }
673
674 instsInProgress[tid] += renamed_insts;
675 renameRenamedInsts += renamed_insts;
676
677 // If we wrote to the time buffer, record this.
678 if (toIEWIndex) {
679 wroteToTimeBuffer = true;
680 }
681
682 // Check if there's any instructions left that haven't yet been renamed.
683 // If so then block.
684 if (insts_available) {
685 blockThisCycle = true;
686 }
687
688 if (blockThisCycle) {
689 block(tid);
690 toDecode->renameUnblock[tid] = false;
691 }
692}
693
694template<class Impl>
695void
696DefaultRename<Impl>::skidInsert(ThreadID tid)
697{
698 DynInstPtr inst = NULL;
699
700 while (!insts[tid].empty()) {
701 inst = insts[tid].front();
702
703 insts[tid].pop_front();
704
705 assert(tid == inst->threadNumber);
706
707 DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC: %s into Rename "
708 "skidBuffer\n", tid, inst->seqNum, inst->pcState());
709
710 ++renameSkidInsts;
711
712 skidBuffer[tid].push_back(inst);
713 }
714
715 if (skidBuffer[tid].size() > skidBufferMax)
716 {
717 typename InstQueue::iterator it;
718 warn("Skidbuffer contents:\n");
719 for(it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++)
720 {
721 warn("[tid:%u]: %s [sn:%i].\n", tid,
722 (*it)->staticInst->disassemble(inst->instAddr()),
723 (*it)->seqNum);
724 }
725 panic("Skidbuffer Exceeded Max Size");
726 }
727}
728
729template <class Impl>
730void
731DefaultRename<Impl>::sortInsts()
732{
733 int insts_from_decode = fromDecode->size;
734 for (int i = 0; i < insts_from_decode; ++i) {
735 DynInstPtr inst = fromDecode->insts[i];
736 insts[inst->threadNumber].push_back(inst);
737#if TRACING_ON
738 if (DTRACE(O3PipeView)) {
739 inst->renameTick = curTick() - inst->fetchTick;
740 }
741#endif
742 }
743}
744
745template<class Impl>
746bool
747DefaultRename<Impl>::skidsEmpty()
748{
749 list<ThreadID>::iterator threads = activeThreads->begin();
750 list<ThreadID>::iterator end = activeThreads->end();
751
752 while (threads != end) {
753 ThreadID tid = *threads++;
754
755 if (!skidBuffer[tid].empty())
756 return false;
757 }
758
759 return true;
760}
761
762template<class Impl>
763void
764DefaultRename<Impl>::updateStatus()
765{
766 bool any_unblocking = false;
767
768 list<ThreadID>::iterator threads = activeThreads->begin();
769 list<ThreadID>::iterator end = activeThreads->end();
770
771 while (threads != end) {
772 ThreadID tid = *threads++;
773
774 if (renameStatus[tid] == Unblocking) {
775 any_unblocking = true;
776 break;
777 }
778 }
779
780 // Rename will have activity if it's unblocking.
781 if (any_unblocking) {
782 if (_status == Inactive) {
783 _status = Active;
784
785 DPRINTF(Activity, "Activating stage.\n");
786
787 cpu->activateStage(O3CPU::RenameIdx);
788 }
789 } else {
790 // If it's not unblocking, then rename will not have any internal
791 // activity. Switch it to inactive.
792 if (_status == Active) {
793 _status = Inactive;
794 DPRINTF(Activity, "Deactivating stage.\n");
795
796 cpu->deactivateStage(O3CPU::RenameIdx);
797 }
798 }
799}
800
801template <class Impl>
802bool
803DefaultRename<Impl>::block(ThreadID tid)
804{
805 DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid);
806
807 // Add the current inputs onto the skid buffer, so they can be
808 // reprocessed when this stage unblocks.
809 skidInsert(tid);
810
811 // Only signal backwards to block if the previous stages do not think
812 // rename is already blocked.
813 if (renameStatus[tid] != Blocked) {
814 // If resumeUnblocking is set, we unblocked during the squash,
815 // but now we're have unblocking status. We need to tell earlier
816 // stages to block.
817 if (resumeUnblocking || renameStatus[tid] != Unblocking) {
818 toDecode->renameBlock[tid] = true;
819 toDecode->renameUnblock[tid] = false;
820 wroteToTimeBuffer = true;
821 }
822
823 // Rename can not go from SerializeStall to Blocked, otherwise
824 // it would not know to complete the serialize stall.
825 if (renameStatus[tid] != SerializeStall) {
826 // Set status to Blocked.
827 renameStatus[tid] = Blocked;
828 return true;
829 }
830 }
831
832 return false;
833}
834
835template <class Impl>
836bool
837DefaultRename<Impl>::unblock(ThreadID tid)
838{
839 DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid);
840
841 // Rename is done unblocking if the skid buffer is empty.
842 if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) {
843
844 DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid);
845
846 toDecode->renameUnblock[tid] = true;
847 wroteToTimeBuffer = true;
848
849 renameStatus[tid] = Running;
850 return true;
851 }
852
853 return false;
854}
855
856template <class Impl>
857void
858DefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, ThreadID tid)
859{
860 typename std::list<RenameHistory>::iterator hb_it =
861 historyBuffer[tid].begin();
862
863 // After a syscall squashes everything, the history buffer may be empty
864 // but the ROB may still be squashing instructions.
865 if (historyBuffer[tid].empty()) {
866 return;
867 }
868
869 // Go through the most recent instructions, undoing the mappings
870 // they did and freeing up the registers.
871 while (!historyBuffer[tid].empty() &&
872 hb_it->instSeqNum > squashed_seq_num) {
873 assert(hb_it != historyBuffer[tid].end());
874
875 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
876 "number %i.\n", tid, hb_it->instSeqNum);
877
878 // Undo the rename mapping only if it was really a change.
879 // Special regs that are not really renamed (like misc regs
880 // and the zero reg) can be recognized because the new mapping
881 // is the same as the old one. While it would be merely a
882 // waste of time to update the rename table, we definitely
883 // don't want to put these on the free list.
884 if (hb_it->newPhysReg != hb_it->prevPhysReg) {
885 // Tell the rename map to set the architected register to the
886 // previous physical register that it was renamed to.
887 renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
888
889 // Put the renamed physical register back on the free list.
890 freeList->addReg(hb_it->newPhysReg);
891 }
892
893 historyBuffer[tid].erase(hb_it++);
894
895 ++renameUndoneMaps;
896 }
897}
898
899template<class Impl>
900void
901DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid)
902{
903 DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the "
904 "history buffer %u (size=%i), until [sn:%lli].\n",
905 tid, tid, historyBuffer[tid].size(), inst_seq_num);
906
907 typename std::list<RenameHistory>::iterator hb_it =
908 historyBuffer[tid].end();
909
910 --hb_it;
911
912 if (historyBuffer[tid].empty()) {
913 DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid);
914 return;
915 } else if (hb_it->instSeqNum > inst_seq_num) {
916 DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure "
917 "that a syscall happened recently.\n", tid);
918 return;
919 }
920
921 // Commit all the renames up until (and including) the committed sequence
922 // number. Some or even all of the committed instructions may not have
923 // rename histories if they did not have destination registers that were
924 // renamed.
925 while (!historyBuffer[tid].empty() &&
926 hb_it != historyBuffer[tid].end() &&
927 hb_it->instSeqNum <= inst_seq_num) {
928
929 DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, "
930 "[sn:%lli].\n",
931 tid, hb_it->prevPhysReg, hb_it->instSeqNum);
932
933 // Don't free special phys regs like misc and zero regs, which
934 // can be recognized because the new mapping is the same as
935 // the old one.
936 if (hb_it->newPhysReg != hb_it->prevPhysReg) {
937 freeList->addReg(hb_it->prevPhysReg);
938 }
939
940 ++renameCommittedMaps;
941
942 historyBuffer[tid].erase(hb_it--);
943 }
944}
945
946template <class Impl>
947inline void
948DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid)
949{
950 ThreadContext *tc = inst->tcBase();
951 RenameMap *map = renameMap[tid];
952 unsigned num_src_regs = inst->numSrcRegs();
953
954 // Get the architectual register numbers from the source and
955 // operands, and redirect them to the right physical register.
956 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) {
957 RegIndex src_reg = inst->srcRegIdx(src_idx);
958 RegIndex rel_src_reg;
959 RegIndex flat_rel_src_reg;
960 PhysRegIndex renamed_reg;
961
962 switch (regIdxToClass(src_reg, &rel_src_reg)) {
963 case IntRegClass:
964 flat_rel_src_reg = tc->flattenIntIndex(rel_src_reg);
965 renamed_reg = map->lookupInt(flat_rel_src_reg);
966 intRenameLookups++;
967 break;
968
969 case FloatRegClass:
970 flat_rel_src_reg = tc->flattenFloatIndex(rel_src_reg);
971 renamed_reg = map->lookupFloat(flat_rel_src_reg);
972 fpRenameLookups++;
973 break;
974
975 case CCRegClass:
976 flat_rel_src_reg = tc->flattenCCIndex(rel_src_reg);
977 renamed_reg = map->lookupCC(flat_rel_src_reg);
978 break;
979
980 case MiscRegClass:
981 // misc regs don't get flattened
982 flat_rel_src_reg = rel_src_reg;
983 renamed_reg = map->lookupMisc(flat_rel_src_reg);
984 break;
985
986 default:
987 panic("Reg index is out of bound: %d.", src_reg);
988 }
989
990 DPRINTF(Rename, "[tid:%u]: Looking up %s arch reg %i (flattened %i), "
991 "got phys reg %i\n", tid, RegClassStrings[regIdxToClass(src_reg)],
992 (int)src_reg, (int)flat_rel_src_reg, (int)renamed_reg);
993
994 inst->renameSrcReg(src_idx, renamed_reg);
995
996 // See if the register is ready or not.
997 if (scoreboard->getReg(renamed_reg)) {
998 DPRINTF(Rename, "[tid:%u]: Register %d is ready.\n",
999 tid, renamed_reg);
1000
1001 inst->markSrcRegReady(src_idx);
1002 } else {
1003 DPRINTF(Rename, "[tid:%u]: Register %d is not ready.\n",
1004 tid, renamed_reg);
1005 }
1006
1007 ++renameRenameLookups;
1008 }
1009}
1010
1011template <class Impl>
1012inline void
1013DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid)
1014{
1015 ThreadContext *tc = inst->tcBase();
1016 RenameMap *map = renameMap[tid];
1017 unsigned num_dest_regs = inst->numDestRegs();
1018
1019 // Rename the destination registers.
1020 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) {
1021 RegIndex dest_reg = inst->destRegIdx(dest_idx);
1022 RegIndex rel_dest_reg;
1023 RegIndex flat_rel_dest_reg;
1024 RegIndex flat_uni_dest_reg;
1025 typename RenameMap::RenameInfo rename_result;
1026
1027 switch (regIdxToClass(dest_reg, &rel_dest_reg)) {
1028 case IntRegClass:
1029 flat_rel_dest_reg = tc->flattenIntIndex(rel_dest_reg);
1030 rename_result = map->renameInt(flat_rel_dest_reg);
1031 flat_uni_dest_reg = flat_rel_dest_reg; // 1:1 mapping
1032 break;
1033
1034 case FloatRegClass:
1035 flat_rel_dest_reg = tc->flattenFloatIndex(rel_dest_reg);
1036 rename_result = map->renameFloat(flat_rel_dest_reg);
1037 flat_uni_dest_reg = flat_rel_dest_reg + TheISA::FP_Reg_Base;
1038 break;
1039
1040 case CCRegClass:
1041 flat_rel_dest_reg = tc->flattenCCIndex(rel_dest_reg);
1042 rename_result = map->renameCC(flat_rel_dest_reg);
1043 flat_uni_dest_reg = flat_rel_dest_reg + TheISA::CC_Reg_Base;
1044 break;
1045
1046 case MiscRegClass:
1047 // misc regs don't get flattened
1048 flat_rel_dest_reg = rel_dest_reg;
1049 rename_result = map->renameMisc(flat_rel_dest_reg);
1050 flat_uni_dest_reg = flat_rel_dest_reg + TheISA::Misc_Reg_Base;
1051 break;
1052
1053 default:
1054 panic("Reg index is out of bound: %d.", dest_reg);
1055 }
1056
1057 inst->flattenDestReg(dest_idx, flat_uni_dest_reg);
1058
1059 // Mark Scoreboard entry as not ready
1060 scoreboard->unsetReg(rename_result.first);
1061
1062 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical "
1063 "reg %i.\n", tid, (int)flat_rel_dest_reg,
1064 (int)rename_result.first);
1065
1066 // Record the rename information so that a history can be kept.
1067 RenameHistory hb_entry(inst->seqNum, flat_uni_dest_reg,
1068 rename_result.first,
1069 rename_result.second);
1070
1071 historyBuffer[tid].push_front(hb_entry);
1072
1073 DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer "
1074 "(size=%i), [sn:%lli].\n",tid,
1075 historyBuffer[tid].size(),
1076 (*historyBuffer[tid].begin()).instSeqNum);
1077
1078 // Tell the instruction to rename the appropriate destination
1079 // register (dest_idx) to the new physical register
1080 // (rename_result.first), and record the previous physical
1081 // register that the same logical register was renamed to
1082 // (rename_result.second).
1083 inst->renameDestReg(dest_idx,
1084 rename_result.first,
1085 rename_result.second);
1086
1087 ++renameRenamedOperands;
1088 }
1089}
1090
1091template <class Impl>
1092inline int
1093DefaultRename<Impl>::calcFreeROBEntries(ThreadID tid)
1094{
1095 int num_free = freeEntries[tid].robEntries -
1096 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1097
1098 //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free);
1099
1100 return num_free;
1101}
1102
1103template <class Impl>
1104inline int
1105DefaultRename<Impl>::calcFreeIQEntries(ThreadID tid)
1106{
1107 int num_free = freeEntries[tid].iqEntries -
1108 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1109
1110 //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free);
1111
1112 return num_free;
1113}
1114
1115template <class Impl>
1116inline int
1117DefaultRename<Impl>::calcFreeLSQEntries(ThreadID tid)
1118{
1119 int num_free = freeEntries[tid].lsqEntries -
1120 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ);
1121
1122 //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free);
1123
1124 return num_free;
1125}
1126
1127template <class Impl>
1128unsigned
1129DefaultRename<Impl>::validInsts()
1130{
1131 unsigned inst_count = 0;
1132
1133 for (int i=0; i<fromDecode->size; i++) {
1134 if (!fromDecode->insts[i]->isSquashed())
1135 inst_count++;
1136 }
1137
1138 return inst_count;
1139}
1140
1141template <class Impl>
1142void
1143DefaultRename<Impl>::readStallSignals(ThreadID tid)
1144{
1145 if (fromIEW->iewBlock[tid]) {
1146 stalls[tid].iew = true;
1147 }
1148
1149 if (fromIEW->iewUnblock[tid]) {
1150 assert(stalls[tid].iew);
1151 stalls[tid].iew = false;
1152 }
1153
1154 if (fromCommit->commitBlock[tid]) {
1155 stalls[tid].commit = true;
1156 }
1157
1158 if (fromCommit->commitUnblock[tid]) {
1159 assert(stalls[tid].commit);
1160 stalls[tid].commit = false;
1161 }
1162}
1163
1164template <class Impl>
1165bool
1166DefaultRename<Impl>::checkStall(ThreadID tid)
1167{
1168 bool ret_val = false;
1169
1170 if (stalls[tid].iew) {
1171 DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid);
1172 ret_val = true;
1173 } else if (stalls[tid].commit) {
1174 DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid);
1175 ret_val = true;
1176 } else if (calcFreeROBEntries(tid) <= 0) {
1177 DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid);
1178 ret_val = true;
1179 } else if (calcFreeIQEntries(tid) <= 0) {
1180 DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid);
1181 ret_val = true;
1182 } else if (calcFreeLSQEntries(tid) <= 0) {
1183 DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid);
1184 ret_val = true;
1185 } else if (renameMap[tid]->numFreeEntries() <= 0) {
1186 DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid);
1187 ret_val = true;
1188 } else if (renameStatus[tid] == SerializeStall &&
1189 (!emptyROB[tid] || instsInProgress[tid])) {
1190 DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not "
1191 "empty.\n",
1192 tid);
1193 ret_val = true;
1194 }
1195
1196 return ret_val;
1197}
1198
1199template <class Impl>
1200void
1201DefaultRename<Impl>::readFreeEntries(ThreadID tid)
1202{
1203 if (fromIEW->iewInfo[tid].usedIQ)
1204 freeEntries[tid].iqEntries = fromIEW->iewInfo[tid].freeIQEntries;
1205
1206 if (fromIEW->iewInfo[tid].usedLSQ)
1207 freeEntries[tid].lsqEntries = fromIEW->iewInfo[tid].freeLSQEntries;
1208
1209 if (fromCommit->commitInfo[tid].usedROB) {
1210 freeEntries[tid].robEntries =
1211 fromCommit->commitInfo[tid].freeROBEntries;
1212 emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB;
1213 }
1214
1215 DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n",
1216 tid,
1217 freeEntries[tid].iqEntries,
1218 freeEntries[tid].robEntries,
1219 freeEntries[tid].lsqEntries);
1220
1221 DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n",
1222 tid, instsInProgress[tid]);
1223}
1224
1225template <class Impl>
1226bool
1227DefaultRename<Impl>::checkSignalsAndUpdate(ThreadID tid)
1228{
1229 // Check if there's a squash signal, squash if there is
1230 // Check stall signals, block if necessary.
1231 // If status was blocked
1232 // check if stall conditions have passed
1233 // if so then go to unblocking
1234 // If status was Squashing
1235 // check if squashing is not high. Switch to running this cycle.
1236 // If status was serialize stall
1237 // check if ROB is empty and no insts are in flight to the ROB
1238
1239 readFreeEntries(tid);
1240 readStallSignals(tid);
1241
1242 if (fromCommit->commitInfo[tid].squash) {
1243 DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from "
1244 "commit.\n", tid);
1245
1246 squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
1247
1248 return true;
1249 }
1250
1251 if (fromCommit->commitInfo[tid].robSquashing) {
1252 DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid);
1253
1254 renameStatus[tid] = Squashing;
1255
1256 return true;
1257 }
1258
1259 if (checkStall(tid)) {
1260 return block(tid);
1261 }
1262
1263 if (renameStatus[tid] == Blocked) {
1264 DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n",
1265 tid);
1266
1267 renameStatus[tid] = Unblocking;
1268
1269 unblock(tid);
1270
1271 return true;
1272 }
1273
1274 if (renameStatus[tid] == Squashing) {
1275 // Switch status to running if rename isn't being told to block or
1276 // squash this cycle.
1277 if (resumeSerialize) {
1278 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n",
1279 tid);
1280
1281 renameStatus[tid] = SerializeStall;
1282 return true;
1283 } else if (resumeUnblocking) {
1284 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n",
1285 tid);
1286 renameStatus[tid] = Unblocking;
1287 return true;
1288 } else {
1289 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n",
1290 tid);
1291
1292 renameStatus[tid] = Running;
1293 return false;
1294 }
1295 }
1296
1297 if (renameStatus[tid] == SerializeStall) {
1298 // Stall ends once the ROB is free.
1299 DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to "
1300 "unblocking.\n", tid);
1301
1302 DynInstPtr serial_inst = serializeInst[tid];
1303
1304 renameStatus[tid] = Unblocking;
1305
1306 unblock(tid);
1307
1308 DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with "
1309 "PC %s.\n", tid, serial_inst->seqNum, serial_inst->pcState());
1310
1311 // Put instruction into queue here.
1312 serial_inst->clearSerializeBefore();
1313
1314 if (!skidBuffer[tid].empty()) {
1315 skidBuffer[tid].push_front(serial_inst);
1316 } else {
1317 insts[tid].push_front(serial_inst);
1318 }
1319
1320 DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename."
1321 " Adding to front of list.\n", tid);
1322
1323 serializeInst[tid] = NULL;
1324
1325 return true;
1326 }
1327
1328 // If we've reached this point, we have not gotten any signals that
1329 // cause rename to change its status. Rename remains the same as before.
1330 return false;
1331}
1332
1333template<class Impl>
1334void
1335DefaultRename<Impl>::serializeAfter(InstQueue &inst_list, ThreadID tid)
1336{
1337 if (inst_list.empty()) {
1338 // Mark a bit to say that I must serialize on the next instruction.
1339 serializeOnNextInst[tid] = true;
1340 return;
1341 }
1342
1343 // Set the next instruction as serializing.
1344 inst_list.front()->setSerializeBefore();
1345}
1346
1347template <class Impl>
1348inline void
1349DefaultRename<Impl>::incrFullStat(const FullSource &source)
1350{
1351 switch (source) {
1352 case ROB:
1353 ++renameROBFullEvents;
1354 break;
1355 case IQ:
1356 ++renameIQFullEvents;
1357 break;
1358 case LSQ:
1359 ++renameLSQFullEvents;
1360 break;
1361 default:
1362 panic("Rename full stall stat should be incremented for a reason!");
1363 break;
1364 }
1365}
1366
1367template <class Impl>
1368void
1369DefaultRename<Impl>::dumpHistory()
1370{
1371 typename std::list<RenameHistory>::iterator buf_it;
1372
1373 for (ThreadID tid = 0; tid < numThreads; tid++) {
1374
1375 buf_it = historyBuffer[tid].begin();
1376
1377 while (buf_it != historyBuffer[tid].end()) {
1378 cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys "
1379 "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg,
1380 (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg);
1381
1382 buf_it++;
1383 }
1384 }
1385}