1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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866 // but the ROB may still be squashing instructions.
867 if (historyBuffer[tid].empty()) {
868 return;
869 }
870
871 // Go through the most recent instructions, undoing the mappings
872 // they did and freeing up the registers.
873 while (!historyBuffer[tid].empty() &&
874 (*hb_it).instSeqNum > squashed_seq_num) {
875 assert(hb_it != historyBuffer[tid].end());
876
877 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
878 "number %i.\n", tid, (*hb_it).instSeqNum);
879
880 // Tell the rename map to set the architected register to the
881 // previous physical register that it was renamed to.
882 renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
883
884 // Put the renamed physical register back on the free list.
885 freeList->addReg(hb_it->newPhysReg);
886
887 historyBuffer[tid].erase(hb_it++);
888
889 ++renameUndoneMaps;
890 }
891}
892
893template<class Impl>

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913 }
914
915 // Commit all the renames up until (and including) the committed sequence
916 // number. Some or even all of the committed instructions may not have
917 // rename histories if they did not have destination registers that were
918 // renamed.
919 while (!historyBuffer[tid].empty() &&
920 hb_it != historyBuffer[tid].end() &&
921 (*hb_it).instSeqNum <= inst_seq_num) {
922
923 DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, "
924 "[sn:%lli].\n",
925 tid, (*hb_it).prevPhysReg, (*hb_it).instSeqNum);
926
927 freeList->addReg((*hb_it).prevPhysReg);
928 ++renameCommittedMaps;
929
930 historyBuffer[tid].erase(hb_it--);
931 }
932}
933
934template <class Impl>
935inline void
936DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid)
937{
938 assert(renameMap[tid] != 0);
939
940 unsigned num_src_regs = inst->numSrcRegs();
941
942 // Get the architectual register numbers from the source and
943 // destination operands, and redirect them to the right register.
944 // Will need to mark dependencies though.
945 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) {
946 RegIndex src_reg = inst->srcRegIdx(src_idx);
947 RegIndex flat_src_reg = src_reg;
948 switch (regIdxToClass(src_reg)) {
949 case IntRegClass:
950 flat_src_reg = inst->tcBase()->flattenIntIndex(src_reg);
951 DPRINTF(Rename, "Flattening index %d to %d.\n",
952 (int)src_reg, (int)flat_src_reg);
953 break;
954
955 case FloatRegClass:
956 src_reg = src_reg - TheISA::FP_Reg_Base;
957 flat_src_reg = inst->tcBase()->flattenFloatIndex(src_reg);
958 DPRINTF(Rename, "Flattening index %d to %d.\n",
959 (int)src_reg, (int)flat_src_reg);
960 flat_src_reg += TheISA::NumIntRegs;
961 break;
962
963 case MiscRegClass:
964 flat_src_reg = src_reg - TheISA::Misc_Reg_Base +
965 TheISA::NumFloatRegs + TheISA::NumIntRegs;
966 DPRINTF(Rename, "Adjusting reg index from %d to %d.\n",
967 src_reg, flat_src_reg);
968 break;
969
970 default:
971 panic("Reg index is out of bound: %d.", src_reg);
972 }
973
974 // Look up the source registers to get the phys. register they've
975 // been renamed to, and set the sources to those registers.
976 PhysRegIndex renamed_reg = renameMap[tid]->lookup(flat_src_reg);
977
978 DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got "
979 "physical reg %i.\n", tid, (int)flat_src_reg,
980 (int)renamed_reg);
981
982 inst->renameSrcReg(src_idx, renamed_reg);
983
984 // See if the register is ready or not.
985 if (scoreboard->getReg(renamed_reg) == true) {
986 DPRINTF(Rename, "[tid:%u]: Register %d is ready.\n",
987 tid, renamed_reg);
988
989 inst->markSrcRegReady(src_idx);
990 } else {
991 DPRINTF(Rename, "[tid:%u]: Register %d is not ready.\n",
992 tid, renamed_reg);
993 }
994
995 ++renameRenameLookups;
996 inst->isFloating() ? fpRenameLookups++ : intRenameLookups++;
997 }
998}
999
1000template <class Impl>
1001inline void
1002DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid)
1003{
1004 typename RenameMap::RenameInfo rename_result;
1005
1006 unsigned num_dest_regs = inst->numDestRegs();
1007
1008 // Rename the destination registers.
1009 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) {
1010 RegIndex dest_reg = inst->destRegIdx(dest_idx);
1011 RegIndex flat_dest_reg = dest_reg;
1012 switch (regIdxToClass(dest_reg)) {
1013 case IntRegClass:
1014 // Integer registers are flattened.
1015 flat_dest_reg = inst->tcBase()->flattenIntIndex(dest_reg);
1016 DPRINTF(Rename, "Flattening index %d to %d.\n",
1017 (int)dest_reg, (int)flat_dest_reg);
1018 break;
1019
1020 case FloatRegClass:
1021 dest_reg = dest_reg - TheISA::FP_Reg_Base;
1022 flat_dest_reg = inst->tcBase()->flattenFloatIndex(dest_reg);
1023 DPRINTF(Rename, "Flattening index %d to %d.\n",
1024 (int)dest_reg, (int)flat_dest_reg);
1025 flat_dest_reg += TheISA::NumIntRegs;
1026 break;
1027
1028 case MiscRegClass:
1029 // Floating point and Miscellaneous registers need their indexes
1030 // adjusted to account for the expanded number of flattened int regs.
1031 flat_dest_reg = dest_reg - TheISA::Misc_Reg_Base +
1032 TheISA::NumIntRegs + TheISA::NumFloatRegs;
1033 DPRINTF(Rename, "Adjusting reg index from %d to %d.\n",
1034 dest_reg, flat_dest_reg);
1035 break;
1036
1037 default:
1038 panic("Reg index is out of bound: %d.", dest_reg);
1039 }
1040
1041 inst->flattenDestReg(dest_idx, flat_dest_reg);
1042
1043 // Get the physical register that the destination will be
1044 // renamed to.
1045 rename_result = renameMap[tid]->rename(flat_dest_reg);
1046
1047 //Mark Scoreboard entry as not ready
1048 scoreboard->unsetReg(rename_result.first);
1049
1050 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical "
1051 "reg %i.\n", tid, (int)flat_dest_reg,
1052 (int)rename_result.first);
1053
1054 // Record the rename information so that a history can be kept.
1055 RenameHistory hb_entry(inst->seqNum, flat_dest_reg,
1056 rename_result.first,
1057 rename_result.second);
1058
1059 historyBuffer[tid].push_front(hb_entry);
1060
1061 DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer "
1062 "(size=%i), [sn:%lli].\n",tid,
1063 historyBuffer[tid].size(),

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