1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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44#include <list>
45
46#include "arch/isa_traits.hh"
47#include "arch/registers.hh"
48#include "config/the_isa.hh"
49#include "cpu/o3/rename.hh"
50#include "debug/Activity.hh"
51#include "debug/Rename.hh"
52#include "params/DerivO3CPU.hh"
53
54using namespace std;
55
56template <class Impl>
57DefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params)
58 : cpu(_cpu),
59 iewToRenameDelay(params->iewToRenameDelay),

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653 }
654
655 renameSrcRegs(inst, inst->threadNumber);
656
657 renameDestRegs(inst, inst->threadNumber);
658
659 ++renamed_insts;
660
661#if TRACING_ON
662 inst->renameTick = curTick() - inst->fetchTick;
663#endif
664
665 // Put instruction in rename queue.
666 toIEW->insts[toIEWIndex] = inst;
667 ++(toIEW->size);
668
669 // Increment which instruction we're on.
670 ++toIEWIndex;
671

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731template <class Impl>
732void
733DefaultRename<Impl>::sortInsts()
734{
735 int insts_from_decode = fromDecode->size;
736 for (int i = 0; i < insts_from_decode; ++i) {
737 DynInstPtr inst = fromDecode->insts[i];
738 insts[inst->threadNumber].push_back(inst);
739 }
740}
741
742template<class Impl>
743bool
744DefaultRename<Impl>::skidsEmpty()
745{
746 list<ThreadID>::iterator threads = activeThreads->begin();

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