1/*
2 * Copyright (c) 2010-2012, 2014-2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 182 unchanged lines hidden (view full) ---

191 fpRenameLookups
192 .name(name() + ".fp_rename_lookups")
193 .desc("Number of floating rename lookups")
194 .prereq(fpRenameLookups);
195 vecRenameLookups
196 .name(name() + ".vec_rename_lookups")
197 .desc("Number of vector rename lookups")
198 .prereq(vecRenameLookups);
199}
200
201template <class Impl>
202void
203DefaultRename<Impl>::regProbePoints()
204{
205 ppRename = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Rename");
206 ppSquashInRename = new ProbePointArg<SeqNumRegPair>(cpu->getProbeManager(),

--- 447 unchanged lines hidden (view full) ---

654 "PC %s.\n", tid, inst->seqNum, inst->pcState());
655
656 // Check here to make sure there are enough destination registers
657 // to rename to. Otherwise block.
658 if (!renameMap[tid]->canRename(inst->numIntDestRegs(),
659 inst->numFPDestRegs(),
660 inst->numVecDestRegs(),
661 inst->numVecElemDestRegs(),
662 inst->numCCDestRegs())) {
663 DPRINTF(Rename, "Blocking due to lack of free "
664 "physical registers to rename to.\n");
665 blockThisCycle = true;
666 insts_to_rename.push_front(inst);
667 ++renameFullRegistersEvents;
668
669 break;

--- 366 unchanged lines hidden (view full) ---

1036 break;
1037 case FloatRegClass:
1038 fpRenameLookups++;
1039 break;
1040 case VecRegClass:
1041 case VecElemClass:
1042 vecRenameLookups++;
1043 break;
1044 case CCRegClass:
1045 case MiscRegClass:
1046 break;
1047
1048 default:
1049 panic("Invalid register class: %d.", src_reg.classValue());
1050 }
1051

--- 199 unchanged lines hidden (view full) ---

1251
1252 if (fromCommit->commitInfo[tid].usedROB) {
1253 freeEntries[tid].robEntries =
1254 fromCommit->commitInfo[tid].freeROBEntries;
1255 emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB;
1256 }
1257
1258 DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, "
1259 "Free LQ: %i, Free SQ: %i, FreeRM %i(%i %i %i %i)\n",
1260 tid,
1261 freeEntries[tid].iqEntries,
1262 freeEntries[tid].robEntries,
1263 freeEntries[tid].lqEntries,
1264 freeEntries[tid].sqEntries,
1265 renameMap[tid]->numFreeEntries(),
1266 renameMap[tid]->numFreeIntEntries(),
1267 renameMap[tid]->numFreeFloatEntries(),
1268 renameMap[tid]->numFreeVecEntries(),
1269 renameMap[tid]->numFreeCCEntries());
1270
1271 DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n",
1272 tid, instsInProgress[tid]);
1273}
1274
1275template <class Impl>
1276bool

--- 162 unchanged lines hidden ---