1/*
2 * Copyright (c) 2010-2012, 2014-2015 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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978 // Commit all the renames up until (and including) the committed sequence
979 // number. Some or even all of the committed instructions may not have
980 // rename histories if they did not have destination registers that were
981 // renamed.
982 while (!historyBuffer[tid].empty() &&
983 hb_it != historyBuffer[tid].end() &&
984 hb_it->instSeqNum <= inst_seq_num) {
985
986 DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, "
987 "[sn:%lli].\n",
988 tid, hb_it->prevPhysReg, hb_it->instSeqNum);
989
990 // Don't free special phys regs like misc and zero regs, which
991 // can be recognized because the new mapping is the same as
992 // the old one.
993 if (hb_it->newPhysReg != hb_it->prevPhysReg) {
994 freeList->addReg(hb_it->prevPhysReg);
995 }
996

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1008 RenameMap *map = renameMap[tid];
1009 unsigned num_src_regs = inst->numSrcRegs();
1010
1011 // Get the architectual register numbers from the source and
1012 // operands, and redirect them to the right physical register.
1013 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) {
1014 RegId src_reg = inst->srcRegIdx(src_idx);
1015 RegIndex flat_src_reg;
1016 PhysRegIndex renamed_reg;
1017
1018 switch (src_reg.regClass) {
1019 case IntRegClass:
1020 flat_src_reg = tc->flattenIntIndex(src_reg.regIdx);
1021 renamed_reg = map->lookupInt(flat_src_reg);
1022 intRenameLookups++;
1023 break;
1024

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1038 flat_src_reg = src_reg.regIdx;
1039 renamed_reg = map->lookupMisc(flat_src_reg);
1040 break;
1041
1042 default:
1043 panic("Invalid register class: %d.", src_reg.regClass);
1044 }
1045
1046 DPRINTF(Rename, "[tid:%u]: Looking up %s arch reg %i (flattened %i), "
1047 "got phys reg %i\n", tid, RegClassStrings[src_reg.regClass],
1048 (int)src_reg.regIdx, (int)flat_src_reg, (int)renamed_reg);
1049
1050 inst->renameSrcReg(src_idx, renamed_reg);
1051
1052 // See if the register is ready or not.
1053 if (scoreboard->getReg(renamed_reg)) {
1054 DPRINTF(Rename, "[tid:%u]: Register %d is ready.\n",
1055 tid, renamed_reg);
1056
1057 inst->markSrcRegReady(src_idx);
1058 } else {
1059 DPRINTF(Rename, "[tid:%u]: Register %d is not ready.\n",
1060 tid, renamed_reg);
1061 }
1062
1063 ++renameRenameLookups;
1064 }
1065}
1066
1067template <class Impl>
1068inline void

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1106
1107 RegId flat_uni_dest_reg(dest_reg.regClass, flat_dest_reg);
1108
1109 inst->flattenDestReg(dest_idx, flat_uni_dest_reg);
1110
1111 // Mark Scoreboard entry as not ready
1112 scoreboard->unsetReg(rename_result.first);
1113
1114 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical "
1115 "reg %i.\n", tid, (int)flat_dest_reg,
1116 (int)rename_result.first);
1117
1118 // Record the rename information so that a history can be kept.
1119 RenameHistory hb_entry(inst->seqNum, flat_uni_dest_reg,
1120 rename_result.first,
1121 rename_result.second);
1122
1123 historyBuffer[tid].push_front(hb_entry);
1124

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1421{
1422 typename std::list<RenameHistory>::iterator buf_it;
1423
1424 for (ThreadID tid = 0; tid < numThreads; tid++) {
1425
1426 buf_it = historyBuffer[tid].begin();
1427
1428 while (buf_it != historyBuffer[tid].end()) {
1429 cprintf("Seq num: %i\nArch reg[%s]: %i New phys reg: %i Old phys "
1430 "reg: %i\n", (*buf_it).instSeqNum,
1431 RegClassStrings[(*buf_it).archReg.regClass],
1432 (*buf_it).archReg.regIdx,
1433 (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg);
1434
1435 buf_it++;
1436 }
1437 }
1438}
1439
1440#endif//__CPU_O3_RENAME_IMPL_HH__