1/*
2 * Copyright (c) 2010-2012, 2014-2015 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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1006{
1007 ThreadContext *tc = inst->tcBase();
1008 RenameMap *map = renameMap[tid];
1009 unsigned num_src_regs = inst->numSrcRegs();
1010
1011 // Get the architectual register numbers from the source and
1012 // operands, and redirect them to the right physical register.
1013 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) {
1014 RegIndex src_reg = inst->srcRegIdx(src_idx);
1015 RegIndex rel_src_reg;
1016 RegIndex flat_rel_src_reg;
1017 PhysRegIndex renamed_reg;
1018
1019 switch (regIdxToClass(src_reg, &rel_src_reg)) {
1020 case IntRegClass:
1021 flat_rel_src_reg = tc->flattenIntIndex(rel_src_reg);
1022 renamed_reg = map->lookupInt(flat_rel_src_reg);
1023 intRenameLookups++;
1024 break;
1025
1026 case FloatRegClass:
1027 flat_rel_src_reg = tc->flattenFloatIndex(rel_src_reg);
1028 renamed_reg = map->lookupFloat(flat_rel_src_reg);
1029 fpRenameLookups++;
1030 break;
1031
1032 case CCRegClass:
1033 flat_rel_src_reg = tc->flattenCCIndex(rel_src_reg);
1034 renamed_reg = map->lookupCC(flat_rel_src_reg);
1035 break;
1036
1037 case MiscRegClass:
1038 // misc regs don't get flattened
1039 flat_rel_src_reg = rel_src_reg;
1040 renamed_reg = map->lookupMisc(flat_rel_src_reg);
1041 break;
1042
1043 default:
1044 panic("Reg index is out of bound: %d.", src_reg);
1045 }
1046
1047 DPRINTF(Rename, "[tid:%u]: Looking up %s arch reg %i (flattened %i), "
1048 "got phys reg %i\n", tid, RegClassStrings[regIdxToClass(src_reg)],
1049 (int)src_reg, (int)flat_rel_src_reg, (int)renamed_reg);
1050
1051 inst->renameSrcReg(src_idx, renamed_reg);
1052
1053 // See if the register is ready or not.
1054 if (scoreboard->getReg(renamed_reg)) {
1055 DPRINTF(Rename, "[tid:%u]: Register %d is ready.\n",
1056 tid, renamed_reg);
1057

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1070DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid)
1071{
1072 ThreadContext *tc = inst->tcBase();
1073 RenameMap *map = renameMap[tid];
1074 unsigned num_dest_regs = inst->numDestRegs();
1075
1076 // Rename the destination registers.
1077 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) {
1078 RegIndex dest_reg = inst->destRegIdx(dest_idx);
1079 RegIndex rel_dest_reg;
1080 RegIndex flat_rel_dest_reg;
1081 RegIndex flat_uni_dest_reg;
1082 typename RenameMap::RenameInfo rename_result;
1083
1084 switch (regIdxToClass(dest_reg, &rel_dest_reg)) {
1085 case IntRegClass:
1086 flat_rel_dest_reg = tc->flattenIntIndex(rel_dest_reg);
1087 rename_result = map->renameInt(flat_rel_dest_reg);
1088 flat_uni_dest_reg = flat_rel_dest_reg; // 1:1 mapping
1089 break;
1090
1091 case FloatRegClass:
1092 flat_rel_dest_reg = tc->flattenFloatIndex(rel_dest_reg);
1093 rename_result = map->renameFloat(flat_rel_dest_reg);
1094 flat_uni_dest_reg = flat_rel_dest_reg + TheISA::FP_Reg_Base;
1095 break;
1096
1097 case CCRegClass:
1098 flat_rel_dest_reg = tc->flattenCCIndex(rel_dest_reg);
1099 rename_result = map->renameCC(flat_rel_dest_reg);
1100 flat_uni_dest_reg = flat_rel_dest_reg + TheISA::CC_Reg_Base;
1101 break;
1102
1103 case MiscRegClass:
1104 // misc regs don't get flattened
1105 flat_rel_dest_reg = rel_dest_reg;
1106 rename_result = map->renameMisc(flat_rel_dest_reg);
1107 flat_uni_dest_reg = flat_rel_dest_reg + TheISA::Misc_Reg_Base;
1108 break;
1109
1110 default:
1111 panic("Reg index is out of bound: %d.", dest_reg);
1112 }
1113
1114 inst->flattenDestReg(dest_idx, flat_uni_dest_reg);
1115
1116 // Mark Scoreboard entry as not ready
1117 scoreboard->unsetReg(rename_result.first);
1118
1119 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical "
1120 "reg %i.\n", tid, (int)flat_rel_dest_reg,
1121 (int)rename_result.first);
1122
1123 // Record the rename information so that a history can be kept.
1124 RenameHistory hb_entry(inst->seqNum, flat_uni_dest_reg,
1125 rename_result.first,
1126 rename_result.second);
1127
1128 historyBuffer[tid].push_front(hb_entry);

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1426{
1427 typename std::list<RenameHistory>::iterator buf_it;
1428
1429 for (ThreadID tid = 0; tid < numThreads; tid++) {
1430
1431 buf_it = historyBuffer[tid].begin();
1432
1433 while (buf_it != historyBuffer[tid].end()) {
1434 cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys "
1435 "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg,
1436 (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg);
1437
1438 buf_it++;
1439 }
1440 }
1441}
1442
1443#endif//__CPU_O3_RENAME_IMPL_HH__