1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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126 renameROBFullEvents
127 .name(name() + ".ROBFullEvents")
128 .desc("Number of times rename has blocked due to ROB full")
129 .prereq(renameROBFullEvents);
130 renameIQFullEvents
131 .name(name() + ".IQFullEvents")
132 .desc("Number of times rename has blocked due to IQ full")
133 .prereq(renameIQFullEvents);
134 renameLSQFullEvents
135 .name(name() + ".LSQFullEvents")
136 .desc("Number of times rename has blocked due to LSQ full")
137 .prereq(renameLSQFullEvents);
138 renameFullRegistersEvents
139 .name(name() + ".FullRegisterEvents")
140 .desc("Number of times there has been no free registers")
141 .prereq(renameFullRegistersEvents);
142 renameRenamedOperands
143 .name(name() + ".RenamedOperands")
144 .desc("Number of destination operands rename has renamed")
145 .prereq(renameRenamedOperands);

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232 resumeSerialize = false;
233 resumeUnblocking = false;
234
235 // Grab the number of free entries directly from the stages.
236 for (ThreadID tid = 0; tid < numThreads; tid++) {
237 renameStatus[tid] = Idle;
238
239 freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid);
240 freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid);
241 freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid);
242 emptyROB[tid] = true;
243
244 stalls[tid].iew = false;
245 stalls[tid].commit = false;
246 serializeInst[tid] = NULL;
247
248 instsInProgress[tid] = 0;
249
250 serializeOnNextInst[tid] = false;
251 }
252}
253
254template<class Impl>
255void
256DefaultRename<Impl>::setActiveThreads(list<ThreadID> *at_ptr)

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415 removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum,
416 tid);
417 }
418 }
419
420 // @todo: make into updateProgress function
421 for (ThreadID tid = 0; tid < numThreads; tid++) {
422 instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched;
423
424 assert(instsInProgress[tid] >=0);
425 }
426
427}
428
429template<class Impl>
430void
431DefaultRename<Impl>::rename(bool &status_change, ThreadID tid)

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504 }
505
506 DynInstPtr inst;
507
508 // Will have to do a different calculation for the number of free
509 // entries.
510 int free_rob_entries = calcFreeROBEntries(tid);
511 int free_iq_entries = calcFreeIQEntries(tid);
512 int free_lsq_entries = calcFreeLSQEntries(tid);
513 int min_free_entries = free_rob_entries;
514
515 FullSource source = ROB;
516
517 if (free_iq_entries < min_free_entries) {
518 min_free_entries = free_iq_entries;
519 source = IQ;
520 }
521
522 if (free_lsq_entries < min_free_entries) {
523 min_free_entries = free_lsq_entries;
524 source = LSQ;
525 }
526
527 // Check if there's any space left.
528 if (min_free_entries <= 0) {
529 DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ "
530 "entries.\n"
531 "ROB has %i free entries.\n"
532 "IQ has %i free entries.\n"
533 "LSQ has %i free entries.\n",
534 tid,
535 free_rob_entries,
536 free_iq_entries,
537 free_lsq_entries);
538
539 blockThisCycle = true;
540
541 block(tid);
542
543 incrFullStat(source);
544
545 return;

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580
581 while (insts_available > 0 && toIEWIndex < renameWidth) {
582 DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid);
583
584 assert(!insts_to_rename.empty());
585
586 inst = insts_to_rename.front();
587
588 insts_to_rename.pop_front();
589
590 if (renameStatus[tid] == Unblocking) {
591 DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%s from rename "
592 "skidBuffer\n", tid, inst->seqNum, inst->pcState());
593 }
594
595 if (inst->isSquashed()) {

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660
661 serializeAfter(insts_to_rename, tid);
662 }
663
664 renameSrcRegs(inst, inst->threadNumber);
665
666 renameDestRegs(inst, inst->threadNumber);
667
668 ++renamed_insts;
669
670
671 // Put instruction in rename queue.
672 toIEW->insts[toIEWIndex] = inst;
673 ++(toIEW->size);
674
675 // Increment which instruction we're on.

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1117
1118 //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free);
1119
1120 return num_free;
1121}
1122
1123template <class Impl>
1124inline int
1125DefaultRename<Impl>::calcFreeLSQEntries(ThreadID tid)
1126{
1127 int num_free = freeEntries[tid].lsqEntries -
1128 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ);
1129
1130 //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free);
1131
1132 return num_free;
1133}
1134
1135template <class Impl>
1136unsigned
1137DefaultRename<Impl>::validInsts()
1138{
1139 unsigned inst_count = 0;
1140

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1182 DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid);
1183 ret_val = true;
1184 } else if (calcFreeROBEntries(tid) <= 0) {
1185 DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid);
1186 ret_val = true;
1187 } else if (calcFreeIQEntries(tid) <= 0) {
1188 DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid);
1189 ret_val = true;
1190 } else if (calcFreeLSQEntries(tid) <= 0) {
1191 DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid);
1192 ret_val = true;
1193 } else if (renameMap[tid]->numFreeEntries() <= 0) {
1194 DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid);
1195 ret_val = true;
1196 } else if (renameStatus[tid] == SerializeStall &&
1197 (!emptyROB[tid] || instsInProgress[tid])) {
1198 DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not "

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1206
1207template <class Impl>
1208void
1209DefaultRename<Impl>::readFreeEntries(ThreadID tid)
1210{
1211 if (fromIEW->iewInfo[tid].usedIQ)
1212 freeEntries[tid].iqEntries = fromIEW->iewInfo[tid].freeIQEntries;
1213
1214 if (fromIEW->iewInfo[tid].usedLSQ)
1215 freeEntries[tid].lsqEntries = fromIEW->iewInfo[tid].freeLSQEntries;
1216
1217 if (fromCommit->commitInfo[tid].usedROB) {
1218 freeEntries[tid].robEntries =
1219 fromCommit->commitInfo[tid].freeROBEntries;
1220 emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB;
1221 }
1222
1223 DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n",
1224 tid,
1225 freeEntries[tid].iqEntries,
1226 freeEntries[tid].robEntries,
1227 freeEntries[tid].lsqEntries);
1228
1229 DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n",
1230 tid, instsInProgress[tid]);
1231}
1232
1233template <class Impl>
1234bool
1235DefaultRename<Impl>::checkSignalsAndUpdate(ThreadID tid)

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1358{
1359 switch (source) {
1360 case ROB:
1361 ++renameROBFullEvents;
1362 break;
1363 case IQ:
1364 ++renameIQFullEvents;
1365 break;
1366 case LSQ:
1367 ++renameLSQFullEvents;
1368 break;
1369 default:
1370 panic("Rename full stall stat should be incremented for a reason!");
1371 break;
1372 }
1373}
1374
1375template <class Impl>
1376void

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