1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#include <list>
33
34#include "arch/isa_traits.hh"
35#include "arch/regfile.hh"
36#include "config/full_system.hh"
37#include "cpu/o3/rename.hh"
38
39template <class Impl>
40DefaultRename<Impl>::DefaultRename(Params *params)
41 : iewToRenameDelay(params->iewToRenameDelay),
42 decodeToRenameDelay(params->decodeToRenameDelay),
43 commitToRenameDelay(params->commitToRenameDelay),

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957
958 unsigned num_src_regs = inst->numSrcRegs();
959
960 // Get the architectual register numbers from the source and
961 // destination operands, and redirect them to the right register.
962 // Will need to mark dependencies though.
963 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) {
964 RegIndex src_reg = inst->srcRegIdx(src_idx);
965 RegIndex flat_src_reg = src_reg;
966 if (src_reg < TheISA::FP_Base_DepTag) {
967 flat_src_reg = TheISA::flattenIntIndex(inst->tcBase(), src_reg);
968 DPRINTF(Rename, "Flattening index %d to %d.\n", (int)src_reg, (int)flat_src_reg);
969 }
970 inst->flattenSrcReg(src_idx, flat_src_reg);
971
972 // Look up the source registers to get the phys. register they've
973 // been renamed to, and set the sources to those registers.
974 PhysRegIndex renamed_reg = renameMap[tid]->lookup(flat_src_reg);
975
976 DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got "
977 "physical reg %i.\n", tid, (int)flat_src_reg,
978 (int)renamed_reg);
979
980 inst->renameSrcReg(src_idx, renamed_reg);
981
982 // See if the register is ready or not.
983 if (scoreboard->getReg(renamed_reg) == true) {
984 DPRINTF(Rename, "[tid:%u]: Register is ready.\n", tid);
985

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996{
997 typename RenameMap::RenameInfo rename_result;
998
999 unsigned num_dest_regs = inst->numDestRegs();
1000
1001 // Rename the destination registers.
1002 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) {
1003 RegIndex dest_reg = inst->destRegIdx(dest_idx);
1004 RegIndex flat_dest_reg = dest_reg;
1005 if (dest_reg < TheISA::FP_Base_DepTag) {
1006 flat_dest_reg = TheISA::flattenIntIndex(inst->tcBase(), dest_reg);
1007 DPRINTF(Rename, "Flattening index %d to %d.\n", (int)dest_reg, (int)flat_dest_reg);
1008 }
1009
1010 inst->flattenDestReg(dest_idx, flat_dest_reg);
1011
1012 // Get the physical register that the destination will be
1013 // renamed to.
1014 rename_result = renameMap[tid]->rename(flat_dest_reg);
1015
1016 //Mark Scoreboard entry as not ready
1017 scoreboard->unsetReg(rename_result.first);
1018
1019 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical "
1020 "reg %i.\n", tid, (int)flat_dest_reg,
1021 (int)rename_result.first);
1022
1023 // Record the rename information so that a history can be kept.
1024 RenameHistory hb_entry(inst->seqNum, flat_dest_reg,
1025 rename_result.first,
1026 rename_result.second);
1027
1028 historyBuffer[tid].push_front(hb_entry);
1029
1030 DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer "
1031 "(size=%i), [sn:%lli].\n",tid,
1032 historyBuffer[tid].size(),

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