rename.hh (11246:93d2a1526103) rename.hh (12104:edd63f9c6184)
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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80 typedef typename CPUPol::RenameStruct RenameStruct;
81 typedef typename CPUPol::TimeStruct TimeStruct;
82 typedef typename CPUPol::FreeList FreeList;
83 typedef typename CPUPol::RenameMap RenameMap;
84 // These are used only for initialization.
85 typedef typename CPUPol::IEW IEW;
86 typedef typename CPUPol::Commit Commit;
87
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 71 unchanged lines hidden (view full) ---

80 typedef typename CPUPol::RenameStruct RenameStruct;
81 typedef typename CPUPol::TimeStruct TimeStruct;
82 typedef typename CPUPol::FreeList FreeList;
83 typedef typename CPUPol::RenameMap RenameMap;
84 // These are used only for initialization.
85 typedef typename CPUPol::IEW IEW;
86 typedef typename CPUPol::Commit Commit;
87
88 // Typedefs from the ISA.
89 typedef TheISA::RegIndex RegIndex;
90
91 // A deque is used to queue the instructions. Barrier insts must
92 // be added to the front of the queue, which is the only reason for
93 // using a deque instead of a queue. (Most other stages use a
94 // queue)
95 typedef std::deque<DynInstPtr> InstQueue;
96
97 public:
98 /** Overall rename status. Used to determine if the CPU can

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296 */
297 void serializeAfter(InstQueue &inst_list, ThreadID tid);
298
299 /** Holds the information for each destination register rename. It holds
300 * the instruction's sequence number, the arch register, the old physical
301 * register for that arch. register, and the new physical register.
302 */
303 struct RenameHistory {
88 // A deque is used to queue the instructions. Barrier insts must
89 // be added to the front of the queue, which is the only reason for
90 // using a deque instead of a queue. (Most other stages use a
91 // queue)
92 typedef std::deque<DynInstPtr> InstQueue;
93
94 public:
95 /** Overall rename status. Used to determine if the CPU can

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293 */
294 void serializeAfter(InstQueue &inst_list, ThreadID tid);
295
296 /** Holds the information for each destination register rename. It holds
297 * the instruction's sequence number, the arch register, the old physical
298 * register for that arch. register, and the new physical register.
299 */
300 struct RenameHistory {
304 RenameHistory(InstSeqNum _instSeqNum, RegIndex _archReg,
301 RenameHistory(InstSeqNum _instSeqNum, RegId _archReg,
305 PhysRegIndex _newPhysReg, PhysRegIndex _prevPhysReg)
306 : instSeqNum(_instSeqNum), archReg(_archReg),
307 newPhysReg(_newPhysReg), prevPhysReg(_prevPhysReg)
308 {
309 }
310
311 /** The sequence number of the instruction that renamed. */
312 InstSeqNum instSeqNum;
313 /** The architectural register index that was renamed. */
302 PhysRegIndex _newPhysReg, PhysRegIndex _prevPhysReg)
303 : instSeqNum(_instSeqNum), archReg(_archReg),
304 newPhysReg(_newPhysReg), prevPhysReg(_prevPhysReg)
305 {
306 }
307
308 /** The sequence number of the instruction that renamed. */
309 InstSeqNum instSeqNum;
310 /** The architectural register index that was renamed. */
314 RegIndex archReg;
311 RegId archReg;
315 /** The new physical register that the arch. register is renamed to. */
316 PhysRegIndex newPhysReg;
317 /** The old physical register that the arch. register was renamed to. */
318 PhysRegIndex prevPhysReg;
319 };
320
321 /** A per-thread list of all destination register renames, used to either
322 * undo rename mappings or free old physical registers.

--- 209 unchanged lines hidden --- 		312 /** The new physical register that the arch. register is renamed to. */
313 PhysRegIndex newPhysReg;
314 /** The old physical register that the arch. register was renamed to. */
315 PhysRegIndex prevPhysReg;
316 };
317
318 /** A per-thread list of all destination register renames, used to either
319 * undo rename mappings or free old physical registers.

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