2c2
< * Copyright (c) 2004-2005 The Regents of The University of Michigan
---
> * Copyright (c) 2004-2006 The Regents of The University of Michigan
31,34c31,32
< // Todo:
< // Fix up trap and barrier handling.
< // May want to have different statuses to differentiate the different stall
< // conditions.
---
> #ifndef __CPU_O3_RENAME_HH__
> #define __CPU_O3_RENAME_HH__
36,38d33
< #ifndef __CPU_O3_CPU_SIMPLE_RENAME_HH__
< #define __CPU_O3_CPU_SIMPLE_RENAME_HH__
<
44,45c39,50
< // Will need rename maps for both the int reg file and fp reg file.
< // Or change rename map class to handle both. (RegFile handles both.)
---
> /**
> * DefaultRename handles both single threaded and SMT rename. Its
> * width is specified by the parameters; each cycle it tries to rename
> * that many instructions. It holds onto the rename history of all
> * instructions with destination registers, storing the
> * arch. register, the new physical register, and the old physical
> * register, to allow for undoing of mappings if squashing happens, or
> * freeing up registers upon commit. Rename handles blocking if the
> * ROB, IQ, or LSQ is going to be full. Rename also handles barriers,
> * and does so by stalling on the instruction until the ROB is empty
> * and there are no instructions in flight to the ROB.
> */
47c52
< class SimpleRename
---
> class DefaultRename
56c61
< typedef typename CPUPol::FetchStruct FetchStruct;
---
> // Typedefs from the CPUPol
60,61d64
<
< // Typedefs from the CPUPol
63a67,69
> // These are used only for initialization.
> typedef typename CPUPol::IEW IEW;
> typedef typename CPUPol::Commit Commit;
67a74,79
> // A list is used to queue the instructions. Barrier insts must
> // be added to the front of the list, which is the only reason for
> // using a list instead of a queue. (Most other stages use a
> // queue)
> typedef std::list<DynInstPtr> InstQueue;
>
69,72c81,90
< // Rename will block if ROB becomes full or issue queue becomes full,
< // or there are no free registers to rename to.
< // Only case where rename squashes is if IEW squashes.
< enum Status {
---
> /** Overall rename status. Used to determine if the CPU can
> * deschedule itself due to a lack of activity.
> */
> enum RenameStatus {
> Active,
> Inactive
> };
>
> /** Individual thread status. */
> enum ThreadStatus {
74a93
> StartSquash,
78c97
< BarrierStall
---
> SerializeStall
82c101,102
< Status _status;
---
> /** Rename status. */
> RenameStatus _status;
83a104,106
> /** Per-thread status. */
> ThreadStatus renameStatus[Impl::MaxThreads];
>
85c108,109
< SimpleRename(Params ¶ms);
---
> /** DefaultRename constructor. */
> DefaultRename(Params *params);
86a111,114
> /** Returns the name of rename. */
> std::string name() const;
>
> /** Registers statistics. */
88a117
> /** Sets CPU pointer. */
90a120
> /** Sets the main backwards communication time buffer pointer. */
92a123
> /** Sets pointer to time buffer used to communicate to the next stage. */
94a126
> /** Sets pointer to time buffer coming from decode. */
97c129,131
< void setRenameMap(RenameMap *rm_ptr);
---
> /** Sets pointer to IEW stage. Used only for initialization. */
> void setIEWStage(IEW *iew_stage)
> { iew_ptr = iew_stage; }
98a133,154
> /** Sets pointer to commit stage. Used only for initialization. */
> void setCommitStage(Commit *commit_stage)
> { commit_ptr = commit_stage; }
>
> private:
> /** Pointer to IEW stage. Used only for initialization. */
> IEW *iew_ptr;
>
> /** Pointer to commit stage. Used only for initialization. */
> Commit *commit_ptr;
>
> public:
> /** Initializes variables for the stage. */
> void initStage();
>
> /** Sets pointer to list of active threads. */
> void setActiveThreads(std::list<unsigned> *at_ptr);
>
> /** Sets pointer to rename maps (per-thread structures). */
> void setRenameMap(RenameMap rm_ptr[Impl::MaxThreads]);
>
> /** Sets pointer to the free list. */
101c157,158
< void dumpHistory();
---
> /** Sets pointer to the scoreboard. */
> void setScoreboard(Scoreboard *_scoreboard);
103c160
< void tick();
---
> void switchOut();
105c162
< void rename();
---
> void doSwitchOut();
107c164
< void squash();
---
> void takeOverFrom();
108a166,176
> /** Squashes all instructions in a thread. */
> void squash(unsigned tid);
>
> /** Ticks rename, which processes all input signals and attempts to rename
> * as many instructions as possible.
> */
> void tick();
>
> /** Debugging function used to dump history buffer of renamings. */
> void dumpHistory();
>
110c178,183
< void block();
---
> /** Determines what to do based on rename's current status.
> * @param status_change rename() sets this variable if there was a status
> * change (ie switching from blocking to unblocking).
> * @param tid Thread id to rename instructions from.
> */
> void rename(bool &status_change, unsigned tid);
112c185,188
< inline void unblock();
---
> /** Renames instructions for the given thread. Also handles serializing
> * instructions.
> */
> void renameInsts(unsigned tid);
114c190,193
< void doSquash();
---
> /** Inserts unused instructions from a given thread into the skid buffer,
> * to be renamed once rename unblocks.
> */
> void skidInsert(unsigned tid);
116c195,198
< void removeFromHistory(InstSeqNum inst_seq_num);
---
> /** Separates instructions from decode into individual lists of instructions
> * sorted by thread.
> */
> void sortInsts();
118c200,201
< inline void renameSrcRegs(DynInstPtr &inst);
---
> /** Returns if all of the skid buffers are empty. */
> bool skidsEmpty();
120c203,204
< inline void renameDestRegs(DynInstPtr &inst);
---
> /** Updates overall rename status based on all of the threads' statuses. */
> void updateStatus();
122c206,210
< inline int calcFreeROBEntries();
---
> /** Switches rename to blocking, and signals back that rename has become
> * blocked.
> * @return Returns true if there is a status change.
> */
> bool block(unsigned tid);
124c212,216
< inline int calcFreeIQEntries();
---
> /** Switches rename to unblocking if the skid buffer is empty, and signals
> * back that rename has unblocked.
> * @return Returns true if there is a status change.
> */
> bool unblock(unsigned tid);
126,128c218,257
< /** Holds the previous information for each rename.
< * Note that often times the inst may have been deleted, so only access
< * the pointer for the address and do not dereference it.
---
> /** Executes actual squash, removing squashed instructions. */
> void doSquash(unsigned tid);
>
> /** Removes a committed instruction's rename history. */
> void removeFromHistory(InstSeqNum inst_seq_num, unsigned tid);
>
> /** Renames the source registers of an instruction. */
> inline void renameSrcRegs(DynInstPtr &inst, unsigned tid);
>
> /** Renames the destination registers of an instruction. */
> inline void renameDestRegs(DynInstPtr &inst, unsigned tid);
>
> /** Calculates the number of free ROB entries for a specific thread. */
> inline int calcFreeROBEntries(unsigned tid);
>
> /** Calculates the number of free IQ entries for a specific thread. */
> inline int calcFreeIQEntries(unsigned tid);
>
> /** Calculates the number of free LSQ entries for a specific thread. */
> inline int calcFreeLSQEntries(unsigned tid);
>
> /** Returns the number of valid instructions coming from decode. */
> unsigned validInsts();
>
> /** Reads signals telling rename to block/unblock. */
> void readStallSignals(unsigned tid);
>
> /** Checks if any stages are telling rename to block. */
> bool checkStall(unsigned tid);
>
> void readFreeEntries(unsigned tid);
>
> bool checkSignalsAndUpdate(unsigned tid);
>
> /** Either serializes on the next instruction available in the InstQueue,
> * or records that it must serialize on the next instruction to enter
> * rename.
> * @param inst_list The list of younger, unprocessed instructions for the
> * thread that has the serializeAfter instruction.
> * @param tid The thread id.
129a259,264
> void serializeAfter(InstQueue &inst_list, unsigned tid);
>
> /** Holds the information for each destination register rename. It holds
> * the instruction's sequence number, the arch register, the old physical
> * register for that arch. register, and the new physical register.
> */
134,135c269
< newPhysReg(_newPhysReg), prevPhysReg(_prevPhysReg),
< placeHolder(false)
---
> newPhysReg(_newPhysReg), prevPhysReg(_prevPhysReg)
139,147c273
< /** Constructor used specifically for cases where a place holder
< * rename history entry is being made.
< */
< RenameHistory(InstSeqNum _instSeqNum)
< : instSeqNum(_instSeqNum), archReg(0), newPhysReg(0),
< prevPhysReg(0), placeHolder(true)
< {
< }
<
---
> /** The sequence number of the instruction that renamed. */
148a275
> /** The architectural register index that was renamed. */
149a277
> /** The new physical register that the arch. register is renamed to. */
150a279
> /** The old physical register that the arch. register was renamed to. */
152d280
< bool placeHolder;
155c283,286
< std::list<RenameHistory> historyBuffer;
---
> /** A per-thread list of all destination register renames, used to either
> * undo rename mappings or free old physical registers.
> */
> std::list<RenameHistory> historyBuffer[Impl::MaxThreads];
157c288
< /** CPU interface. */
---
> /** Pointer to CPU. */
160,161c291
< // Interfaces to objects outside of rename.
< /** Time buffer interface. */
---
> /** Pointer to main time buffer used for backwards communication. */
171d300
< // Might not be the best name as not only decode will read it.
185a315,317
> /** Queue of all instructions coming from decode this cycle. */
> InstQueue insts[Impl::MaxThreads];
>
187c319
< std::queue<DecodeStruct> skidBuffer;
---
> InstQueue skidBuffer[Impl::MaxThreads];
190c322
< SimpleRenameMap *renameMap;
---
> RenameMap *renameMap[Impl::MaxThreads];
194a327,379
> /** Pointer to the list of active threads. */
> std::list<unsigned> *activeThreads;
>
> /** Pointer to the scoreboard. */
> Scoreboard *scoreboard;
>
> /** Count of instructions in progress that have been sent off to the IQ
> * and ROB, but are not yet included in their occupancy counts.
> */
> int instsInProgress[Impl::MaxThreads];
>
> /** Variable that tracks if decode has written to the time buffer this
> * cycle. Used to tell CPU if there is activity this cycle.
> */
> bool wroteToTimeBuffer;
>
> /** Structures whose free entries impact the amount of instructions that
> * can be renamed.
> */
> struct FreeEntries {
> unsigned iqEntries;
> unsigned lsqEntries;
> unsigned robEntries;
> };
>
> /** Per-thread tracking of the number of free entries of back-end
> * structures.
> */
> FreeEntries freeEntries[Impl::MaxThreads];
>
> /** Records if the ROB is empty. In SMT mode the ROB may be dynamically
> * partitioned between threads, so the ROB must tell rename when it is
> * empty.
> */
> bool emptyROB[Impl::MaxThreads];
>
> /** Source of possible stalls. */
> struct Stalls {
> bool iew;
> bool commit;
> };
>
> /** Tracks which stages are telling decode to stall. */
> Stalls stalls[Impl::MaxThreads];
>
> /** The serialize instruction that rename has stalled on. */
> DynInstPtr serializeInst[Impl::MaxThreads];
>
> /** Records if rename needs to serialize on the next instruction for any
> * thread.
> */
> bool serializeOnNextInst[Impl::MaxThreads];
>
212,214c397,398
< /** The instruction that rename is currently on. It needs to have
< * persistent state so that when a stall occurs in the middle of a
< * group of instructions, it can restart at the proper instruction.
---
> /** The index of the instruction in the time buffer to IEW that rename is
> * currently using.
216c400
< unsigned numInst;
---
> unsigned toIEWIndex;
217a402,426
> /** Whether or not rename needs to block this cycle. */
> bool blockThisCycle;
>
> /** The number of threads active in rename. */
> unsigned numThreads;
>
> /** The maximum skid buffer size. */
> unsigned skidBufferMax;
>
> /** Enum to record the source of a structure full stall. Can come from
> * either ROB, IQ, LSQ, and it is priortized in that order.
> */
> enum FullSource {
> ROB,
> IQ,
> LSQ,
> NONE
> };
>
> /** Function used to increment the stat that corresponds to the source of
> * the stall.
> */
> inline void incrFullStat(const FullSource &source);
>
> /** Stat for total number of cycles spent squashing. */
218a428
> /** Stat for total number of cycles spent idle. */
219a430
> /** Stat for total number of cycles spent blocking. */
220a432,436
> /** Stat for total number of cycles spent stalling for a serializing inst. */
> Stats::Scalar<> renameSerializeStallCycles;
> /** Stat for total number of cycles spent running normally. */
> Stats::Scalar<> renameRunCycles;
> /** Stat for total number of cycles spent unblocking. */
221a438
> /** Stat for total number of renamed instructions. */
222a440
> /** Stat for total number of squashed instructions that rename discards. */
223a442
> /** Stat for total number of times that the ROB starts a stall in rename. */
224a444
> /** Stat for total number of times that the IQ starts a stall in rename. */
225a446,449
> /** Stat for total number of times that the LSQ starts a stall in rename. */
> Stats::Scalar<> renameLSQFullEvents;
> /** Stat for total number of times that rename runs out of free registers
> * to use to rename. */
226a451
> /** Stat for total number of renamed destination registers. */
227a453
> /** Stat for total number of source register rename lookups. */
229c455
< Stats::Scalar<> renameHBPlaceHolders;
---
> /** Stat for total number of committed renaming mappings. */
230a457
> /** Stat for total number of mappings that were undone due to a squash. */
232c459,461
< Stats::Scalar<> renameValidUndoneMaps;
---
> Stats::Scalar<> renamedSerializing;
> Stats::Scalar<> renamedTempSerializing;
> Stats::Scalar<> renameSkidInsts;
235c464
< #endif // __CPU_O3_CPU_SIMPLE_RENAME_HH__
---
> #endif // __CPU_O3_RENAME_HH__
< * Copyright (c) 2004-2005 The Regents of The University of Michigan
---
> * Copyright (c) 2004-2006 The Regents of The University of Michigan
31,34c31,32
< // Todo:
< // Fix up trap and barrier handling.
< // May want to have different statuses to differentiate the different stall
< // conditions.
---
> #ifndef __CPU_O3_RENAME_HH__
> #define __CPU_O3_RENAME_HH__
36,38d33
< #ifndef __CPU_O3_CPU_SIMPLE_RENAME_HH__
< #define __CPU_O3_CPU_SIMPLE_RENAME_HH__
<
44,45c39,50
< // Will need rename maps for both the int reg file and fp reg file.
< // Or change rename map class to handle both. (RegFile handles both.)
---
> /**
> * DefaultRename handles both single threaded and SMT rename. Its
> * width is specified by the parameters; each cycle it tries to rename
> * that many instructions. It holds onto the rename history of all
> * instructions with destination registers, storing the
> * arch. register, the new physical register, and the old physical
> * register, to allow for undoing of mappings if squashing happens, or
> * freeing up registers upon commit. Rename handles blocking if the
> * ROB, IQ, or LSQ is going to be full. Rename also handles barriers,
> * and does so by stalling on the instruction until the ROB is empty
> * and there are no instructions in flight to the ROB.
> */
47c52
< class SimpleRename
---
> class DefaultRename
56c61
< typedef typename CPUPol::FetchStruct FetchStruct;
---
> // Typedefs from the CPUPol
60,61d64
<
< // Typedefs from the CPUPol
63a67,69
> // These are used only for initialization.
> typedef typename CPUPol::IEW IEW;
> typedef typename CPUPol::Commit Commit;
67a74,79
> // A list is used to queue the instructions. Barrier insts must
> // be added to the front of the list, which is the only reason for
> // using a list instead of a queue. (Most other stages use a
> // queue)
> typedef std::list<DynInstPtr> InstQueue;
>
69,72c81,90
< // Rename will block if ROB becomes full or issue queue becomes full,
< // or there are no free registers to rename to.
< // Only case where rename squashes is if IEW squashes.
< enum Status {
---
> /** Overall rename status. Used to determine if the CPU can
> * deschedule itself due to a lack of activity.
> */
> enum RenameStatus {
> Active,
> Inactive
> };
>
> /** Individual thread status. */
> enum ThreadStatus {
74a93
> StartSquash,
78c97
< BarrierStall
---
> SerializeStall
82c101,102
< Status _status;
---
> /** Rename status. */
> RenameStatus _status;
83a104,106
> /** Per-thread status. */
> ThreadStatus renameStatus[Impl::MaxThreads];
>
85c108,109
< SimpleRename(Params ¶ms);
---
> /** DefaultRename constructor. */
> DefaultRename(Params *params);
86a111,114
> /** Returns the name of rename. */
> std::string name() const;
>
> /** Registers statistics. */
88a117
> /** Sets CPU pointer. */
90a120
> /** Sets the main backwards communication time buffer pointer. */
92a123
> /** Sets pointer to time buffer used to communicate to the next stage. */
94a126
> /** Sets pointer to time buffer coming from decode. */
97c129,131
< void setRenameMap(RenameMap *rm_ptr);
---
> /** Sets pointer to IEW stage. Used only for initialization. */
> void setIEWStage(IEW *iew_stage)
> { iew_ptr = iew_stage; }
98a133,154
> /** Sets pointer to commit stage. Used only for initialization. */
> void setCommitStage(Commit *commit_stage)
> { commit_ptr = commit_stage; }
>
> private:
> /** Pointer to IEW stage. Used only for initialization. */
> IEW *iew_ptr;
>
> /** Pointer to commit stage. Used only for initialization. */
> Commit *commit_ptr;
>
> public:
> /** Initializes variables for the stage. */
> void initStage();
>
> /** Sets pointer to list of active threads. */
> void setActiveThreads(std::list<unsigned> *at_ptr);
>
> /** Sets pointer to rename maps (per-thread structures). */
> void setRenameMap(RenameMap rm_ptr[Impl::MaxThreads]);
>
> /** Sets pointer to the free list. */
101c157,158
< void dumpHistory();
---
> /** Sets pointer to the scoreboard. */
> void setScoreboard(Scoreboard *_scoreboard);
103c160
< void tick();
---
> void switchOut();
105c162
< void rename();
---
> void doSwitchOut();
107c164
< void squash();
---
> void takeOverFrom();
108a166,176
> /** Squashes all instructions in a thread. */
> void squash(unsigned tid);
>
> /** Ticks rename, which processes all input signals and attempts to rename
> * as many instructions as possible.
> */
> void tick();
>
> /** Debugging function used to dump history buffer of renamings. */
> void dumpHistory();
>
110c178,183
< void block();
---
> /** Determines what to do based on rename's current status.
> * @param status_change rename() sets this variable if there was a status
> * change (ie switching from blocking to unblocking).
> * @param tid Thread id to rename instructions from.
> */
> void rename(bool &status_change, unsigned tid);
112c185,188
< inline void unblock();
---
> /** Renames instructions for the given thread. Also handles serializing
> * instructions.
> */
> void renameInsts(unsigned tid);
114c190,193
< void doSquash();
---
> /** Inserts unused instructions from a given thread into the skid buffer,
> * to be renamed once rename unblocks.
> */
> void skidInsert(unsigned tid);
116c195,198
< void removeFromHistory(InstSeqNum inst_seq_num);
---
> /** Separates instructions from decode into individual lists of instructions
> * sorted by thread.
> */
> void sortInsts();
118c200,201
< inline void renameSrcRegs(DynInstPtr &inst);
---
> /** Returns if all of the skid buffers are empty. */
> bool skidsEmpty();
120c203,204
< inline void renameDestRegs(DynInstPtr &inst);
---
> /** Updates overall rename status based on all of the threads' statuses. */
> void updateStatus();
122c206,210
< inline int calcFreeROBEntries();
---
> /** Switches rename to blocking, and signals back that rename has become
> * blocked.
> * @return Returns true if there is a status change.
> */
> bool block(unsigned tid);
124c212,216
< inline int calcFreeIQEntries();
---
> /** Switches rename to unblocking if the skid buffer is empty, and signals
> * back that rename has unblocked.
> * @return Returns true if there is a status change.
> */
> bool unblock(unsigned tid);
126,128c218,257
< /** Holds the previous information for each rename.
< * Note that often times the inst may have been deleted, so only access
< * the pointer for the address and do not dereference it.
---
> /** Executes actual squash, removing squashed instructions. */
> void doSquash(unsigned tid);
>
> /** Removes a committed instruction's rename history. */
> void removeFromHistory(InstSeqNum inst_seq_num, unsigned tid);
>
> /** Renames the source registers of an instruction. */
> inline void renameSrcRegs(DynInstPtr &inst, unsigned tid);
>
> /** Renames the destination registers of an instruction. */
> inline void renameDestRegs(DynInstPtr &inst, unsigned tid);
>
> /** Calculates the number of free ROB entries for a specific thread. */
> inline int calcFreeROBEntries(unsigned tid);
>
> /** Calculates the number of free IQ entries for a specific thread. */
> inline int calcFreeIQEntries(unsigned tid);
>
> /** Calculates the number of free LSQ entries for a specific thread. */
> inline int calcFreeLSQEntries(unsigned tid);
>
> /** Returns the number of valid instructions coming from decode. */
> unsigned validInsts();
>
> /** Reads signals telling rename to block/unblock. */
> void readStallSignals(unsigned tid);
>
> /** Checks if any stages are telling rename to block. */
> bool checkStall(unsigned tid);
>
> void readFreeEntries(unsigned tid);
>
> bool checkSignalsAndUpdate(unsigned tid);
>
> /** Either serializes on the next instruction available in the InstQueue,
> * or records that it must serialize on the next instruction to enter
> * rename.
> * @param inst_list The list of younger, unprocessed instructions for the
> * thread that has the serializeAfter instruction.
> * @param tid The thread id.
129a259,264
> void serializeAfter(InstQueue &inst_list, unsigned tid);
>
> /** Holds the information for each destination register rename. It holds
> * the instruction's sequence number, the arch register, the old physical
> * register for that arch. register, and the new physical register.
> */
134,135c269
< newPhysReg(_newPhysReg), prevPhysReg(_prevPhysReg),
< placeHolder(false)
---
> newPhysReg(_newPhysReg), prevPhysReg(_prevPhysReg)
139,147c273
< /** Constructor used specifically for cases where a place holder
< * rename history entry is being made.
< */
< RenameHistory(InstSeqNum _instSeqNum)
< : instSeqNum(_instSeqNum), archReg(0), newPhysReg(0),
< prevPhysReg(0), placeHolder(true)
< {
< }
<
---
> /** The sequence number of the instruction that renamed. */
148a275
> /** The architectural register index that was renamed. */
149a277
> /** The new physical register that the arch. register is renamed to. */
150a279
> /** The old physical register that the arch. register was renamed to. */
152d280
< bool placeHolder;
155c283,286
< std::list<RenameHistory> historyBuffer;
---
> /** A per-thread list of all destination register renames, used to either
> * undo rename mappings or free old physical registers.
> */
> std::list<RenameHistory> historyBuffer[Impl::MaxThreads];
157c288
< /** CPU interface. */
---
> /** Pointer to CPU. */
160,161c291
< // Interfaces to objects outside of rename.
< /** Time buffer interface. */
---
> /** Pointer to main time buffer used for backwards communication. */
171d300
< // Might not be the best name as not only decode will read it.
185a315,317
> /** Queue of all instructions coming from decode this cycle. */
> InstQueue insts[Impl::MaxThreads];
>
187c319
< std::queue<DecodeStruct> skidBuffer;
---
> InstQueue skidBuffer[Impl::MaxThreads];
190c322
< SimpleRenameMap *renameMap;
---
> RenameMap *renameMap[Impl::MaxThreads];
194a327,379
> /** Pointer to the list of active threads. */
> std::list<unsigned> *activeThreads;
>
> /** Pointer to the scoreboard. */
> Scoreboard *scoreboard;
>
> /** Count of instructions in progress that have been sent off to the IQ
> * and ROB, but are not yet included in their occupancy counts.
> */
> int instsInProgress[Impl::MaxThreads];
>
> /** Variable that tracks if decode has written to the time buffer this
> * cycle. Used to tell CPU if there is activity this cycle.
> */
> bool wroteToTimeBuffer;
>
> /** Structures whose free entries impact the amount of instructions that
> * can be renamed.
> */
> struct FreeEntries {
> unsigned iqEntries;
> unsigned lsqEntries;
> unsigned robEntries;
> };
>
> /** Per-thread tracking of the number of free entries of back-end
> * structures.
> */
> FreeEntries freeEntries[Impl::MaxThreads];
>
> /** Records if the ROB is empty. In SMT mode the ROB may be dynamically
> * partitioned between threads, so the ROB must tell rename when it is
> * empty.
> */
> bool emptyROB[Impl::MaxThreads];
>
> /** Source of possible stalls. */
> struct Stalls {
> bool iew;
> bool commit;
> };
>
> /** Tracks which stages are telling decode to stall. */
> Stalls stalls[Impl::MaxThreads];
>
> /** The serialize instruction that rename has stalled on. */
> DynInstPtr serializeInst[Impl::MaxThreads];
>
> /** Records if rename needs to serialize on the next instruction for any
> * thread.
> */
> bool serializeOnNextInst[Impl::MaxThreads];
>
212,214c397,398
< /** The instruction that rename is currently on. It needs to have
< * persistent state so that when a stall occurs in the middle of a
< * group of instructions, it can restart at the proper instruction.
---
> /** The index of the instruction in the time buffer to IEW that rename is
> * currently using.
216c400
< unsigned numInst;
---
> unsigned toIEWIndex;
217a402,426
> /** Whether or not rename needs to block this cycle. */
> bool blockThisCycle;
>
> /** The number of threads active in rename. */
> unsigned numThreads;
>
> /** The maximum skid buffer size. */
> unsigned skidBufferMax;
>
> /** Enum to record the source of a structure full stall. Can come from
> * either ROB, IQ, LSQ, and it is priortized in that order.
> */
> enum FullSource {
> ROB,
> IQ,
> LSQ,
> NONE
> };
>
> /** Function used to increment the stat that corresponds to the source of
> * the stall.
> */
> inline void incrFullStat(const FullSource &source);
>
> /** Stat for total number of cycles spent squashing. */
218a428
> /** Stat for total number of cycles spent idle. */
219a430
> /** Stat for total number of cycles spent blocking. */
220a432,436
> /** Stat for total number of cycles spent stalling for a serializing inst. */
> Stats::Scalar<> renameSerializeStallCycles;
> /** Stat for total number of cycles spent running normally. */
> Stats::Scalar<> renameRunCycles;
> /** Stat for total number of cycles spent unblocking. */
221a438
> /** Stat for total number of renamed instructions. */
222a440
> /** Stat for total number of squashed instructions that rename discards. */
223a442
> /** Stat for total number of times that the ROB starts a stall in rename. */
224a444
> /** Stat for total number of times that the IQ starts a stall in rename. */
225a446,449
> /** Stat for total number of times that the LSQ starts a stall in rename. */
> Stats::Scalar<> renameLSQFullEvents;
> /** Stat for total number of times that rename runs out of free registers
> * to use to rename. */
226a451
> /** Stat for total number of renamed destination registers. */
227a453
> /** Stat for total number of source register rename lookups. */
229c455
< Stats::Scalar<> renameHBPlaceHolders;
---
> /** Stat for total number of committed renaming mappings. */
230a457
> /** Stat for total number of mappings that were undone due to a squash. */
232c459,461
< Stats::Scalar<> renameValidUndoneMaps;
---
> Stats::Scalar<> renamedSerializing;
> Stats::Scalar<> renamedTempSerializing;
> Stats::Scalar<> renameSkidInsts;
235c464
< #endif // __CPU_O3_CPU_SIMPLE_RENAME_HH__
---
> #endif // __CPU_O3_RENAME_HH__