1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_O3_RENAME_HH__
32#define __CPU_O3_RENAME_HH__
33
34#include <list>
35
36#include "base/statistics.hh"
37#include "cpu/timebuf.hh"
38#include "config/the_isa.hh"
39
40class DerivO3CPUParams;
41
42/**
43 * DefaultRename handles both single threaded and SMT rename. Its
44 * width is specified by the parameters; each cycle it tries to rename
45 * that many instructions. It holds onto the rename history of all
46 * instructions with destination registers, storing the
47 * arch. register, the new physical register, and the old physical
48 * register, to allow for undoing of mappings if squashing happens, or
49 * freeing up registers upon commit. Rename handles blocking if the
50 * ROB, IQ, or LSQ is going to be full. Rename also handles barriers,
51 * and does so by stalling on the instruction until the ROB is empty
52 * and there are no instructions in flight to the ROB.
53 */
54template<class Impl>
55class DefaultRename
56{
57 public:
58 // Typedefs from the Impl.
59 typedef typename Impl::CPUPol CPUPol;
60 typedef typename Impl::DynInstPtr DynInstPtr;
61 typedef typename Impl::O3CPU O3CPU;
62
63 // Typedefs from the CPUPol
64 typedef typename CPUPol::DecodeStruct DecodeStruct;
65 typedef typename CPUPol::RenameStruct RenameStruct;
66 typedef typename CPUPol::TimeStruct TimeStruct;
67 typedef typename CPUPol::FreeList FreeList;
68 typedef typename CPUPol::RenameMap RenameMap;
69 // These are used only for initialization.
70 typedef typename CPUPol::IEW IEW;
71 typedef typename CPUPol::Commit Commit;
72
73 // Typedefs from the ISA.
74 typedef TheISA::RegIndex RegIndex;
75
76 // A list is used to queue the instructions. Barrier insts must
77 // be added to the front of the list, which is the only reason for
78 // using a list instead of a queue. (Most other stages use a
79 // queue)
80 typedef std::list<DynInstPtr> InstQueue;
81 typedef typename std::list<DynInstPtr>::iterator ListIt;
82
83 public:
84 /** Overall rename status. Used to determine if the CPU can
85 * deschedule itself due to a lack of activity.
86 */
87 enum RenameStatus {
88 Active,
89 Inactive
90 };
91
92 /** Individual thread status. */
93 enum ThreadStatus {
94 Running,
95 Idle,
96 StartSquash,
97 Squashing,
98 Blocked,
99 Unblocking,
100 SerializeStall
101 };
102
103 private:
104 /** Rename status. */
105 RenameStatus _status;
106
107 /** Per-thread status. */
108 ThreadStatus renameStatus[Impl::MaxThreads];
109
110 public:
111 /** DefaultRename constructor. */
112 DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params);
113
114 /** Returns the name of rename. */
115 std::string name() const;
116
117 /** Registers statistics. */
118 void regStats();
119
120 /** Sets the main backwards communication time buffer pointer. */
121 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
122
123 /** Sets pointer to time buffer used to communicate to the next stage. */
124 void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
125
126 /** Sets pointer to time buffer coming from decode. */
127 void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr);
128
129 /** Sets pointer to IEW stage. Used only for initialization. */
130 void setIEWStage(IEW *iew_stage)
131 { iew_ptr = iew_stage; }
132
133 /** Sets pointer to commit stage. Used only for initialization. */
134 void setCommitStage(Commit *commit_stage)
135 { commit_ptr = commit_stage; }
136
137 private:
138 /** Pointer to IEW stage. Used only for initialization. */
139 IEW *iew_ptr;
140
141 /** Pointer to commit stage. Used only for initialization. */
142 Commit *commit_ptr;
143
144 public:
145 /** Initializes variables for the stage. */
146 void initStage();
147
148 /** Sets pointer to list of active threads. */
149 void setActiveThreads(std::list<ThreadID> *at_ptr);
150
151 /** Sets pointer to rename maps (per-thread structures). */
152 void setRenameMap(RenameMap rm_ptr[Impl::MaxThreads]);
153
154 /** Sets pointer to the free list. */
155 void setFreeList(FreeList *fl_ptr);
156
157 /** Sets pointer to the scoreboard. */
158 void setScoreboard(Scoreboard *_scoreboard);
159
160 /** Drains the rename stage. */
161 bool drain();
162
163 /** Resumes execution after a drain. */
164 void resume() { }
165
166 /** Switches out the rename stage. */
167 void switchOut();
168
169 /** Takes over from another CPU's thread. */
170 void takeOverFrom();
171
172 /** Squashes all instructions in a thread. */
173 void squash(const InstSeqNum &squash_seq_num, ThreadID tid);
174
175 /** Ticks rename, which processes all input signals and attempts to rename
176 * as many instructions as possible.
177 */
178 void tick();
179
180 /** Debugging function used to dump history buffer of renamings. */
181 void dumpHistory();
182
183 private:
184 /** Determines what to do based on rename's current status.
185 * @param status_change rename() sets this variable if there was a status
186 * change (ie switching from blocking to unblocking).
187 * @param tid Thread id to rename instructions from.
188 */
189 void rename(bool &status_change, ThreadID tid);
190
191 /** Renames instructions for the given thread. Also handles serializing
192 * instructions.
193 */
194 void renameInsts(ThreadID tid);
195
196 /** Inserts unused instructions from a given thread into the skid buffer,
197 * to be renamed once rename unblocks.
198 */
199 void skidInsert(ThreadID tid);
200
201 /** Separates instructions from decode into individual lists of instructions
202 * sorted by thread.
203 */
204 void sortInsts();
205
206 /** Returns if all of the skid buffers are empty. */
207 bool skidsEmpty();
208
209 /** Updates overall rename status based on all of the threads' statuses. */
210 void updateStatus();
211
212 /** Switches rename to blocking, and signals back that rename has become
213 * blocked.
214 * @return Returns true if there is a status change.
215 */
216 bool block(ThreadID tid);
217
218 /** Switches rename to unblocking if the skid buffer is empty, and signals
219 * back that rename has unblocked.
220 * @return Returns true if there is a status change.
221 */
222 bool unblock(ThreadID tid);
223
224 /** Executes actual squash, removing squashed instructions. */
225 void doSquash(const InstSeqNum &squash_seq_num, ThreadID tid);
226
227 /** Removes a committed instruction's rename history. */
228 void removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid);
229
230 /** Renames the source registers of an instruction. */
231 inline void renameSrcRegs(DynInstPtr &inst, ThreadID tid);
232
233 /** Renames the destination registers of an instruction. */
234 inline void renameDestRegs(DynInstPtr &inst, ThreadID tid);
235
236 /** Calculates the number of free ROB entries for a specific thread. */
237 inline int calcFreeROBEntries(ThreadID tid);
238
239 /** Calculates the number of free IQ entries for a specific thread. */
240 inline int calcFreeIQEntries(ThreadID tid);
241
242 /** Calculates the number of free LSQ entries for a specific thread. */
243 inline int calcFreeLSQEntries(ThreadID tid);
244
245 /** Returns the number of valid instructions coming from decode. */
246 unsigned validInsts();
247
248 /** Reads signals telling rename to block/unblock. */
249 void readStallSignals(ThreadID tid);
250
251 /** Checks if any stages are telling rename to block. */
252 bool checkStall(ThreadID tid);
253
254 /** Gets the number of free entries for a specific thread. */
255 void readFreeEntries(ThreadID tid);
256
257 /** Checks the signals and updates the status. */
258 bool checkSignalsAndUpdate(ThreadID tid);
259
260 /** Either serializes on the next instruction available in the InstQueue,
261 * or records that it must serialize on the next instruction to enter
262 * rename.
263 * @param inst_list The list of younger, unprocessed instructions for the
264 * thread that has the serializeAfter instruction.
265 * @param tid The thread id.
266 */
267 void serializeAfter(InstQueue &inst_list, ThreadID tid);
268
269 /** Holds the information for each destination register rename. It holds
270 * the instruction's sequence number, the arch register, the old physical
271 * register for that arch. register, and the new physical register.
272 */
273 struct RenameHistory {
274 RenameHistory(InstSeqNum _instSeqNum, RegIndex _archReg,
275 PhysRegIndex _newPhysReg, PhysRegIndex _prevPhysReg)
276 : instSeqNum(_instSeqNum), archReg(_archReg),
277 newPhysReg(_newPhysReg), prevPhysReg(_prevPhysReg)
278 {
279 }
280
281 /** The sequence number of the instruction that renamed. */
282 InstSeqNum instSeqNum;
283 /** The architectural register index that was renamed. */
284 RegIndex archReg;
285 /** The new physical register that the arch. register is renamed to. */
286 PhysRegIndex newPhysReg;
287 /** The old physical register that the arch. register was renamed to. */
288 PhysRegIndex prevPhysReg;
289 };
290
291 /** A per-thread list of all destination register renames, used to either
292 * undo rename mappings or free old physical registers.
293 */
294 std::list<RenameHistory> historyBuffer[Impl::MaxThreads];
295
296 /** Pointer to CPU. */
297 O3CPU *cpu;
298
299 /** Pointer to main time buffer used for backwards communication. */
300 TimeBuffer<TimeStruct> *timeBuffer;
301
302 /** Wire to get IEW's output from backwards time buffer. */
303 typename TimeBuffer<TimeStruct>::wire fromIEW;
304
305 /** Wire to get commit's output from backwards time buffer. */
306 typename TimeBuffer<TimeStruct>::wire fromCommit;
307
308 /** Wire to write infromation heading to previous stages. */
309 typename TimeBuffer<TimeStruct>::wire toDecode;
310
311 /** Rename instruction queue. */
312 TimeBuffer<RenameStruct> *renameQueue;
313
314 /** Wire to write any information heading to IEW. */
315 typename TimeBuffer<RenameStruct>::wire toIEW;
316
317 /** Decode instruction queue interface. */
318 TimeBuffer<DecodeStruct> *decodeQueue;
319
320 /** Wire to get decode's output from decode queue. */
321 typename TimeBuffer<DecodeStruct>::wire fromDecode;
322
323 /** Queue of all instructions coming from decode this cycle. */
324 InstQueue insts[Impl::MaxThreads];
325
326 /** Skid buffer between rename and decode. */
327 InstQueue skidBuffer[Impl::MaxThreads];
328
329 /** Rename map interface. */
330 RenameMap *renameMap[Impl::MaxThreads];
331
332 /** Free list interface. */
333 FreeList *freeList;
334
335 /** Pointer to the list of active threads. */
336 std::list<ThreadID> *activeThreads;
337
338 /** Pointer to the scoreboard. */
339 Scoreboard *scoreboard;
340
341 /** Count of instructions in progress that have been sent off to the IQ
342 * and ROB, but are not yet included in their occupancy counts.
343 */
344 int instsInProgress[Impl::MaxThreads];
345
346 /** Variable that tracks if decode has written to the time buffer this
347 * cycle. Used to tell CPU if there is activity this cycle.
348 */
349 bool wroteToTimeBuffer;
350
351 /** Structures whose free entries impact the amount of instructions that
352 * can be renamed.
353 */
354 struct FreeEntries {
355 unsigned iqEntries;
356 unsigned lsqEntries;
357 unsigned robEntries;
358 };
359
360 /** Per-thread tracking of the number of free entries of back-end
361 * structures.
362 */
363 FreeEntries freeEntries[Impl::MaxThreads];
364
365 /** Records if the ROB is empty. In SMT mode the ROB may be dynamically
366 * partitioned between threads, so the ROB must tell rename when it is
367 * empty.
368 */
369 bool emptyROB[Impl::MaxThreads];
370
371 /** Source of possible stalls. */
372 struct Stalls {
373 bool iew;
374 bool commit;
375 };
376
377 /** Tracks which stages are telling decode to stall. */
378 Stalls stalls[Impl::MaxThreads];
379
380 /** The serialize instruction that rename has stalled on. */
381 DynInstPtr serializeInst[Impl::MaxThreads];
382
383 /** Records if rename needs to serialize on the next instruction for any
384 * thread.
385 */
386 bool serializeOnNextInst[Impl::MaxThreads];
387
388 /** Delay between iew and rename, in ticks. */
389 int iewToRenameDelay;
390
391 /** Delay between decode and rename, in ticks. */
392 int decodeToRenameDelay;
393
394 /** Delay between commit and rename, in ticks. */
395 unsigned commitToRenameDelay;
396
397 /** Rename width, in instructions. */
398 unsigned renameWidth;
399
400 /** Commit width, in instructions. Used so rename knows how many
401 * instructions might have freed registers in the previous cycle.
402 */
403 unsigned commitWidth;
404
405 /** The index of the instruction in the time buffer to IEW that rename is
406 * currently using.
407 */
408 unsigned toIEWIndex;
409
410 /** Whether or not rename needs to block this cycle. */
411 bool blockThisCycle;
412
413 /** Whether or not rename needs to resume a serialize instruction
414 * after squashing. */
415 bool resumeSerialize;
416
417 /** Whether or not rename needs to resume clearing out the skidbuffer
418 * after squashing. */
419 bool resumeUnblocking;
420
421 /** The number of threads active in rename. */
422 ThreadID numThreads;
423
424 /** The maximum skid buffer size. */
425 unsigned skidBufferMax;
426
427 PhysRegIndex maxPhysicalRegs;
428
429 /** Enum to record the source of a structure full stall. Can come from
430 * either ROB, IQ, LSQ, and it is priortized in that order.
431 */
432 enum FullSource {
433 ROB,
434 IQ,
435 LSQ,
436 NONE
437 };
438
439 /** Function used to increment the stat that corresponds to the source of
440 * the stall.
441 */
442 inline void incrFullStat(const FullSource &source);
443
444 /** Stat for total number of cycles spent squashing. */
445 Stats::Scalar renameSquashCycles;
446 /** Stat for total number of cycles spent idle. */
447 Stats::Scalar renameIdleCycles;
448 /** Stat for total number of cycles spent blocking. */
449 Stats::Scalar renameBlockCycles;
450 /** Stat for total number of cycles spent stalling for a serializing inst. */
451 Stats::Scalar renameSerializeStallCycles;
452 /** Stat for total number of cycles spent running normally. */
453 Stats::Scalar renameRunCycles;
454 /** Stat for total number of cycles spent unblocking. */
455 Stats::Scalar renameUnblockCycles;
456 /** Stat for total number of renamed instructions. */
457 Stats::Scalar renameRenamedInsts;
458 /** Stat for total number of squashed instructions that rename discards. */
459 Stats::Scalar renameSquashedInsts;
460 /** Stat for total number of times that the ROB starts a stall in rename. */
461 Stats::Scalar renameROBFullEvents;
462 /** Stat for total number of times that the IQ starts a stall in rename. */
463 Stats::Scalar renameIQFullEvents;
464 /** Stat for total number of times that the LSQ starts a stall in rename. */
465 Stats::Scalar renameLSQFullEvents;
466 /** Stat for total number of times that rename runs out of free registers
467 * to use to rename. */
468 Stats::Scalar renameFullRegistersEvents;
469 /** Stat for total number of renamed destination registers. */
470 Stats::Scalar renameRenamedOperands;
471 /** Stat for total number of source register rename lookups. */
472 Stats::Scalar renameRenameLookups;
| 1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_O3_RENAME_HH__
32#define __CPU_O3_RENAME_HH__
33
34#include <list>
35
36#include "base/statistics.hh"
37#include "cpu/timebuf.hh"
38#include "config/the_isa.hh"
39
40class DerivO3CPUParams;
41
42/**
43 * DefaultRename handles both single threaded and SMT rename. Its
44 * width is specified by the parameters; each cycle it tries to rename
45 * that many instructions. It holds onto the rename history of all
46 * instructions with destination registers, storing the
47 * arch. register, the new physical register, and the old physical
48 * register, to allow for undoing of mappings if squashing happens, or
49 * freeing up registers upon commit. Rename handles blocking if the
50 * ROB, IQ, or LSQ is going to be full. Rename also handles barriers,
51 * and does so by stalling on the instruction until the ROB is empty
52 * and there are no instructions in flight to the ROB.
53 */
54template<class Impl>
55class DefaultRename
56{
57 public:
58 // Typedefs from the Impl.
59 typedef typename Impl::CPUPol CPUPol;
60 typedef typename Impl::DynInstPtr DynInstPtr;
61 typedef typename Impl::O3CPU O3CPU;
62
63 // Typedefs from the CPUPol
64 typedef typename CPUPol::DecodeStruct DecodeStruct;
65 typedef typename CPUPol::RenameStruct RenameStruct;
66 typedef typename CPUPol::TimeStruct TimeStruct;
67 typedef typename CPUPol::FreeList FreeList;
68 typedef typename CPUPol::RenameMap RenameMap;
69 // These are used only for initialization.
70 typedef typename CPUPol::IEW IEW;
71 typedef typename CPUPol::Commit Commit;
72
73 // Typedefs from the ISA.
74 typedef TheISA::RegIndex RegIndex;
75
76 // A list is used to queue the instructions. Barrier insts must
77 // be added to the front of the list, which is the only reason for
78 // using a list instead of a queue. (Most other stages use a
79 // queue)
80 typedef std::list<DynInstPtr> InstQueue;
81 typedef typename std::list<DynInstPtr>::iterator ListIt;
82
83 public:
84 /** Overall rename status. Used to determine if the CPU can
85 * deschedule itself due to a lack of activity.
86 */
87 enum RenameStatus {
88 Active,
89 Inactive
90 };
91
92 /** Individual thread status. */
93 enum ThreadStatus {
94 Running,
95 Idle,
96 StartSquash,
97 Squashing,
98 Blocked,
99 Unblocking,
100 SerializeStall
101 };
102
103 private:
104 /** Rename status. */
105 RenameStatus _status;
106
107 /** Per-thread status. */
108 ThreadStatus renameStatus[Impl::MaxThreads];
109
110 public:
111 /** DefaultRename constructor. */
112 DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params);
113
114 /** Returns the name of rename. */
115 std::string name() const;
116
117 /** Registers statistics. */
118 void regStats();
119
120 /** Sets the main backwards communication time buffer pointer. */
121 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
122
123 /** Sets pointer to time buffer used to communicate to the next stage. */
124 void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
125
126 /** Sets pointer to time buffer coming from decode. */
127 void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr);
128
129 /** Sets pointer to IEW stage. Used only for initialization. */
130 void setIEWStage(IEW *iew_stage)
131 { iew_ptr = iew_stage; }
132
133 /** Sets pointer to commit stage. Used only for initialization. */
134 void setCommitStage(Commit *commit_stage)
135 { commit_ptr = commit_stage; }
136
137 private:
138 /** Pointer to IEW stage. Used only for initialization. */
139 IEW *iew_ptr;
140
141 /** Pointer to commit stage. Used only for initialization. */
142 Commit *commit_ptr;
143
144 public:
145 /** Initializes variables for the stage. */
146 void initStage();
147
148 /** Sets pointer to list of active threads. */
149 void setActiveThreads(std::list<ThreadID> *at_ptr);
150
151 /** Sets pointer to rename maps (per-thread structures). */
152 void setRenameMap(RenameMap rm_ptr[Impl::MaxThreads]);
153
154 /** Sets pointer to the free list. */
155 void setFreeList(FreeList *fl_ptr);
156
157 /** Sets pointer to the scoreboard. */
158 void setScoreboard(Scoreboard *_scoreboard);
159
160 /** Drains the rename stage. */
161 bool drain();
162
163 /** Resumes execution after a drain. */
164 void resume() { }
165
166 /** Switches out the rename stage. */
167 void switchOut();
168
169 /** Takes over from another CPU's thread. */
170 void takeOverFrom();
171
172 /** Squashes all instructions in a thread. */
173 void squash(const InstSeqNum &squash_seq_num, ThreadID tid);
174
175 /** Ticks rename, which processes all input signals and attempts to rename
176 * as many instructions as possible.
177 */
178 void tick();
179
180 /** Debugging function used to dump history buffer of renamings. */
181 void dumpHistory();
182
183 private:
184 /** Determines what to do based on rename's current status.
185 * @param status_change rename() sets this variable if there was a status
186 * change (ie switching from blocking to unblocking).
187 * @param tid Thread id to rename instructions from.
188 */
189 void rename(bool &status_change, ThreadID tid);
190
191 /** Renames instructions for the given thread. Also handles serializing
192 * instructions.
193 */
194 void renameInsts(ThreadID tid);
195
196 /** Inserts unused instructions from a given thread into the skid buffer,
197 * to be renamed once rename unblocks.
198 */
199 void skidInsert(ThreadID tid);
200
201 /** Separates instructions from decode into individual lists of instructions
202 * sorted by thread.
203 */
204 void sortInsts();
205
206 /** Returns if all of the skid buffers are empty. */
207 bool skidsEmpty();
208
209 /** Updates overall rename status based on all of the threads' statuses. */
210 void updateStatus();
211
212 /** Switches rename to blocking, and signals back that rename has become
213 * blocked.
214 * @return Returns true if there is a status change.
215 */
216 bool block(ThreadID tid);
217
218 /** Switches rename to unblocking if the skid buffer is empty, and signals
219 * back that rename has unblocked.
220 * @return Returns true if there is a status change.
221 */
222 bool unblock(ThreadID tid);
223
224 /** Executes actual squash, removing squashed instructions. */
225 void doSquash(const InstSeqNum &squash_seq_num, ThreadID tid);
226
227 /** Removes a committed instruction's rename history. */
228 void removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid);
229
230 /** Renames the source registers of an instruction. */
231 inline void renameSrcRegs(DynInstPtr &inst, ThreadID tid);
232
233 /** Renames the destination registers of an instruction. */
234 inline void renameDestRegs(DynInstPtr &inst, ThreadID tid);
235
236 /** Calculates the number of free ROB entries for a specific thread. */
237 inline int calcFreeROBEntries(ThreadID tid);
238
239 /** Calculates the number of free IQ entries for a specific thread. */
240 inline int calcFreeIQEntries(ThreadID tid);
241
242 /** Calculates the number of free LSQ entries for a specific thread. */
243 inline int calcFreeLSQEntries(ThreadID tid);
244
245 /** Returns the number of valid instructions coming from decode. */
246 unsigned validInsts();
247
248 /** Reads signals telling rename to block/unblock. */
249 void readStallSignals(ThreadID tid);
250
251 /** Checks if any stages are telling rename to block. */
252 bool checkStall(ThreadID tid);
253
254 /** Gets the number of free entries for a specific thread. */
255 void readFreeEntries(ThreadID tid);
256
257 /** Checks the signals and updates the status. */
258 bool checkSignalsAndUpdate(ThreadID tid);
259
260 /** Either serializes on the next instruction available in the InstQueue,
261 * or records that it must serialize on the next instruction to enter
262 * rename.
263 * @param inst_list The list of younger, unprocessed instructions for the
264 * thread that has the serializeAfter instruction.
265 * @param tid The thread id.
266 */
267 void serializeAfter(InstQueue &inst_list, ThreadID tid);
268
269 /** Holds the information for each destination register rename. It holds
270 * the instruction's sequence number, the arch register, the old physical
271 * register for that arch. register, and the new physical register.
272 */
273 struct RenameHistory {
274 RenameHistory(InstSeqNum _instSeqNum, RegIndex _archReg,
275 PhysRegIndex _newPhysReg, PhysRegIndex _prevPhysReg)
276 : instSeqNum(_instSeqNum), archReg(_archReg),
277 newPhysReg(_newPhysReg), prevPhysReg(_prevPhysReg)
278 {
279 }
280
281 /** The sequence number of the instruction that renamed. */
282 InstSeqNum instSeqNum;
283 /** The architectural register index that was renamed. */
284 RegIndex archReg;
285 /** The new physical register that the arch. register is renamed to. */
286 PhysRegIndex newPhysReg;
287 /** The old physical register that the arch. register was renamed to. */
288 PhysRegIndex prevPhysReg;
289 };
290
291 /** A per-thread list of all destination register renames, used to either
292 * undo rename mappings or free old physical registers.
293 */
294 std::list<RenameHistory> historyBuffer[Impl::MaxThreads];
295
296 /** Pointer to CPU. */
297 O3CPU *cpu;
298
299 /** Pointer to main time buffer used for backwards communication. */
300 TimeBuffer<TimeStruct> *timeBuffer;
301
302 /** Wire to get IEW's output from backwards time buffer. */
303 typename TimeBuffer<TimeStruct>::wire fromIEW;
304
305 /** Wire to get commit's output from backwards time buffer. */
306 typename TimeBuffer<TimeStruct>::wire fromCommit;
307
308 /** Wire to write infromation heading to previous stages. */
309 typename TimeBuffer<TimeStruct>::wire toDecode;
310
311 /** Rename instruction queue. */
312 TimeBuffer<RenameStruct> *renameQueue;
313
314 /** Wire to write any information heading to IEW. */
315 typename TimeBuffer<RenameStruct>::wire toIEW;
316
317 /** Decode instruction queue interface. */
318 TimeBuffer<DecodeStruct> *decodeQueue;
319
320 /** Wire to get decode's output from decode queue. */
321 typename TimeBuffer<DecodeStruct>::wire fromDecode;
322
323 /** Queue of all instructions coming from decode this cycle. */
324 InstQueue insts[Impl::MaxThreads];
325
326 /** Skid buffer between rename and decode. */
327 InstQueue skidBuffer[Impl::MaxThreads];
328
329 /** Rename map interface. */
330 RenameMap *renameMap[Impl::MaxThreads];
331
332 /** Free list interface. */
333 FreeList *freeList;
334
335 /** Pointer to the list of active threads. */
336 std::list<ThreadID> *activeThreads;
337
338 /** Pointer to the scoreboard. */
339 Scoreboard *scoreboard;
340
341 /** Count of instructions in progress that have been sent off to the IQ
342 * and ROB, but are not yet included in their occupancy counts.
343 */
344 int instsInProgress[Impl::MaxThreads];
345
346 /** Variable that tracks if decode has written to the time buffer this
347 * cycle. Used to tell CPU if there is activity this cycle.
348 */
349 bool wroteToTimeBuffer;
350
351 /** Structures whose free entries impact the amount of instructions that
352 * can be renamed.
353 */
354 struct FreeEntries {
355 unsigned iqEntries;
356 unsigned lsqEntries;
357 unsigned robEntries;
358 };
359
360 /** Per-thread tracking of the number of free entries of back-end
361 * structures.
362 */
363 FreeEntries freeEntries[Impl::MaxThreads];
364
365 /** Records if the ROB is empty. In SMT mode the ROB may be dynamically
366 * partitioned between threads, so the ROB must tell rename when it is
367 * empty.
368 */
369 bool emptyROB[Impl::MaxThreads];
370
371 /** Source of possible stalls. */
372 struct Stalls {
373 bool iew;
374 bool commit;
375 };
376
377 /** Tracks which stages are telling decode to stall. */
378 Stalls stalls[Impl::MaxThreads];
379
380 /** The serialize instruction that rename has stalled on. */
381 DynInstPtr serializeInst[Impl::MaxThreads];
382
383 /** Records if rename needs to serialize on the next instruction for any
384 * thread.
385 */
386 bool serializeOnNextInst[Impl::MaxThreads];
387
388 /** Delay between iew and rename, in ticks. */
389 int iewToRenameDelay;
390
391 /** Delay between decode and rename, in ticks. */
392 int decodeToRenameDelay;
393
394 /** Delay between commit and rename, in ticks. */
395 unsigned commitToRenameDelay;
396
397 /** Rename width, in instructions. */
398 unsigned renameWidth;
399
400 /** Commit width, in instructions. Used so rename knows how many
401 * instructions might have freed registers in the previous cycle.
402 */
403 unsigned commitWidth;
404
405 /** The index of the instruction in the time buffer to IEW that rename is
406 * currently using.
407 */
408 unsigned toIEWIndex;
409
410 /** Whether or not rename needs to block this cycle. */
411 bool blockThisCycle;
412
413 /** Whether or not rename needs to resume a serialize instruction
414 * after squashing. */
415 bool resumeSerialize;
416
417 /** Whether or not rename needs to resume clearing out the skidbuffer
418 * after squashing. */
419 bool resumeUnblocking;
420
421 /** The number of threads active in rename. */
422 ThreadID numThreads;
423
424 /** The maximum skid buffer size. */
425 unsigned skidBufferMax;
426
427 PhysRegIndex maxPhysicalRegs;
428
429 /** Enum to record the source of a structure full stall. Can come from
430 * either ROB, IQ, LSQ, and it is priortized in that order.
431 */
432 enum FullSource {
433 ROB,
434 IQ,
435 LSQ,
436 NONE
437 };
438
439 /** Function used to increment the stat that corresponds to the source of
440 * the stall.
441 */
442 inline void incrFullStat(const FullSource &source);
443
444 /** Stat for total number of cycles spent squashing. */
445 Stats::Scalar renameSquashCycles;
446 /** Stat for total number of cycles spent idle. */
447 Stats::Scalar renameIdleCycles;
448 /** Stat for total number of cycles spent blocking. */
449 Stats::Scalar renameBlockCycles;
450 /** Stat for total number of cycles spent stalling for a serializing inst. */
451 Stats::Scalar renameSerializeStallCycles;
452 /** Stat for total number of cycles spent running normally. */
453 Stats::Scalar renameRunCycles;
454 /** Stat for total number of cycles spent unblocking. */
455 Stats::Scalar renameUnblockCycles;
456 /** Stat for total number of renamed instructions. */
457 Stats::Scalar renameRenamedInsts;
458 /** Stat for total number of squashed instructions that rename discards. */
459 Stats::Scalar renameSquashedInsts;
460 /** Stat for total number of times that the ROB starts a stall in rename. */
461 Stats::Scalar renameROBFullEvents;
462 /** Stat for total number of times that the IQ starts a stall in rename. */
463 Stats::Scalar renameIQFullEvents;
464 /** Stat for total number of times that the LSQ starts a stall in rename. */
465 Stats::Scalar renameLSQFullEvents;
466 /** Stat for total number of times that rename runs out of free registers
467 * to use to rename. */
468 Stats::Scalar renameFullRegistersEvents;
469 /** Stat for total number of renamed destination registers. */
470 Stats::Scalar renameRenamedOperands;
471 /** Stat for total number of source register rename lookups. */
472 Stats::Scalar renameRenameLookups;
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