1/*
| 1/*
|
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
| 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
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3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30
| 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30
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31// Todo: 32// Fix up trap and barrier handling. 33// May want to have different statuses to differentiate the different stall 34// conditions.
| 31#ifndef __CPU_O3_RENAME_HH__ 32#define __CPU_O3_RENAME_HH__
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35
| 33
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36#ifndef __CPU_O3_CPU_SIMPLE_RENAME_HH__ 37#define __CPU_O3_CPU_SIMPLE_RENAME_HH__ 38
| |
39#include <list> 40 41#include "base/statistics.hh" 42#include "base/timebuf.hh" 43
| 34#include <list> 35 36#include "base/statistics.hh" 37#include "base/timebuf.hh" 38
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44// Will need rename maps for both the int reg file and fp reg file. 45// Or change rename map class to handle both. (RegFile handles both.)
| 39/** 40 * DefaultRename handles both single threaded and SMT rename. Its 41 * width is specified by the parameters; each cycle it tries to rename 42 * that many instructions. It holds onto the rename history of all 43 * instructions with destination registers, storing the 44 * arch. register, the new physical register, and the old physical 45 * register, to allow for undoing of mappings if squashing happens, or 46 * freeing up registers upon commit. Rename handles blocking if the 47 * ROB, IQ, or LSQ is going to be full. Rename also handles barriers, 48 * and does so by stalling on the instruction until the ROB is empty 49 * and there are no instructions in flight to the ROB. 50 */
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46template<class Impl>
| 51template<class Impl>
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47class SimpleRename
| 52class DefaultRename
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48{ 49 public: 50 // Typedefs from the Impl. 51 typedef typename Impl::CPUPol CPUPol; 52 typedef typename Impl::DynInstPtr DynInstPtr; 53 typedef typename Impl::FullCPU FullCPU; 54 typedef typename Impl::Params Params; 55
| 53{ 54 public: 55 // Typedefs from the Impl. 56 typedef typename Impl::CPUPol CPUPol; 57 typedef typename Impl::DynInstPtr DynInstPtr; 58 typedef typename Impl::FullCPU FullCPU; 59 typedef typename Impl::Params Params; 60
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56 typedef typename CPUPol::FetchStruct FetchStruct;
| 61 // Typedefs from the CPUPol
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57 typedef typename CPUPol::DecodeStruct DecodeStruct; 58 typedef typename CPUPol::RenameStruct RenameStruct; 59 typedef typename CPUPol::TimeStruct TimeStruct;
| 62 typedef typename CPUPol::DecodeStruct DecodeStruct; 63 typedef typename CPUPol::RenameStruct RenameStruct; 64 typedef typename CPUPol::TimeStruct TimeStruct;
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60 61 // Typedefs from the CPUPol
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62 typedef typename CPUPol::FreeList FreeList; 63 typedef typename CPUPol::RenameMap RenameMap;
| 65 typedef typename CPUPol::FreeList FreeList; 66 typedef typename CPUPol::RenameMap RenameMap;
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| 67 // These are used only for initialization. 68 typedef typename CPUPol::IEW IEW; 69 typedef typename CPUPol::Commit Commit;
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64 65 // Typedefs from the ISA. 66 typedef TheISA::RegIndex RegIndex; 67
| 70 71 // Typedefs from the ISA. 72 typedef TheISA::RegIndex RegIndex; 73
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| 74 // A list is used to queue the instructions. Barrier insts must 75 // be added to the front of the list, which is the only reason for 76 // using a list instead of a queue. (Most other stages use a 77 // queue) 78 typedef std::list<DynInstPtr> InstQueue; 79
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68 public:
| 80 public:
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69 // Rename will block if ROB becomes full or issue queue becomes full, 70 // or there are no free registers to rename to. 71 // Only case where rename squashes is if IEW squashes. 72 enum Status {
| 81 /** Overall rename status. Used to determine if the CPU can 82 * deschedule itself due to a lack of activity. 83 */ 84 enum RenameStatus { 85 Active, 86 Inactive 87 }; 88 89 /** Individual thread status. */ 90 enum ThreadStatus {
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73 Running, 74 Idle,
| 91 Running, 92 Idle,
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| 93 StartSquash,
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75 Squashing, 76 Blocked, 77 Unblocking,
| 94 Squashing, 95 Blocked, 96 Unblocking,
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78 BarrierStall
| 97 SerializeStall
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79 }; 80 81 private:
| 98 }; 99 100 private:
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82 Status _status;
| 101 /** Rename status. */ 102 RenameStatus _status;
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83
| 103
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| 104 /** Per-thread status. */ 105 ThreadStatus renameStatus[Impl::MaxThreads]; 106
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84 public:
| 107 public:
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85 SimpleRename(Params ¶ms);
| 108 /** DefaultRename constructor. */ 109 DefaultRename(Params *params);
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86
| 110
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| 111 /** Returns the name of rename. */ 112 std::string name() const; 113 114 /** Registers statistics. */
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87 void regStats(); 88
| 115 void regStats(); 116
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| 117 /** Sets CPU pointer. */
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89 void setCPU(FullCPU *cpu_ptr); 90
| 118 void setCPU(FullCPU *cpu_ptr); 119
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| 120 /** Sets the main backwards communication time buffer pointer. */
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91 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 92
| 121 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 122
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| 123 /** Sets pointer to time buffer used to communicate to the next stage. */
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93 void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 94
| 124 void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 125
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| 126 /** Sets pointer to time buffer coming from decode. */
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95 void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr); 96
| 127 void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr); 128
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97 void setRenameMap(RenameMap *rm_ptr);
| 129 /** Sets pointer to IEW stage. Used only for initialization. */ 130 void setIEWStage(IEW *iew_stage) 131 { iew_ptr = iew_stage; }
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98
| 132
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| 133 /** Sets pointer to commit stage. Used only for initialization. */ 134 void setCommitStage(Commit *commit_stage) 135 { commit_ptr = commit_stage; } 136 137 private: 138 /** Pointer to IEW stage. Used only for initialization. */ 139 IEW *iew_ptr; 140 141 /** Pointer to commit stage. Used only for initialization. */ 142 Commit *commit_ptr; 143 144 public: 145 /** Initializes variables for the stage. */ 146 void initStage(); 147 148 /** Sets pointer to list of active threads. */ 149 void setActiveThreads(std::list<unsigned> *at_ptr); 150 151 /** Sets pointer to rename maps (per-thread structures). */ 152 void setRenameMap(RenameMap rm_ptr[Impl::MaxThreads]); 153 154 /** Sets pointer to the free list. */
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99 void setFreeList(FreeList *fl_ptr); 100
| 155 void setFreeList(FreeList *fl_ptr); 156
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101 void dumpHistory();
| 157 /** Sets pointer to the scoreboard. */ 158 void setScoreboard(Scoreboard *_scoreboard);
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102
| 159
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103 void tick();
| 160 void switchOut();
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104
| 161
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105 void rename();
| 162 void doSwitchOut();
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106
| 163
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107 void squash();
| 164 void takeOverFrom();
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108
| 165
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| 166 /** Squashes all instructions in a thread. */ 167 void squash(unsigned tid); 168 169 /** Ticks rename, which processes all input signals and attempts to rename 170 * as many instructions as possible. 171 */ 172 void tick(); 173 174 /** Debugging function used to dump history buffer of renamings. */ 175 void dumpHistory(); 176
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109 private:
| 177 private:
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110 void block();
| 178 /** Determines what to do based on rename's current status. 179 * @param status_change rename() sets this variable if there was a status 180 * change (ie switching from blocking to unblocking). 181 * @param tid Thread id to rename instructions from. 182 */ 183 void rename(bool &status_change, unsigned tid);
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111
| 184
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112 inline void unblock();
| 185 /** Renames instructions for the given thread. Also handles serializing 186 * instructions. 187 */ 188 void renameInsts(unsigned tid);
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113
| 189
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114 void doSquash();
| 190 /** Inserts unused instructions from a given thread into the skid buffer, 191 * to be renamed once rename unblocks. 192 */ 193 void skidInsert(unsigned tid);
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115
| 194
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116 void removeFromHistory(InstSeqNum inst_seq_num);
| 195 /** Separates instructions from decode into individual lists of instructions 196 * sorted by thread. 197 */ 198 void sortInsts();
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117
| 199
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118 inline void renameSrcRegs(DynInstPtr &inst);
| 200 /** Returns if all of the skid buffers are empty. */ 201 bool skidsEmpty();
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119
| 202
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120 inline void renameDestRegs(DynInstPtr &inst);
| 203 /** Updates overall rename status based on all of the threads' statuses. */ 204 void updateStatus();
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121
| 205
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122 inline int calcFreeROBEntries();
| 206 /** Switches rename to blocking, and signals back that rename has become 207 * blocked. 208 * @return Returns true if there is a status change. 209 */ 210 bool block(unsigned tid);
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123
| 211
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124 inline int calcFreeIQEntries();
| 212 /** Switches rename to unblocking if the skid buffer is empty, and signals 213 * back that rename has unblocked. 214 * @return Returns true if there is a status change. 215 */ 216 bool unblock(unsigned tid);
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125
| 217
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126 /** Holds the previous information for each rename. 127 * Note that often times the inst may have been deleted, so only access 128 * the pointer for the address and do not dereference it.
| 218 /** Executes actual squash, removing squashed instructions. */ 219 void doSquash(unsigned tid); 220 221 /** Removes a committed instruction's rename history. */ 222 void removeFromHistory(InstSeqNum inst_seq_num, unsigned tid); 223 224 /** Renames the source registers of an instruction. */ 225 inline void renameSrcRegs(DynInstPtr &inst, unsigned tid); 226 227 /** Renames the destination registers of an instruction. */ 228 inline void renameDestRegs(DynInstPtr &inst, unsigned tid); 229 230 /** Calculates the number of free ROB entries for a specific thread. */ 231 inline int calcFreeROBEntries(unsigned tid); 232 233 /** Calculates the number of free IQ entries for a specific thread. */ 234 inline int calcFreeIQEntries(unsigned tid); 235 236 /** Calculates the number of free LSQ entries for a specific thread. */ 237 inline int calcFreeLSQEntries(unsigned tid); 238 239 /** Returns the number of valid instructions coming from decode. */ 240 unsigned validInsts(); 241 242 /** Reads signals telling rename to block/unblock. */ 243 void readStallSignals(unsigned tid); 244 245 /** Checks if any stages are telling rename to block. */ 246 bool checkStall(unsigned tid); 247 248 void readFreeEntries(unsigned tid); 249 250 bool checkSignalsAndUpdate(unsigned tid); 251 252 /** Either serializes on the next instruction available in the InstQueue, 253 * or records that it must serialize on the next instruction to enter 254 * rename. 255 * @param inst_list The list of younger, unprocessed instructions for the 256 * thread that has the serializeAfter instruction. 257 * @param tid The thread id.
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129 */
| 258 */
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| 259 void serializeAfter(InstQueue &inst_list, unsigned tid); 260 261 /** Holds the information for each destination register rename. It holds 262 * the instruction's sequence number, the arch register, the old physical 263 * register for that arch. register, and the new physical register. 264 */
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130 struct RenameHistory { 131 RenameHistory(InstSeqNum _instSeqNum, RegIndex _archReg, 132 PhysRegIndex _newPhysReg, PhysRegIndex _prevPhysReg) 133 : instSeqNum(_instSeqNum), archReg(_archReg),
| 265 struct RenameHistory { 266 RenameHistory(InstSeqNum _instSeqNum, RegIndex _archReg, 267 PhysRegIndex _newPhysReg, PhysRegIndex _prevPhysReg) 268 : instSeqNum(_instSeqNum), archReg(_archReg),
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134 newPhysReg(_newPhysReg), prevPhysReg(_prevPhysReg), 135 placeHolder(false)
| 269 newPhysReg(_newPhysReg), prevPhysReg(_prevPhysReg)
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136 { 137 } 138
| 270 { 271 } 272
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139 /** Constructor used specifically for cases where a place holder 140 * rename history entry is being made. 141 */ 142 RenameHistory(InstSeqNum _instSeqNum) 143 : instSeqNum(_instSeqNum), archReg(0), newPhysReg(0), 144 prevPhysReg(0), placeHolder(true) 145 { 146 } 147
| 273 /** The sequence number of the instruction that renamed. */
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148 InstSeqNum instSeqNum;
| 274 InstSeqNum instSeqNum;
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| 275 /** The architectural register index that was renamed. */
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149 RegIndex archReg;
| 276 RegIndex archReg;
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| 277 /** The new physical register that the arch. register is renamed to. */
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150 PhysRegIndex newPhysReg;
| 278 PhysRegIndex newPhysReg;
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| 279 /** The old physical register that the arch. register was renamed to. */
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151 PhysRegIndex prevPhysReg;
| 280 PhysRegIndex prevPhysReg;
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152 bool placeHolder;
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153 }; 154
| 281 }; 282
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155 std::list<RenameHistory> historyBuffer;
| 283 /** A per-thread list of all destination register renames, used to either 284 * undo rename mappings or free old physical registers. 285 */ 286 std::list<RenameHistory> historyBuffer[Impl::MaxThreads];
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156
| 287
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157 /** CPU interface. */
| 288 /** Pointer to CPU. */
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158 FullCPU *cpu; 159
| 289 FullCPU *cpu; 290
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160 // Interfaces to objects outside of rename. 161 /** Time buffer interface. */
| 291 /** Pointer to main time buffer used for backwards communication. */
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162 TimeBuffer<TimeStruct> *timeBuffer; 163 164 /** Wire to get IEW's output from backwards time buffer. */ 165 typename TimeBuffer<TimeStruct>::wire fromIEW; 166 167 /** Wire to get commit's output from backwards time buffer. */ 168 typename TimeBuffer<TimeStruct>::wire fromCommit; 169 170 /** Wire to write infromation heading to previous stages. */
| 292 TimeBuffer<TimeStruct> *timeBuffer; 293 294 /** Wire to get IEW's output from backwards time buffer. */ 295 typename TimeBuffer<TimeStruct>::wire fromIEW; 296 297 /** Wire to get commit's output from backwards time buffer. */ 298 typename TimeBuffer<TimeStruct>::wire fromCommit; 299 300 /** Wire to write infromation heading to previous stages. */
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171 // Might not be the best name as not only decode will read it.
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172 typename TimeBuffer<TimeStruct>::wire toDecode; 173 174 /** Rename instruction queue. */ 175 TimeBuffer<RenameStruct> *renameQueue; 176 177 /** Wire to write any information heading to IEW. */ 178 typename TimeBuffer<RenameStruct>::wire toIEW; 179 180 /** Decode instruction queue interface. */ 181 TimeBuffer<DecodeStruct> *decodeQueue; 182 183 /** Wire to get decode's output from decode queue. */ 184 typename TimeBuffer<DecodeStruct>::wire fromDecode; 185
| 301 typename TimeBuffer<TimeStruct>::wire toDecode; 302 303 /** Rename instruction queue. */ 304 TimeBuffer<RenameStruct> *renameQueue; 305 306 /** Wire to write any information heading to IEW. */ 307 typename TimeBuffer<RenameStruct>::wire toIEW; 308 309 /** Decode instruction queue interface. */ 310 TimeBuffer<DecodeStruct> *decodeQueue; 311 312 /** Wire to get decode's output from decode queue. */ 313 typename TimeBuffer<DecodeStruct>::wire fromDecode; 314
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| 315 /** Queue of all instructions coming from decode this cycle. */ 316 InstQueue insts[Impl::MaxThreads]; 317
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186 /** Skid buffer between rename and decode. */
| 318 /** Skid buffer between rename and decode. */
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187 std::queue<DecodeStruct> skidBuffer;
| 319 InstQueue skidBuffer[Impl::MaxThreads];
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188 189 /** Rename map interface. */
| 320 321 /** Rename map interface. */
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190 SimpleRenameMap *renameMap;
| 322 RenameMap *renameMap[Impl::MaxThreads];
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191 192 /** Free list interface. */ 193 FreeList *freeList; 194
| 323 324 /** Free list interface. */ 325 FreeList *freeList; 326
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| 327 /** Pointer to the list of active threads. */ 328 std::list<unsigned> *activeThreads; 329 330 /** Pointer to the scoreboard. */ 331 Scoreboard *scoreboard; 332 333 /** Count of instructions in progress that have been sent off to the IQ 334 * and ROB, but are not yet included in their occupancy counts. 335 */ 336 int instsInProgress[Impl::MaxThreads]; 337 338 /** Variable that tracks if decode has written to the time buffer this 339 * cycle. Used to tell CPU if there is activity this cycle. 340 */ 341 bool wroteToTimeBuffer; 342 343 /** Structures whose free entries impact the amount of instructions that 344 * can be renamed. 345 */ 346 struct FreeEntries { 347 unsigned iqEntries; 348 unsigned lsqEntries; 349 unsigned robEntries; 350 }; 351 352 /** Per-thread tracking of the number of free entries of back-end 353 * structures. 354 */ 355 FreeEntries freeEntries[Impl::MaxThreads]; 356 357 /** Records if the ROB is empty. In SMT mode the ROB may be dynamically 358 * partitioned between threads, so the ROB must tell rename when it is 359 * empty. 360 */ 361 bool emptyROB[Impl::MaxThreads]; 362 363 /** Source of possible stalls. */ 364 struct Stalls { 365 bool iew; 366 bool commit; 367 }; 368 369 /** Tracks which stages are telling decode to stall. */ 370 Stalls stalls[Impl::MaxThreads]; 371 372 /** The serialize instruction that rename has stalled on. */ 373 DynInstPtr serializeInst[Impl::MaxThreads]; 374 375 /** Records if rename needs to serialize on the next instruction for any 376 * thread. 377 */ 378 bool serializeOnNextInst[Impl::MaxThreads]; 379
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195 /** Delay between iew and rename, in ticks. */ 196 int iewToRenameDelay; 197 198 /** Delay between decode and rename, in ticks. */ 199 int decodeToRenameDelay; 200 201 /** Delay between commit and rename, in ticks. */ 202 unsigned commitToRenameDelay; 203 204 /** Rename width, in instructions. */ 205 unsigned renameWidth; 206 207 /** Commit width, in instructions. Used so rename knows how many 208 * instructions might have freed registers in the previous cycle. 209 */ 210 unsigned commitWidth; 211
| 380 /** Delay between iew and rename, in ticks. */ 381 int iewToRenameDelay; 382 383 /** Delay between decode and rename, in ticks. */ 384 int decodeToRenameDelay; 385 386 /** Delay between commit and rename, in ticks. */ 387 unsigned commitToRenameDelay; 388 389 /** Rename width, in instructions. */ 390 unsigned renameWidth; 391 392 /** Commit width, in instructions. Used so rename knows how many 393 * instructions might have freed registers in the previous cycle. 394 */ 395 unsigned commitWidth; 396
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212 /** The instruction that rename is currently on. It needs to have 213 * persistent state so that when a stall occurs in the middle of a 214 * group of instructions, it can restart at the proper instruction.
| 397 /** The index of the instruction in the time buffer to IEW that rename is 398 * currently using.
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215 */
| 399 */
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216 unsigned numInst;
| 400 unsigned toIEWIndex;
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217
| 401
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| 402 /** Whether or not rename needs to block this cycle. */ 403 bool blockThisCycle; 404 405 /** The number of threads active in rename. */ 406 unsigned numThreads; 407 408 /** The maximum skid buffer size. */ 409 unsigned skidBufferMax; 410 411 /** Enum to record the source of a structure full stall. Can come from 412 * either ROB, IQ, LSQ, and it is priortized in that order. 413 */ 414 enum FullSource { 415 ROB, 416 IQ, 417 LSQ, 418 NONE 419 }; 420 421 /** Function used to increment the stat that corresponds to the source of 422 * the stall. 423 */ 424 inline void incrFullStat(const FullSource &source); 425 426 /** Stat for total number of cycles spent squashing. */
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218 Stats::Scalar<> renameSquashCycles;
| 427 Stats::Scalar<> renameSquashCycles;
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| 428 /** Stat for total number of cycles spent idle. */
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219 Stats::Scalar<> renameIdleCycles;
| 429 Stats::Scalar<> renameIdleCycles;
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| 430 /** Stat for total number of cycles spent blocking. */
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220 Stats::Scalar<> renameBlockCycles;
| 431 Stats::Scalar<> renameBlockCycles;
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| 432 /** Stat for total number of cycles spent stalling for a serializing inst. */ 433 Stats::Scalar<> renameSerializeStallCycles; 434 /** Stat for total number of cycles spent running normally. */ 435 Stats::Scalar<> renameRunCycles; 436 /** Stat for total number of cycles spent unblocking. */
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221 Stats::Scalar<> renameUnblockCycles;
| 437 Stats::Scalar<> renameUnblockCycles;
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| 438 /** Stat for total number of renamed instructions. */
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222 Stats::Scalar<> renameRenamedInsts;
| 439 Stats::Scalar<> renameRenamedInsts;
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| 440 /** Stat for total number of squashed instructions that rename discards. */
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223 Stats::Scalar<> renameSquashedInsts;
| 441 Stats::Scalar<> renameSquashedInsts;
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| 442 /** Stat for total number of times that the ROB starts a stall in rename. */
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224 Stats::Scalar<> renameROBFullEvents;
| 443 Stats::Scalar<> renameROBFullEvents;
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| 444 /** Stat for total number of times that the IQ starts a stall in rename. */
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225 Stats::Scalar<> renameIQFullEvents;
| 445 Stats::Scalar<> renameIQFullEvents;
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| 446 /** Stat for total number of times that the LSQ starts a stall in rename. */ 447 Stats::Scalar<> renameLSQFullEvents; 448 /** Stat for total number of times that rename runs out of free registers 449 * to use to rename. */
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226 Stats::Scalar<> renameFullRegistersEvents;
| 450 Stats::Scalar<> renameFullRegistersEvents;
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| 451 /** Stat for total number of renamed destination registers. */
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227 Stats::Scalar<> renameRenamedOperands;
| 452 Stats::Scalar<> renameRenamedOperands;
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| 453 /** Stat for total number of source register rename lookups. */
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228 Stats::Scalar<> renameRenameLookups;
| 454 Stats::Scalar<> renameRenameLookups;
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229 Stats::Scalar<> renameHBPlaceHolders;
| 455 /** Stat for total number of committed renaming mappings. */
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230 Stats::Scalar<> renameCommittedMaps;
| 456 Stats::Scalar<> renameCommittedMaps;
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| 457 /** Stat for total number of mappings that were undone due to a squash. */
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231 Stats::Scalar<> renameUndoneMaps;
| 458 Stats::Scalar<> renameUndoneMaps;
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232 Stats::Scalar<> renameValidUndoneMaps;
| 459 Stats::Scalar<> renamedSerializing; 460 Stats::Scalar<> renamedTempSerializing; 461 Stats::Scalar<> renameSkidInsts;
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233}; 234
| 462}; 463
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235#endif // __CPU_O3_CPU_SIMPLE_RENAME_HH__
| 464#endif // __CPU_O3_RENAME_HH__
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| |