1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * Copyright (c) 2013 Advanced Micro Devices, Inc.
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 */
43
44#ifndef __CPU_O3_RENAME_HH__
45#define __CPU_O3_RENAME_HH__
46
47#include <list>
48#include <utility>
49
50#include "base/statistics.hh"
51#include "config/the_isa.hh"
52#include "cpu/timebuf.hh"
53#include "sim/probe/probe.hh"
54
55struct DerivO3CPUParams;
56
57/**
58 * DefaultRename handles both single threaded and SMT rename. Its
59 * width is specified by the parameters; each cycle it tries to rename
60 * that many instructions. It holds onto the rename history of all
61 * instructions with destination registers, storing the
62 * arch. register, the new physical register, and the old physical
63 * register, to allow for undoing of mappings if squashing happens, or
64 * freeing up registers upon commit. Rename handles blocking if the
65 * ROB, IQ, or LSQ is going to be full. Rename also handles barriers,
66 * and does so by stalling on the instruction until the ROB is empty
67 * and there are no instructions in flight to the ROB.
68 */
69template<class Impl>
70class DefaultRename
71{
72 public:
73 // Typedefs from the Impl.
74 typedef typename Impl::CPUPol CPUPol;
75 typedef typename Impl::DynInstPtr DynInstPtr;
76 typedef typename Impl::O3CPU O3CPU;
77
78 // Typedefs from the CPUPol
79 typedef typename CPUPol::DecodeStruct DecodeStruct;
80 typedef typename CPUPol::RenameStruct RenameStruct;
81 typedef typename CPUPol::TimeStruct TimeStruct;
82 typedef typename CPUPol::FreeList FreeList;
83 typedef typename CPUPol::RenameMap RenameMap;
84 // These are used only for initialization.
85 typedef typename CPUPol::IEW IEW;
86 typedef typename CPUPol::Commit Commit;
87
88 // A deque is used to queue the instructions. Barrier insts must
89 // be added to the front of the queue, which is the only reason for
90 // using a deque instead of a queue. (Most other stages use a
91 // queue)
92 typedef std::deque<DynInstPtr> InstQueue;
93
94 public:
95 /** Overall rename status. Used to determine if the CPU can
96 * deschedule itself due to a lack of activity.
97 */
98 enum RenameStatus {
99 Active,
100 Inactive
101 };
102
103 /** Individual thread status. */
104 enum ThreadStatus {
105 Running,
106 Idle,
107 StartSquash,
108 Squashing,
109 Blocked,
110 Unblocking,
111 SerializeStall
112 };
113
114 private:
115 /** Rename status. */
116 RenameStatus _status;
117
118 /** Per-thread status. */
119 ThreadStatus renameStatus[Impl::MaxThreads];
120
121 /** Probe points. */
122 typedef typename std::pair<InstSeqNum, PhysRegIdPtr> SeqNumRegPair;
123 /** To probe when register renaming for an instruction is complete */
124 ProbePointArg<DynInstPtr> *ppRename;
125 /**
126 * To probe when an instruction is squashed and the register mapping
127 * for it needs to be undone
128 */
129 ProbePointArg<SeqNumRegPair> *ppSquashInRename;
130
131 public:
132 /** DefaultRename constructor. */
133 DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params);
134
135 /** Returns the name of rename. */
136 std::string name() const;
137
138 /** Registers statistics. */
139 void regStats();
140
141 /** Registers probes. */
142 void regProbePoints();
143
144 /** Sets the main backwards communication time buffer pointer. */
145 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
146
147 /** Sets pointer to time buffer used to communicate to the next stage. */
148 void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
149
150 /** Sets pointer to time buffer coming from decode. */
151 void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr);
152
153 /** Sets pointer to IEW stage. Used only for initialization. */
154 void setIEWStage(IEW *iew_stage)
155 { iew_ptr = iew_stage; }
156
157 /** Sets pointer to commit stage. Used only for initialization. */
158 void setCommitStage(Commit *commit_stage)
159 { commit_ptr = commit_stage; }
160
161 private:
162 /** Pointer to IEW stage. Used only for initialization. */
163 IEW *iew_ptr;
164
165 /** Pointer to commit stage. Used only for initialization. */
166 Commit *commit_ptr;
167
168 public:
169 /** Initializes variables for the stage. */
170 void startupStage();
171
172 /** Sets pointer to list of active threads. */
173 void setActiveThreads(std::list<ThreadID> *at_ptr);
174
175 /** Sets pointer to rename maps (per-thread structures). */
176 void setRenameMap(RenameMap rm_ptr[Impl::MaxThreads]);
177
178 /** Sets pointer to the free list. */
179 void setFreeList(FreeList *fl_ptr);
180
181 /** Sets pointer to the scoreboard. */
182 void setScoreboard(Scoreboard *_scoreboard);
183
184 /** Perform sanity checks after a drain. */
185 void drainSanityCheck() const;
186
187 /** Has the stage drained? */
188 bool isDrained() const;
189
190 /** Takes over from another CPU's thread. */
191 void takeOverFrom();
192
193 /** Squashes all instructions in a thread. */
194 void squash(const InstSeqNum &squash_seq_num, ThreadID tid);
195
196 /** Ticks rename, which processes all input signals and attempts to rename
197 * as many instructions as possible.
198 */
199 void tick();
200
201 /** Debugging function used to dump history buffer of renamings. */
202 void dumpHistory();
203
204 private:
205 /** Reset this pipeline stage */
206 void resetStage();
207
208 /** Determines what to do based on rename's current status.
209 * @param status_change rename() sets this variable if there was a status
210 * change (ie switching from blocking to unblocking).
211 * @param tid Thread id to rename instructions from.
212 */
213 void rename(bool &status_change, ThreadID tid);
214
215 /** Renames instructions for the given thread. Also handles serializing
216 * instructions.
217 */
218 void renameInsts(ThreadID tid);
219
220 /** Inserts unused instructions from a given thread into the skid buffer,
221 * to be renamed once rename unblocks.
222 */
223 void skidInsert(ThreadID tid);
224
225 /** Separates instructions from decode into individual lists of instructions
226 * sorted by thread.
227 */
228 void sortInsts();
229
230 /** Returns if all of the skid buffers are empty. */
231 bool skidsEmpty();
232
233 /** Updates overall rename status based on all of the threads' statuses. */
234 void updateStatus();
235
236 /** Switches rename to blocking, and signals back that rename has become
237 * blocked.
238 * @return Returns true if there is a status change.
239 */
240 bool block(ThreadID tid);
241
242 /** Switches rename to unblocking if the skid buffer is empty, and signals
243 * back that rename has unblocked.
244 * @return Returns true if there is a status change.
245 */
246 bool unblock(ThreadID tid);
247
248 /** Executes actual squash, removing squashed instructions. */
249 void doSquash(const InstSeqNum &squash_seq_num, ThreadID tid);
250
251 /** Removes a committed instruction's rename history. */
252 void removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid);
253
254 /** Renames the source registers of an instruction. */
255 inline void renameSrcRegs(DynInstPtr &inst, ThreadID tid);
256
257 /** Renames the destination registers of an instruction. */
258 inline void renameDestRegs(DynInstPtr &inst, ThreadID tid);
259
260 /** Calculates the number of free ROB entries for a specific thread. */
261 inline int calcFreeROBEntries(ThreadID tid);
262
263 /** Calculates the number of free IQ entries for a specific thread. */
264 inline int calcFreeIQEntries(ThreadID tid);
265
266 /** Calculates the number of free LQ entries for a specific thread. */
267 inline int calcFreeLQEntries(ThreadID tid);
268
269 /** Calculates the number of free SQ entries for a specific thread. */
270 inline int calcFreeSQEntries(ThreadID tid);
271
272 /** Returns the number of valid instructions coming from decode. */
273 unsigned validInsts();
274
275 /** Reads signals telling rename to block/unblock. */
276 void readStallSignals(ThreadID tid);
277
278 /** Checks if any stages are telling rename to block. */
279 bool checkStall(ThreadID tid);
280
281 /** Gets the number of free entries for a specific thread. */
282 void readFreeEntries(ThreadID tid);
283
284 /** Checks the signals and updates the status. */
285 bool checkSignalsAndUpdate(ThreadID tid);
286
287 /** Either serializes on the next instruction available in the InstQueue,
288 * or records that it must serialize on the next instruction to enter
289 * rename.
290 * @param inst_list The list of younger, unprocessed instructions for the
291 * thread that has the serializeAfter instruction.
292 * @param tid The thread id.
293 */
294 void serializeAfter(InstQueue &inst_list, ThreadID tid);
295
296 /** Holds the information for each destination register rename. It holds
297 * the instruction's sequence number, the arch register, the old physical
298 * register for that arch. register, and the new physical register.
299 */
300 struct RenameHistory {
| 1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * Copyright (c) 2013 Advanced Micro Devices, Inc.
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 */
43
44#ifndef __CPU_O3_RENAME_HH__
45#define __CPU_O3_RENAME_HH__
46
47#include <list>
48#include <utility>
49
50#include "base/statistics.hh"
51#include "config/the_isa.hh"
52#include "cpu/timebuf.hh"
53#include "sim/probe/probe.hh"
54
55struct DerivO3CPUParams;
56
57/**
58 * DefaultRename handles both single threaded and SMT rename. Its
59 * width is specified by the parameters; each cycle it tries to rename
60 * that many instructions. It holds onto the rename history of all
61 * instructions with destination registers, storing the
62 * arch. register, the new physical register, and the old physical
63 * register, to allow for undoing of mappings if squashing happens, or
64 * freeing up registers upon commit. Rename handles blocking if the
65 * ROB, IQ, or LSQ is going to be full. Rename also handles barriers,
66 * and does so by stalling on the instruction until the ROB is empty
67 * and there are no instructions in flight to the ROB.
68 */
69template<class Impl>
70class DefaultRename
71{
72 public:
73 // Typedefs from the Impl.
74 typedef typename Impl::CPUPol CPUPol;
75 typedef typename Impl::DynInstPtr DynInstPtr;
76 typedef typename Impl::O3CPU O3CPU;
77
78 // Typedefs from the CPUPol
79 typedef typename CPUPol::DecodeStruct DecodeStruct;
80 typedef typename CPUPol::RenameStruct RenameStruct;
81 typedef typename CPUPol::TimeStruct TimeStruct;
82 typedef typename CPUPol::FreeList FreeList;
83 typedef typename CPUPol::RenameMap RenameMap;
84 // These are used only for initialization.
85 typedef typename CPUPol::IEW IEW;
86 typedef typename CPUPol::Commit Commit;
87
88 // A deque is used to queue the instructions. Barrier insts must
89 // be added to the front of the queue, which is the only reason for
90 // using a deque instead of a queue. (Most other stages use a
91 // queue)
92 typedef std::deque<DynInstPtr> InstQueue;
93
94 public:
95 /** Overall rename status. Used to determine if the CPU can
96 * deschedule itself due to a lack of activity.
97 */
98 enum RenameStatus {
99 Active,
100 Inactive
101 };
102
103 /** Individual thread status. */
104 enum ThreadStatus {
105 Running,
106 Idle,
107 StartSquash,
108 Squashing,
109 Blocked,
110 Unblocking,
111 SerializeStall
112 };
113
114 private:
115 /** Rename status. */
116 RenameStatus _status;
117
118 /** Per-thread status. */
119 ThreadStatus renameStatus[Impl::MaxThreads];
120
121 /** Probe points. */
122 typedef typename std::pair<InstSeqNum, PhysRegIdPtr> SeqNumRegPair;
123 /** To probe when register renaming for an instruction is complete */
124 ProbePointArg<DynInstPtr> *ppRename;
125 /**
126 * To probe when an instruction is squashed and the register mapping
127 * for it needs to be undone
128 */
129 ProbePointArg<SeqNumRegPair> *ppSquashInRename;
130
131 public:
132 /** DefaultRename constructor. */
133 DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params);
134
135 /** Returns the name of rename. */
136 std::string name() const;
137
138 /** Registers statistics. */
139 void regStats();
140
141 /** Registers probes. */
142 void regProbePoints();
143
144 /** Sets the main backwards communication time buffer pointer. */
145 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
146
147 /** Sets pointer to time buffer used to communicate to the next stage. */
148 void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
149
150 /** Sets pointer to time buffer coming from decode. */
151 void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr);
152
153 /** Sets pointer to IEW stage. Used only for initialization. */
154 void setIEWStage(IEW *iew_stage)
155 { iew_ptr = iew_stage; }
156
157 /** Sets pointer to commit stage. Used only for initialization. */
158 void setCommitStage(Commit *commit_stage)
159 { commit_ptr = commit_stage; }
160
161 private:
162 /** Pointer to IEW stage. Used only for initialization. */
163 IEW *iew_ptr;
164
165 /** Pointer to commit stage. Used only for initialization. */
166 Commit *commit_ptr;
167
168 public:
169 /** Initializes variables for the stage. */
170 void startupStage();
171
172 /** Sets pointer to list of active threads. */
173 void setActiveThreads(std::list<ThreadID> *at_ptr);
174
175 /** Sets pointer to rename maps (per-thread structures). */
176 void setRenameMap(RenameMap rm_ptr[Impl::MaxThreads]);
177
178 /** Sets pointer to the free list. */
179 void setFreeList(FreeList *fl_ptr);
180
181 /** Sets pointer to the scoreboard. */
182 void setScoreboard(Scoreboard *_scoreboard);
183
184 /** Perform sanity checks after a drain. */
185 void drainSanityCheck() const;
186
187 /** Has the stage drained? */
188 bool isDrained() const;
189
190 /** Takes over from another CPU's thread. */
191 void takeOverFrom();
192
193 /** Squashes all instructions in a thread. */
194 void squash(const InstSeqNum &squash_seq_num, ThreadID tid);
195
196 /** Ticks rename, which processes all input signals and attempts to rename
197 * as many instructions as possible.
198 */
199 void tick();
200
201 /** Debugging function used to dump history buffer of renamings. */
202 void dumpHistory();
203
204 private:
205 /** Reset this pipeline stage */
206 void resetStage();
207
208 /** Determines what to do based on rename's current status.
209 * @param status_change rename() sets this variable if there was a status
210 * change (ie switching from blocking to unblocking).
211 * @param tid Thread id to rename instructions from.
212 */
213 void rename(bool &status_change, ThreadID tid);
214
215 /** Renames instructions for the given thread. Also handles serializing
216 * instructions.
217 */
218 void renameInsts(ThreadID tid);
219
220 /** Inserts unused instructions from a given thread into the skid buffer,
221 * to be renamed once rename unblocks.
222 */
223 void skidInsert(ThreadID tid);
224
225 /** Separates instructions from decode into individual lists of instructions
226 * sorted by thread.
227 */
228 void sortInsts();
229
230 /** Returns if all of the skid buffers are empty. */
231 bool skidsEmpty();
232
233 /** Updates overall rename status based on all of the threads' statuses. */
234 void updateStatus();
235
236 /** Switches rename to blocking, and signals back that rename has become
237 * blocked.
238 * @return Returns true if there is a status change.
239 */
240 bool block(ThreadID tid);
241
242 /** Switches rename to unblocking if the skid buffer is empty, and signals
243 * back that rename has unblocked.
244 * @return Returns true if there is a status change.
245 */
246 bool unblock(ThreadID tid);
247
248 /** Executes actual squash, removing squashed instructions. */
249 void doSquash(const InstSeqNum &squash_seq_num, ThreadID tid);
250
251 /** Removes a committed instruction's rename history. */
252 void removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid);
253
254 /** Renames the source registers of an instruction. */
255 inline void renameSrcRegs(DynInstPtr &inst, ThreadID tid);
256
257 /** Renames the destination registers of an instruction. */
258 inline void renameDestRegs(DynInstPtr &inst, ThreadID tid);
259
260 /** Calculates the number of free ROB entries for a specific thread. */
261 inline int calcFreeROBEntries(ThreadID tid);
262
263 /** Calculates the number of free IQ entries for a specific thread. */
264 inline int calcFreeIQEntries(ThreadID tid);
265
266 /** Calculates the number of free LQ entries for a specific thread. */
267 inline int calcFreeLQEntries(ThreadID tid);
268
269 /** Calculates the number of free SQ entries for a specific thread. */
270 inline int calcFreeSQEntries(ThreadID tid);
271
272 /** Returns the number of valid instructions coming from decode. */
273 unsigned validInsts();
274
275 /** Reads signals telling rename to block/unblock. */
276 void readStallSignals(ThreadID tid);
277
278 /** Checks if any stages are telling rename to block. */
279 bool checkStall(ThreadID tid);
280
281 /** Gets the number of free entries for a specific thread. */
282 void readFreeEntries(ThreadID tid);
283
284 /** Checks the signals and updates the status. */
285 bool checkSignalsAndUpdate(ThreadID tid);
286
287 /** Either serializes on the next instruction available in the InstQueue,
288 * or records that it must serialize on the next instruction to enter
289 * rename.
290 * @param inst_list The list of younger, unprocessed instructions for the
291 * thread that has the serializeAfter instruction.
292 * @param tid The thread id.
293 */
294 void serializeAfter(InstQueue &inst_list, ThreadID tid);
295
296 /** Holds the information for each destination register rename. It holds
297 * the instruction's sequence number, the arch register, the old physical
298 * register for that arch. register, and the new physical register.
299 */
300 struct RenameHistory {
|
302 PhysRegIdPtr _newPhysReg,
303 PhysRegIdPtr _prevPhysReg)
304 : instSeqNum(_instSeqNum), archReg(_archReg),
305 newPhysReg(_newPhysReg), prevPhysReg(_prevPhysReg)
306 {
307 }
308
309 /** The sequence number of the instruction that renamed. */
310 InstSeqNum instSeqNum;
311 /** The architectural register index that was renamed. */
312 RegId archReg;
313 /** The new physical register that the arch. register is renamed to. */
314 PhysRegIdPtr newPhysReg;
315 /** The old physical register that the arch. register was renamed to.
316 */
317 PhysRegIdPtr prevPhysReg;
318 };
319
320 /** A per-thread list of all destination register renames, used to either
321 * undo rename mappings or free old physical registers.
322 */
323 std::list<RenameHistory> historyBuffer[Impl::MaxThreads];
324
325 /** Pointer to CPU. */
326 O3CPU *cpu;
327
328 /** Pointer to main time buffer used for backwards communication. */
329 TimeBuffer<TimeStruct> *timeBuffer;
330
331 /** Wire to get IEW's output from backwards time buffer. */
332 typename TimeBuffer<TimeStruct>::wire fromIEW;
333
334 /** Wire to get commit's output from backwards time buffer. */
335 typename TimeBuffer<TimeStruct>::wire fromCommit;
336
337 /** Wire to write infromation heading to previous stages. */
338 typename TimeBuffer<TimeStruct>::wire toDecode;
339
340 /** Rename instruction queue. */
341 TimeBuffer<RenameStruct> *renameQueue;
342
343 /** Wire to write any information heading to IEW. */
344 typename TimeBuffer<RenameStruct>::wire toIEW;
345
346 /** Decode instruction queue interface. */
347 TimeBuffer<DecodeStruct> *decodeQueue;
348
349 /** Wire to get decode's output from decode queue. */
350 typename TimeBuffer<DecodeStruct>::wire fromDecode;
351
352 /** Queue of all instructions coming from decode this cycle. */
353 InstQueue insts[Impl::MaxThreads];
354
355 /** Skid buffer between rename and decode. */
356 InstQueue skidBuffer[Impl::MaxThreads];
357
358 /** Rename map interface. */
359 RenameMap *renameMap[Impl::MaxThreads];
360
361 /** Free list interface. */
362 FreeList *freeList;
363
364 /** Pointer to the list of active threads. */
365 std::list<ThreadID> *activeThreads;
366
367 /** Pointer to the scoreboard. */
368 Scoreboard *scoreboard;
369
370 /** Count of instructions in progress that have been sent off to the IQ
371 * and ROB, but are not yet included in their occupancy counts.
372 */
373 int instsInProgress[Impl::MaxThreads];
374
375 /** Count of Load instructions in progress that have been sent off to the IQ
376 * and ROB, but are not yet included in their occupancy counts.
377 */
378 int loadsInProgress[Impl::MaxThreads];
379
380 /** Count of Store instructions in progress that have been sent off to the IQ
381 * and ROB, but are not yet included in their occupancy counts.
382 */
383 int storesInProgress[Impl::MaxThreads];
384
385 /** Variable that tracks if decode has written to the time buffer this
386 * cycle. Used to tell CPU if there is activity this cycle.
387 */
388 bool wroteToTimeBuffer;
389
390 /** Structures whose free entries impact the amount of instructions that
391 * can be renamed.
392 */
393 struct FreeEntries {
394 unsigned iqEntries;
395 unsigned robEntries;
396 unsigned lqEntries;
397 unsigned sqEntries;
398 };
399
400 /** Per-thread tracking of the number of free entries of back-end
401 * structures.
402 */
403 FreeEntries freeEntries[Impl::MaxThreads];
404
405 /** Records if the ROB is empty. In SMT mode the ROB may be dynamically
406 * partitioned between threads, so the ROB must tell rename when it is
407 * empty.
408 */
409 bool emptyROB[Impl::MaxThreads];
410
411 /** Source of possible stalls. */
412 struct Stalls {
413 bool iew;
414 bool commit;
415 };
416
417 /** Tracks which stages are telling decode to stall. */
418 Stalls stalls[Impl::MaxThreads];
419
420 /** The serialize instruction that rename has stalled on. */
421 DynInstPtr serializeInst[Impl::MaxThreads];
422
423 /** Records if rename needs to serialize on the next instruction for any
424 * thread.
425 */
426 bool serializeOnNextInst[Impl::MaxThreads];
427
428 /** Delay between iew and rename, in ticks. */
429 int iewToRenameDelay;
430
431 /** Delay between decode and rename, in ticks. */
432 int decodeToRenameDelay;
433
434 /** Delay between commit and rename, in ticks. */
435 unsigned commitToRenameDelay;
436
437 /** Rename width, in instructions. */
438 unsigned renameWidth;
439
440 /** Commit width, in instructions. Used so rename knows how many
441 * instructions might have freed registers in the previous cycle.
442 */
443 unsigned commitWidth;
444
445 /** The index of the instruction in the time buffer to IEW that rename is
446 * currently using.
447 */
448 unsigned toIEWIndex;
449
450 /** Whether or not rename needs to block this cycle. */
451 bool blockThisCycle;
452
453 /** Whether or not rename needs to resume a serialize instruction
454 * after squashing. */
455 bool resumeSerialize;
456
457 /** Whether or not rename needs to resume clearing out the skidbuffer
458 * after squashing. */
459 bool resumeUnblocking;
460
461 /** The number of threads active in rename. */
462 ThreadID numThreads;
463
464 /** The maximum skid buffer size. */
465 unsigned skidBufferMax;
466
467 PhysRegIndex maxPhysicalRegs;
468
469 /** Enum to record the source of a structure full stall. Can come from
470 * either ROB, IQ, LSQ, and it is priortized in that order.
471 */
472 enum FullSource {
473 ROB,
474 IQ,
475 LQ,
476 SQ,
477 NONE
478 };
479
480 /** Function used to increment the stat that corresponds to the source of
481 * the stall.
482 */
483 inline void incrFullStat(const FullSource &source);
484
485 /** Stat for total number of cycles spent squashing. */
486 Stats::Scalar renameSquashCycles;
487 /** Stat for total number of cycles spent idle. */
488 Stats::Scalar renameIdleCycles;
489 /** Stat for total number of cycles spent blocking. */
490 Stats::Scalar renameBlockCycles;
491 /** Stat for total number of cycles spent stalling for a serializing inst. */
492 Stats::Scalar renameSerializeStallCycles;
493 /** Stat for total number of cycles spent running normally. */
494 Stats::Scalar renameRunCycles;
495 /** Stat for total number of cycles spent unblocking. */
496 Stats::Scalar renameUnblockCycles;
497 /** Stat for total number of renamed instructions. */
498 Stats::Scalar renameRenamedInsts;
499 /** Stat for total number of squashed instructions that rename discards. */
500 Stats::Scalar renameSquashedInsts;
501 /** Stat for total number of times that the ROB starts a stall in rename. */
502 Stats::Scalar renameROBFullEvents;
503 /** Stat for total number of times that the IQ starts a stall in rename. */
504 Stats::Scalar renameIQFullEvents;
505 /** Stat for total number of times that the LQ starts a stall in rename. */
506 Stats::Scalar renameLQFullEvents;
507 /** Stat for total number of times that the SQ starts a stall in rename. */
508 Stats::Scalar renameSQFullEvents;
509 /** Stat for total number of times that rename runs out of free registers
510 * to use to rename. */
511 Stats::Scalar renameFullRegistersEvents;
512 /** Stat for total number of renamed destination registers. */
513 Stats::Scalar renameRenamedOperands;
514 /** Stat for total number of source register rename lookups. */
515 Stats::Scalar renameRenameLookups;
516 Stats::Scalar intRenameLookups;
517 Stats::Scalar fpRenameLookups;
518 /** Stat for total number of committed renaming mappings. */
519 Stats::Scalar renameCommittedMaps;
520 /** Stat for total number of mappings that were undone due to a squash. */
521 Stats::Scalar renameUndoneMaps;
522 /** Number of serialize instructions handled. */
523 Stats::Scalar renamedSerializing;
524 /** Number of instructions marked as temporarily serializing. */
525 Stats::Scalar renamedTempSerializing;
526 /** Number of instructions inserted into skid buffers. */
527 Stats::Scalar renameSkidInsts;
528};
529
530#endif // __CPU_O3_RENAME_HH__
| 302 PhysRegIdPtr _newPhysReg,
303 PhysRegIdPtr _prevPhysReg)
304 : instSeqNum(_instSeqNum), archReg(_archReg),
305 newPhysReg(_newPhysReg), prevPhysReg(_prevPhysReg)
306 {
307 }
308
309 /** The sequence number of the instruction that renamed. */
310 InstSeqNum instSeqNum;
311 /** The architectural register index that was renamed. */
312 RegId archReg;
313 /** The new physical register that the arch. register is renamed to. */
314 PhysRegIdPtr newPhysReg;
315 /** The old physical register that the arch. register was renamed to.
316 */
317 PhysRegIdPtr prevPhysReg;
318 };
319
320 /** A per-thread list of all destination register renames, used to either
321 * undo rename mappings or free old physical registers.
322 */
323 std::list<RenameHistory> historyBuffer[Impl::MaxThreads];
324
325 /** Pointer to CPU. */
326 O3CPU *cpu;
327
328 /** Pointer to main time buffer used for backwards communication. */
329 TimeBuffer<TimeStruct> *timeBuffer;
330
331 /** Wire to get IEW's output from backwards time buffer. */
332 typename TimeBuffer<TimeStruct>::wire fromIEW;
333
334 /** Wire to get commit's output from backwards time buffer. */
335 typename TimeBuffer<TimeStruct>::wire fromCommit;
336
337 /** Wire to write infromation heading to previous stages. */
338 typename TimeBuffer<TimeStruct>::wire toDecode;
339
340 /** Rename instruction queue. */
341 TimeBuffer<RenameStruct> *renameQueue;
342
343 /** Wire to write any information heading to IEW. */
344 typename TimeBuffer<RenameStruct>::wire toIEW;
345
346 /** Decode instruction queue interface. */
347 TimeBuffer<DecodeStruct> *decodeQueue;
348
349 /** Wire to get decode's output from decode queue. */
350 typename TimeBuffer<DecodeStruct>::wire fromDecode;
351
352 /** Queue of all instructions coming from decode this cycle. */
353 InstQueue insts[Impl::MaxThreads];
354
355 /** Skid buffer between rename and decode. */
356 InstQueue skidBuffer[Impl::MaxThreads];
357
358 /** Rename map interface. */
359 RenameMap *renameMap[Impl::MaxThreads];
360
361 /** Free list interface. */
362 FreeList *freeList;
363
364 /** Pointer to the list of active threads. */
365 std::list<ThreadID> *activeThreads;
366
367 /** Pointer to the scoreboard. */
368 Scoreboard *scoreboard;
369
370 /** Count of instructions in progress that have been sent off to the IQ
371 * and ROB, but are not yet included in their occupancy counts.
372 */
373 int instsInProgress[Impl::MaxThreads];
374
375 /** Count of Load instructions in progress that have been sent off to the IQ
376 * and ROB, but are not yet included in their occupancy counts.
377 */
378 int loadsInProgress[Impl::MaxThreads];
379
380 /** Count of Store instructions in progress that have been sent off to the IQ
381 * and ROB, but are not yet included in their occupancy counts.
382 */
383 int storesInProgress[Impl::MaxThreads];
384
385 /** Variable that tracks if decode has written to the time buffer this
386 * cycle. Used to tell CPU if there is activity this cycle.
387 */
388 bool wroteToTimeBuffer;
389
390 /** Structures whose free entries impact the amount of instructions that
391 * can be renamed.
392 */
393 struct FreeEntries {
394 unsigned iqEntries;
395 unsigned robEntries;
396 unsigned lqEntries;
397 unsigned sqEntries;
398 };
399
400 /** Per-thread tracking of the number of free entries of back-end
401 * structures.
402 */
403 FreeEntries freeEntries[Impl::MaxThreads];
404
405 /** Records if the ROB is empty. In SMT mode the ROB may be dynamically
406 * partitioned between threads, so the ROB must tell rename when it is
407 * empty.
408 */
409 bool emptyROB[Impl::MaxThreads];
410
411 /** Source of possible stalls. */
412 struct Stalls {
413 bool iew;
414 bool commit;
415 };
416
417 /** Tracks which stages are telling decode to stall. */
418 Stalls stalls[Impl::MaxThreads];
419
420 /** The serialize instruction that rename has stalled on. */
421 DynInstPtr serializeInst[Impl::MaxThreads];
422
423 /** Records if rename needs to serialize on the next instruction for any
424 * thread.
425 */
426 bool serializeOnNextInst[Impl::MaxThreads];
427
428 /** Delay between iew and rename, in ticks. */
429 int iewToRenameDelay;
430
431 /** Delay between decode and rename, in ticks. */
432 int decodeToRenameDelay;
433
434 /** Delay between commit and rename, in ticks. */
435 unsigned commitToRenameDelay;
436
437 /** Rename width, in instructions. */
438 unsigned renameWidth;
439
440 /** Commit width, in instructions. Used so rename knows how many
441 * instructions might have freed registers in the previous cycle.
442 */
443 unsigned commitWidth;
444
445 /** The index of the instruction in the time buffer to IEW that rename is
446 * currently using.
447 */
448 unsigned toIEWIndex;
449
450 /** Whether or not rename needs to block this cycle. */
451 bool blockThisCycle;
452
453 /** Whether or not rename needs to resume a serialize instruction
454 * after squashing. */
455 bool resumeSerialize;
456
457 /** Whether or not rename needs to resume clearing out the skidbuffer
458 * after squashing. */
459 bool resumeUnblocking;
460
461 /** The number of threads active in rename. */
462 ThreadID numThreads;
463
464 /** The maximum skid buffer size. */
465 unsigned skidBufferMax;
466
467 PhysRegIndex maxPhysicalRegs;
468
469 /** Enum to record the source of a structure full stall. Can come from
470 * either ROB, IQ, LSQ, and it is priortized in that order.
471 */
472 enum FullSource {
473 ROB,
474 IQ,
475 LQ,
476 SQ,
477 NONE
478 };
479
480 /** Function used to increment the stat that corresponds to the source of
481 * the stall.
482 */
483 inline void incrFullStat(const FullSource &source);
484
485 /** Stat for total number of cycles spent squashing. */
486 Stats::Scalar renameSquashCycles;
487 /** Stat for total number of cycles spent idle. */
488 Stats::Scalar renameIdleCycles;
489 /** Stat for total number of cycles spent blocking. */
490 Stats::Scalar renameBlockCycles;
491 /** Stat for total number of cycles spent stalling for a serializing inst. */
492 Stats::Scalar renameSerializeStallCycles;
493 /** Stat for total number of cycles spent running normally. */
494 Stats::Scalar renameRunCycles;
495 /** Stat for total number of cycles spent unblocking. */
496 Stats::Scalar renameUnblockCycles;
497 /** Stat for total number of renamed instructions. */
498 Stats::Scalar renameRenamedInsts;
499 /** Stat for total number of squashed instructions that rename discards. */
500 Stats::Scalar renameSquashedInsts;
501 /** Stat for total number of times that the ROB starts a stall in rename. */
502 Stats::Scalar renameROBFullEvents;
503 /** Stat for total number of times that the IQ starts a stall in rename. */
504 Stats::Scalar renameIQFullEvents;
505 /** Stat for total number of times that the LQ starts a stall in rename. */
506 Stats::Scalar renameLQFullEvents;
507 /** Stat for total number of times that the SQ starts a stall in rename. */
508 Stats::Scalar renameSQFullEvents;
509 /** Stat for total number of times that rename runs out of free registers
510 * to use to rename. */
511 Stats::Scalar renameFullRegistersEvents;
512 /** Stat for total number of renamed destination registers. */
513 Stats::Scalar renameRenamedOperands;
514 /** Stat for total number of source register rename lookups. */
515 Stats::Scalar renameRenameLookups;
516 Stats::Scalar intRenameLookups;
517 Stats::Scalar fpRenameLookups;
518 /** Stat for total number of committed renaming mappings. */
519 Stats::Scalar renameCommittedMaps;
520 /** Stat for total number of mappings that were undone due to a squash. */
521 Stats::Scalar renameUndoneMaps;
522 /** Number of serialize instructions handled. */
523 Stats::Scalar renamedSerializing;
524 /** Number of instructions marked as temporarily serializing. */
525 Stats::Scalar renamedTempSerializing;
526 /** Number of instructions inserted into skid buffers. */
527 Stats::Scalar renameSkidInsts;
528};
529
530#endif // __CPU_O3_RENAME_HH__
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