1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the

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19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31// Todo:
32// Fix up trap and barrier handling.
33// May want to have different statuses to differentiate the different stall
34// conditions.
35
36#ifndef __CPU_O3_CPU_SIMPLE_RENAME_HH__
37#define __CPU_O3_CPU_SIMPLE_RENAME_HH__
38
39#include <list>
40
41#include "base/statistics.hh"
42#include "base/timebuf.hh"
43
44// Will need rename maps for both the int reg file and fp reg file.
45// Or change rename map class to handle both. (RegFile handles both.)
46template<class Impl>
47class SimpleRename
48{
49 public:
50 // Typedefs from the Impl.
51 typedef typename Impl::CPUPol CPUPol;
52 typedef typename Impl::DynInstPtr DynInstPtr;
53 typedef typename Impl::FullCPU FullCPU;
54 typedef typename Impl::Params Params;
55
56 typedef typename CPUPol::FetchStruct FetchStruct;
57 typedef typename CPUPol::DecodeStruct DecodeStruct;
58 typedef typename CPUPol::RenameStruct RenameStruct;
59 typedef typename CPUPol::TimeStruct TimeStruct;
60
61 // Typedefs from the CPUPol
62 typedef typename CPUPol::FreeList FreeList;
63 typedef typename CPUPol::RenameMap RenameMap;
64
65 // Typedefs from the ISA.
66 typedef TheISA::RegIndex RegIndex;
67
68 public:
69 // Rename will block if ROB becomes full or issue queue becomes full,
70 // or there are no free registers to rename to.
71 // Only case where rename squashes is if IEW squashes.
72 enum Status {
73 Running,
74 Idle,
75 Squashing,
76 Blocked,
77 Unblocking,
78 BarrierStall
79 };
80
81 private:
82 Status _status;
83
84 public:
85 SimpleRename(Params &params);
86
87 void regStats();
88
89 void setCPU(FullCPU *cpu_ptr);
90
91 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
92
93 void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
94
95 void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr);
96
97 void setRenameMap(RenameMap *rm_ptr);
98
99 void setFreeList(FreeList *fl_ptr);
100
101 void dumpHistory();
102
103 void tick();
104
105 void rename();
106
107 void squash();
108
109 private:
110 void block();
111
112 inline void unblock();
113
114 void doSquash();
115
116 void removeFromHistory(InstSeqNum inst_seq_num);
117
118 inline void renameSrcRegs(DynInstPtr &inst);
119
120 inline void renameDestRegs(DynInstPtr &inst);
121
122 inline int calcFreeROBEntries();
123
124 inline int calcFreeIQEntries();
125
126 /** Holds the previous information for each rename.
127 * Note that often times the inst may have been deleted, so only access
128 * the pointer for the address and do not dereference it.
129 */
130 struct RenameHistory {
131 RenameHistory(InstSeqNum _instSeqNum, RegIndex _archReg,
132 PhysRegIndex _newPhysReg, PhysRegIndex _prevPhysReg)
133 : instSeqNum(_instSeqNum), archReg(_archReg),
134 newPhysReg(_newPhysReg), prevPhysReg(_prevPhysReg),
135 placeHolder(false)
136 {
137 }
138
139 /** Constructor used specifically for cases where a place holder
140 * rename history entry is being made.
141 */
142 RenameHistory(InstSeqNum _instSeqNum)
143 : instSeqNum(_instSeqNum), archReg(0), newPhysReg(0),
144 prevPhysReg(0), placeHolder(true)
145 {
146 }
147
148 InstSeqNum instSeqNum;
149 RegIndex archReg;
150 PhysRegIndex newPhysReg;
151 PhysRegIndex prevPhysReg;
152 bool placeHolder;
153 };
154
155 std::list<RenameHistory> historyBuffer;
156
157 /** CPU interface. */
158 FullCPU *cpu;
159
160 // Interfaces to objects outside of rename.
161 /** Time buffer interface. */
162 TimeBuffer<TimeStruct> *timeBuffer;
163
164 /** Wire to get IEW's output from backwards time buffer. */
165 typename TimeBuffer<TimeStruct>::wire fromIEW;
166
167 /** Wire to get commit's output from backwards time buffer. */
168 typename TimeBuffer<TimeStruct>::wire fromCommit;
169
170 /** Wire to write infromation heading to previous stages. */
171 // Might not be the best name as not only decode will read it.
172 typename TimeBuffer<TimeStruct>::wire toDecode;
173
174 /** Rename instruction queue. */
175 TimeBuffer<RenameStruct> *renameQueue;
176
177 /** Wire to write any information heading to IEW. */
178 typename TimeBuffer<RenameStruct>::wire toIEW;
179
180 /** Decode instruction queue interface. */
181 TimeBuffer<DecodeStruct> *decodeQueue;
182
183 /** Wire to get decode's output from decode queue. */
184 typename TimeBuffer<DecodeStruct>::wire fromDecode;
185
186 /** Skid buffer between rename and decode. */
187 std::queue<DecodeStruct> skidBuffer;
188
189 /** Rename map interface. */
190 SimpleRenameMap *renameMap;
191
192 /** Free list interface. */
193 FreeList *freeList;
194
195 /** Delay between iew and rename, in ticks. */
196 int iewToRenameDelay;
197
198 /** Delay between decode and rename, in ticks. */
199 int decodeToRenameDelay;
200
201 /** Delay between commit and rename, in ticks. */
202 unsigned commitToRenameDelay;
203
204 /** Rename width, in instructions. */
205 unsigned renameWidth;
206
207 /** Commit width, in instructions. Used so rename knows how many
208 * instructions might have freed registers in the previous cycle.
209 */
210 unsigned commitWidth;
211
212 /** The instruction that rename is currently on. It needs to have
213 * persistent state so that when a stall occurs in the middle of a
214 * group of instructions, it can restart at the proper instruction.
215 */
216 unsigned numInst;
217
218 Stats::Scalar<> renameSquashCycles;
219 Stats::Scalar<> renameIdleCycles;
220 Stats::Scalar<> renameBlockCycles;
221 Stats::Scalar<> renameUnblockCycles;
222 Stats::Scalar<> renameRenamedInsts;
223 Stats::Scalar<> renameSquashedInsts;
224 Stats::Scalar<> renameROBFullEvents;
225 Stats::Scalar<> renameIQFullEvents;
226 Stats::Scalar<> renameFullRegistersEvents;
227 Stats::Scalar<> renameRenamedOperands;
228 Stats::Scalar<> renameRenameLookups;
229 Stats::Scalar<> renameHBPlaceHolders;
230 Stats::Scalar<> renameCommittedMaps;
231 Stats::Scalar<> renameUndoneMaps;
232 Stats::Scalar<> renameValidUndoneMaps;
233};
234
235#endif // __CPU_O3_CPU_SIMPLE_RENAME_HH__