regfile.hh (4329:52057dbec096) regfile.hh (4352:52f11aaf7d19)
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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169 }
170
171 /** Sets a single precision floating point register to the given value. */
172 void setFloatReg(PhysRegIndex reg_idx, FloatReg val, int width)
173 {
174 // Remove the base Float reg dependency.
175 reg_idx = reg_idx - numPhysicalIntRegs;
176
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 160 unchanged lines hidden (view full) ---

169 }
170
171 /** Sets a single precision floating point register to the given value. */
172 void setFloatReg(PhysRegIndex reg_idx, FloatReg val, int width)
173 {
174 // Remove the base Float reg dependency.
175 reg_idx = reg_idx - numPhysicalIntRegs;
176
177 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
177 assert(reg_idx < numPhysicalFloatRegs);
178
179 DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
180 int(reg_idx), (uint64_t)val);
181
182 if (reg_idx != TheISA::ZeroReg)
183 floatRegFile[reg_idx].d = val;
184 }
185
186 /** Sets a double precision floating point register to the given value. */
187 void setFloatReg(PhysRegIndex reg_idx, FloatReg val)
188 {
189 // Remove the base Float reg dependency.
190 reg_idx = reg_idx - numPhysicalIntRegs;
191
178
179 DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
180 int(reg_idx), (uint64_t)val);
181
182 if (reg_idx != TheISA::ZeroReg)
183 floatRegFile[reg_idx].d = val;
184 }
185
186 /** Sets a double precision floating point register to the given value. */
187 void setFloatReg(PhysRegIndex reg_idx, FloatReg val)
188 {
189 // Remove the base Float reg dependency.
190 reg_idx = reg_idx - numPhysicalIntRegs;
191
192 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
192 assert(reg_idx < numPhysicalFloatRegs);
193
194 DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
195 int(reg_idx), (uint64_t)val);
196
197 if (reg_idx != TheISA::ZeroReg)
198 floatRegFile[reg_idx].d = val;
199 }
200
201 /** Sets a floating point register to the given integer value. */
202 void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val, int width)
203 {
204 // Remove the base Float reg dependency.
205 reg_idx = reg_idx - numPhysicalIntRegs;
206
193
194 DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
195 int(reg_idx), (uint64_t)val);
196
197 if (reg_idx != TheISA::ZeroReg)
198 floatRegFile[reg_idx].d = val;
199 }
200
201 /** Sets a floating point register to the given integer value. */
202 void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val, int width)
203 {
204 // Remove the base Float reg dependency.
205 reg_idx = reg_idx - numPhysicalIntRegs;
206
207 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
207 assert(reg_idx < numPhysicalFloatRegs);
208
209 DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
210 int(reg_idx), (uint64_t)val);
211
212 floatRegFile[reg_idx].q = val;
213 }
214
215 void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val)
216 {
217 // Remove the base Float reg dependency.
218 reg_idx = reg_idx - numPhysicalIntRegs;
219
208
209 DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
210 int(reg_idx), (uint64_t)val);
211
212 floatRegFile[reg_idx].q = val;
213 }
214
215 void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val)
216 {
217 // Remove the base Float reg dependency.
218 reg_idx = reg_idx - numPhysicalIntRegs;
219
220 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
220 assert(reg_idx < numPhysicalFloatRegs);
221
222 DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
223 int(reg_idx), (uint64_t)val);
224
225 floatRegFile[reg_idx].q = val;
226 }
227
228 MiscReg readMiscRegNoEffect(int misc_reg, unsigned thread_id)
229 {
230 return miscRegs[thread_id].readRegNoEffect(misc_reg);
231 }
232
233 MiscReg readMiscReg(int misc_reg, unsigned thread_id)
234 {
221
222 DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
223 int(reg_idx), (uint64_t)val);
224
225 floatRegFile[reg_idx].q = val;
226 }
227
228 MiscReg readMiscRegNoEffect(int misc_reg, unsigned thread_id)
229 {
230 return miscRegs[thread_id].readRegNoEffect(misc_reg);
231 }
232
233 MiscReg readMiscReg(int misc_reg, unsigned thread_id)
234 {
235 return miscRegs[thread_id].readReg(misc_reg,
236 cpu->tcBase(thread_id));
235 return miscRegs[thread_id].readReg(misc_reg, cpu->tcBase(thread_id));
237 }
238
236 }
237
239 void setMiscRegNoEffect(int misc_reg, const MiscReg &val, unsigned thread_id)
238 void setMiscRegNoEffect(int misc_reg,
239 const MiscReg &val, unsigned thread_id)
240 {
241 miscRegs[thread_id].setRegNoEffect(misc_reg, val);
242 }
243
244 void setMiscReg(int misc_reg, const MiscReg &val,
245 unsigned thread_id)
246 {
247 miscRegs[thread_id].setReg(misc_reg, val,

--- 47 unchanged lines hidden --- 		240 {
241 miscRegs[thread_id].setRegNoEffect(misc_reg, val);
242 }
243
244 void setMiscReg(int misc_reg, const MiscReg &val,
245 unsigned thread_id)
246 {
247 miscRegs[thread_id].setReg(misc_reg, val,

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