regfile.hh (3565:6ad587fb7dfd) regfile.hh (4172:141705d83494)
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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220 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
221
222 DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
223 int(reg_idx), (uint64_t)val);
224
225 floatRegFile[reg_idx].q = val;
226 }
227
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 211 unchanged lines hidden (view full) ---

220 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
221
222 DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
223 int(reg_idx), (uint64_t)val);
224
225 floatRegFile[reg_idx].q = val;
226 }
227
228 MiscReg readMiscReg(int misc_reg, unsigned thread_id)
228 MiscReg readMiscRegNoEffect(int misc_reg, unsigned thread_id)
229 {
229 {
230 return miscRegs[thread_id].readReg(misc_reg);
230 return miscRegs[thread_id].readRegNoEffect(misc_reg);
231 }
232
231 }
232
233 MiscReg readMiscRegWithEffect(int misc_reg, unsigned thread_id)
233 MiscReg readMiscReg(int misc_reg, unsigned thread_id)
234 {
234 {
235 return miscRegs[thread_id].readRegWithEffect(misc_reg,
235 return miscRegs[thread_id].readReg(misc_reg,
236 cpu->tcBase(thread_id));
237 }
238
236 cpu->tcBase(thread_id));
237 }
238
239 void setMiscReg(int misc_reg, const MiscReg &val, unsigned thread_id)
239 void setMiscRegNoEffect(int misc_reg, const MiscReg &val, unsigned thread_id)
240 {
240 {
241 miscRegs[thread_id].setReg(misc_reg, val);
241 miscRegs[thread_id].setRegNoEffect(misc_reg, val);
242 }
243
242 }
243
244 void setMiscRegWithEffect(int misc_reg, const MiscReg &val,
244 void setMiscReg(int misc_reg, const MiscReg &val,
245 unsigned thread_id)
246 {
245 unsigned thread_id)
246 {
247 miscRegs[thread_id].setRegWithEffect(misc_reg, val,
247 miscRegs[thread_id].setReg(misc_reg, val,
248 cpu->tcBase(thread_id));
249 }
250
251 public:
252 /** (signed) integer register file. */
253 IntReg *intRegFile;
254
255 /** Floating point register file. */

--- 42 unchanged lines hidden --- 		248 cpu->tcBase(thread_id));
249 }
250
251 public:
252 /** (signed) integer register file. */
253 IntReg *intRegFile;
254
255 /** Floating point register file. */

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