regfile.hh (3454:26850ac19a39) regfile.hh (3468:cf23ad1ceef2)
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 23 unchanged lines hidden (view full) ---

32#ifndef __CPU_O3_REGFILE_HH__
33#define __CPU_O3_REGFILE_HH__
34
35#include "arch/isa_traits.hh"
36#include "arch/types.hh"
37#include "base/trace.hh"
38#include "config/full_system.hh"
39#include "cpu/o3/comm.hh"
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 23 unchanged lines hidden (view full) ---

32#ifndef __CPU_O3_REGFILE_HH__
33#define __CPU_O3_REGFILE_HH__
34
35#include "arch/isa_traits.hh"
36#include "arch/types.hh"
37#include "base/trace.hh"
38#include "config/full_system.hh"
39#include "cpu/o3/comm.hh"
40#include "sim/faults.hh"
41
42#if FULL_SYSTEM
43#include "kern/kernel_stats.hh"
44
45#endif
46
47#include <vector>
48

--- 178 unchanged lines hidden (view full) ---

227 floatRegFile[reg_idx].q = val;
228 }
229
230 MiscReg readMiscReg(int misc_reg, unsigned thread_id)
231 {
232 return miscRegs[thread_id].readReg(misc_reg);
233 }
234
40
41#if FULL_SYSTEM
42#include "kern/kernel_stats.hh"
43
44#endif
45
46#include <vector>
47

--- 178 unchanged lines hidden (view full) ---

226 floatRegFile[reg_idx].q = val;
227 }
228
229 MiscReg readMiscReg(int misc_reg, unsigned thread_id)
230 {
231 return miscRegs[thread_id].readReg(misc_reg);
232 }
233
235 MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault,
236 unsigned thread_id)
234 MiscReg readMiscRegWithEffect(int misc_reg, unsigned thread_id)
237 {
235 {
238 return miscRegs[thread_id].readRegWithEffect(misc_reg, fault,
236 return miscRegs[thread_id].readRegWithEffect(misc_reg,
239 cpu->tcBase(thread_id));
240 }
241
237 cpu->tcBase(thread_id));
238 }
239
242 Fault setMiscReg(int misc_reg, const MiscReg &val, unsigned thread_id)
240 void setMiscReg(int misc_reg, const MiscReg &val, unsigned thread_id)
243 {
241 {
244 return miscRegs[thread_id].setReg(misc_reg, val);
242 miscRegs[thread_id].setReg(misc_reg, val);
245 }
246
243 }
244
247 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val,
245 void setMiscRegWithEffect(int misc_reg, const MiscReg &val,
248 unsigned thread_id)
249 {
246 unsigned thread_id)
247 {
250 return miscRegs[thread_id].setRegWithEffect(misc_reg, val,
248 miscRegs[thread_id].setRegWithEffect(misc_reg, val,
251 cpu->tcBase(thread_id));
252 }
253
254 public:
255 /** (signed) integer register file. */
256 IntReg *intRegFile;
257
258 /** Floating point register file. */

--- 42 unchanged lines hidden --- 		249 cpu->tcBase(thread_id));
250 }
251
252 public:
253 /** (signed) integer register file. */
254 IntReg *intRegFile;
255
256 /** Floating point register file. */

--- 42 unchanged lines hidden ---