regfile.hh (2670:9107b8bd08cd) regfile.hh (2680:246e7104f744)
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 226 unchanged lines hidden (view full) ---

235 {
236 return miscRegs[thread_id].readReg(misc_reg);
237 }
238
239 MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault,
240 unsigned thread_id)
241 {
242 return miscRegs[thread_id].readRegWithEffect(misc_reg, fault,
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 226 unchanged lines hidden (view full) ---

235 {
236 return miscRegs[thread_id].readReg(misc_reg);
237 }
238
239 MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault,
240 unsigned thread_id)
241 {
242 return miscRegs[thread_id].readRegWithEffect(misc_reg, fault,
243 cpu->xcBase(thread_id));
243 cpu->tcBase(thread_id));
244 }
245
246 Fault setMiscReg(int misc_reg, const MiscReg &val, unsigned thread_id)
247 {
248 return miscRegs[thread_id].setReg(misc_reg, val);
249 }
250
251 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val,
252 unsigned thread_id)
253 {
254 return miscRegs[thread_id].setRegWithEffect(misc_reg, val,
244 }
245
246 Fault setMiscReg(int misc_reg, const MiscReg &val, unsigned thread_id)
247 {
248 return miscRegs[thread_id].setReg(misc_reg, val);
249 }
250
251 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val,
252 unsigned thread_id)
253 {
254 return miscRegs[thread_id].setRegWithEffect(misc_reg, val,
255 cpu->xcBase(thread_id));
255 cpu->tcBase(thread_id));
256 }
257
258#if FULL_SYSTEM
259 int readIntrFlag() { return intrflag; }
260 /** Sets an interrupt flag. */
261 void setIntrFlag(int val) { intrflag = val; }
262#endif
263

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257
258#if FULL_SYSTEM
259 int readIntrFlag() { return intrflag; }
260 /** Sets an interrupt flag. */
261 void setIntrFlag(int val) { intrflag = val; }
262#endif
263

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