regfile.hh (2665:a124942bacb8) | regfile.hh (2669:f2b336e89d2a) |
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1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 10 unchanged lines hidden (view full) --- 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | 1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 10 unchanged lines hidden (view full) --- 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 * 28 * Authors: Kevin Lim 29 * Gabe Black | |
30 */ 31 | 27 */ 28 |
32#ifndef __CPU_O3_CPU_REGFILE_HH__ 33#define __CPU_O3_CPU_REGFILE_HH__ | 29#ifndef __CPU_O3_REGFILE_HH__ 30#define __CPU_O3_REGFILE_HH__ |
34 | 31 |
35// @todo: Destructor 36 | |
37#include "arch/isa_traits.hh" 38#include "arch/faults.hh" | 32#include "arch/isa_traits.hh" 33#include "arch/faults.hh" |
34#include "arch/types.hh" |
|
39#include "base/trace.hh" 40#include "config/full_system.hh" 41#include "cpu/o3/comm.hh" 42 43#if FULL_SYSTEM 44#include "kern/kernel_stats.hh" 45 46#endif 47 | 35#include "base/trace.hh" 36#include "config/full_system.hh" 37#include "cpu/o3/comm.hh" 38 39#if FULL_SYSTEM 40#include "kern/kernel_stats.hh" 41 42#endif 43 |
48// This really only depends on the ISA, and not the Impl. It might be nicer 49// to see if I can make it depend on nothing... 50// Things that are in the ifdef FULL_SYSTEM are pretty dependent on the ISA, 51// and should go in the AlphaFullCPU. | 44#include <vector> |
52 | 45 |
46/** 47 * Simple physical register file class. 48 * Right now this is specific to Alpha until we decide if/how to make things 49 * generic enough to support other ISAs. 50 */ |
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53template <class Impl> 54class PhysRegFile 55{ 56 protected: 57 typedef TheISA::IntReg IntReg; 58 typedef TheISA::FloatReg FloatReg; | 51template <class Impl> 52class PhysRegFile 53{ 54 protected: 55 typedef TheISA::IntReg IntReg; 56 typedef TheISA::FloatReg FloatReg; |
57 typedef TheISA::FloatRegBits FloatRegBits; |
|
59 typedef TheISA::MiscRegFile MiscRegFile; 60 typedef TheISA::MiscReg MiscReg; 61 | 58 typedef TheISA::MiscRegFile MiscRegFile; 59 typedef TheISA::MiscReg MiscReg; 60 |
62 //Note that most of the definitions of the IntReg, FloatReg, etc. exist 63 //within the Impl/ISA class and not within this PhysRegFile class. | 61 typedef union { 62 FloatReg d; 63 FloatRegBits q; 64 } PhysFloatReg; |
64 | 65 |
65 //Will need some way to allow stuff like swap_palshadow to access the 66 //correct registers. Might require code changes to swap_palshadow and 67 //other execution contexts. | 66 // Note that most of the definitions of the IntReg, FloatReg, etc. exist 67 // within the Impl/ISA class and not within this PhysRegFile class. |
68 | 68 |
69 //Will make these registers public for now, but they probably should 70 //be private eventually with some accessor functions. | 69 // Will make these registers public for now, but they probably should 70 // be private eventually with some accessor functions. |
71 public: 72 typedef typename Impl::FullCPU FullCPU; 73 | 71 public: 72 typedef typename Impl::FullCPU FullCPU; 73 |
74 /** 75 * Constructs a physical register file with the specified amount of 76 * integer and floating point registers. 77 */ |
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74 PhysRegFile(unsigned _numPhysicalIntRegs, 75 unsigned _numPhysicalFloatRegs); 76 77 //Everything below should be pretty well identical to the normal 78 //register file that exists within AlphaISA class. 79 //The duplication is unfortunate but it's better than having 80 //different ways to access certain registers. 81 82 //Add these in later when everything else is in place 83// void serialize(std::ostream &os); 84// void unserialize(Checkpoint *cp, const std::string §ion); 85 | 78 PhysRegFile(unsigned _numPhysicalIntRegs, 79 unsigned _numPhysicalFloatRegs); 80 81 //Everything below should be pretty well identical to the normal 82 //register file that exists within AlphaISA class. 83 //The duplication is unfortunate but it's better than having 84 //different ways to access certain registers. 85 86 //Add these in later when everything else is in place 87// void serialize(std::ostream &os); 88// void unserialize(Checkpoint *cp, const std::string §ion); 89 |
90 /** Reads an integer register. */ |
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86 uint64_t readIntReg(PhysRegIndex reg_idx) 87 { 88 assert(reg_idx < numPhysicalIntRegs); 89 90 DPRINTF(IEW, "RegFile: Access to int register %i, has data " 91 "%i\n", int(reg_idx), intRegFile[reg_idx]); 92 return intRegFile[reg_idx]; 93 } 94 95 FloatReg readFloatReg(PhysRegIndex reg_idx, int width) 96 { 97 // Remove the base Float reg dependency. 98 reg_idx = reg_idx - numPhysicalIntRegs; 99 100 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 101 | 91 uint64_t readIntReg(PhysRegIndex reg_idx) 92 { 93 assert(reg_idx < numPhysicalIntRegs); 94 95 DPRINTF(IEW, "RegFile: Access to int register %i, has data " 96 "%i\n", int(reg_idx), intRegFile[reg_idx]); 97 return intRegFile[reg_idx]; 98 } 99 100 FloatReg readFloatReg(PhysRegIndex reg_idx, int width) 101 { 102 // Remove the base Float reg dependency. 103 reg_idx = reg_idx - numPhysicalIntRegs; 104 105 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 106 |
102 FloatReg floatReg = floatRegFile.readReg(reg_idx, width); | 107 FloatReg floatReg = floatRegFile[reg_idx].d; |
103 104 DPRINTF(IEW, "RegFile: Access to %d byte float register %i, has " 105 "data %8.8d\n", int(reg_idx), (double)floatReg); 106 107 return floatReg; 108 } 109 | 108 109 DPRINTF(IEW, "RegFile: Access to %d byte float register %i, has " 110 "data %8.8d\n", int(reg_idx), (double)floatReg); 111 112 return floatReg; 113 } 114 |
115 /** Reads a floating point register (double precision). */ |
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110 FloatReg readFloatReg(PhysRegIndex reg_idx) 111 { 112 // Remove the base Float reg dependency. 113 reg_idx = reg_idx - numPhysicalIntRegs; 114 115 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 116 | 116 FloatReg readFloatReg(PhysRegIndex reg_idx) 117 { 118 // Remove the base Float reg dependency. 119 reg_idx = reg_idx - numPhysicalIntRegs; 120 121 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 122 |
117 FloatReg floatReg = floatRegFile.readReg(reg_idx); | 123 FloatReg floatReg = floatRegFile[reg_idx].d; |
118 119 DPRINTF(IEW, "RegFile: Access to float register %i, has " 120 "data %8.8d\n", int(reg_idx), (double)floatReg); 121 122 return floatReg; 123 } 124 | 124 125 DPRINTF(IEW, "RegFile: Access to float register %i, has " 126 "data %8.8d\n", int(reg_idx), (double)floatReg); 127 128 return floatReg; 129 } 130 |
131 /** Reads a floating point register as an integer. */ |
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125 FloatRegBits readFloatRegBits(PhysRegIndex reg_idx, int width) 126 { 127 // Remove the base Float reg dependency. 128 reg_idx = reg_idx - numPhysicalIntRegs; 129 130 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 131 | 132 FloatRegBits readFloatRegBits(PhysRegIndex reg_idx, int width) 133 { 134 // Remove the base Float reg dependency. 135 reg_idx = reg_idx - numPhysicalIntRegs; 136 137 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 138 |
132 FloatRegBits floatRegBits = floatRegFile.readRegBits(reg_idx, width); | 139 FloatRegBits floatRegBits = floatRegFile[reg_idx].q; |
133 134 DPRINTF(IEW, "RegFile: Access to %d byte float register %i as int, " 135 "has data %lli\n", int(reg_idx), (uint64_t)floatRegBits); 136 137 return floatRegBits; 138 } 139 140 FloatRegBits readFloatRegBits(PhysRegIndex reg_idx) 141 { 142 // Remove the base Float reg dependency. 143 reg_idx = reg_idx - numPhysicalIntRegs; 144 145 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 146 | 140 141 DPRINTF(IEW, "RegFile: Access to %d byte float register %i as int, " 142 "has data %lli\n", int(reg_idx), (uint64_t)floatRegBits); 143 144 return floatRegBits; 145 } 146 147 FloatRegBits readFloatRegBits(PhysRegIndex reg_idx) 148 { 149 // Remove the base Float reg dependency. 150 reg_idx = reg_idx - numPhysicalIntRegs; 151 152 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 153 |
147 FloatRegBits floatRegBits = floatRegFile.readRegBits(reg_idx); | 154 FloatRegBits floatRegBits = floatRegFile[reg_idx].q; |
148 149 DPRINTF(IEW, "RegFile: Access to float register %i as int, " 150 "has data %lli\n", int(reg_idx), (uint64_t)floatRegBits); 151 152 return floatRegBits; 153 } 154 | 155 156 DPRINTF(IEW, "RegFile: Access to float register %i as int, " 157 "has data %lli\n", int(reg_idx), (uint64_t)floatRegBits); 158 159 return floatRegBits; 160 } 161 |
162 /** Sets an integer register to the given value. */ |
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155 void setIntReg(PhysRegIndex reg_idx, uint64_t val) 156 { 157 assert(reg_idx < numPhysicalIntRegs); 158 159 DPRINTF(IEW, "RegFile: Setting int register %i to %lli\n", 160 int(reg_idx), val); 161 | 163 void setIntReg(PhysRegIndex reg_idx, uint64_t val) 164 { 165 assert(reg_idx < numPhysicalIntRegs); 166 167 DPRINTF(IEW, "RegFile: Setting int register %i to %lli\n", 168 int(reg_idx), val); 169 |
162 intRegFile[reg_idx] = val; | 170 if (reg_idx != TheISA::ZeroReg) 171 intRegFile[reg_idx] = val; |
163 } 164 | 172 } 173 |
174 /** Sets a single precision floating point register to the given value. */ |
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165 void setFloatReg(PhysRegIndex reg_idx, FloatReg val, int width) 166 { 167 // Remove the base Float reg dependency. 168 reg_idx = reg_idx - numPhysicalIntRegs; 169 170 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 171 172 DPRINTF(IEW, "RegFile: Setting float register %i to %8.8d\n", 173 int(reg_idx), (double)val); 174 | 175 void setFloatReg(PhysRegIndex reg_idx, FloatReg val, int width) 176 { 177 // Remove the base Float reg dependency. 178 reg_idx = reg_idx - numPhysicalIntRegs; 179 180 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 181 182 DPRINTF(IEW, "RegFile: Setting float register %i to %8.8d\n", 183 int(reg_idx), (double)val); 184 |
175 floatRegFile.setReg(reg_idx, val, width); | 185 if (reg_idx != TheISA::ZeroReg) 186 floatRegFile[reg_idx].d = width; |
176 } 177 | 187 } 188 |
189 /** Sets a double precision floating point register to the given value. */ |
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178 void setFloatReg(PhysRegIndex reg_idx, FloatReg val) 179 { 180 // Remove the base Float reg dependency. 181 reg_idx = reg_idx - numPhysicalIntRegs; 182 183 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 184 185 DPRINTF(IEW, "RegFile: Setting float register %i to %8.8d\n", 186 int(reg_idx), (double)val); 187 | 190 void setFloatReg(PhysRegIndex reg_idx, FloatReg val) 191 { 192 // Remove the base Float reg dependency. 193 reg_idx = reg_idx - numPhysicalIntRegs; 194 195 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 196 197 DPRINTF(IEW, "RegFile: Setting float register %i to %8.8d\n", 198 int(reg_idx), (double)val); 199 |
188 floatRegFile.setReg(reg_idx, val); | 200 if (reg_idx != TheISA::ZeroReg) 201 floatRegFile[reg_idx].d = val; |
189 } 190 | 202 } 203 |
204 /** Sets a floating point register to the given integer value. */ |
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191 void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val, int width) 192 { 193 // Remove the base Float reg dependency. 194 reg_idx = reg_idx - numPhysicalIntRegs; 195 196 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 197 198 DPRINTF(IEW, "RegFile: Setting float register %i to %lli\n", 199 int(reg_idx), (uint64_t)val); 200 | 205 void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val, int width) 206 { 207 // Remove the base Float reg dependency. 208 reg_idx = reg_idx - numPhysicalIntRegs; 209 210 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 211 212 DPRINTF(IEW, "RegFile: Setting float register %i to %lli\n", 213 int(reg_idx), (uint64_t)val); 214 |
201 floatRegFile.setRegBits(reg_idx, val, width); | 215 floatRegFile[reg_idx].q = val; |
202 } 203 204 void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val) 205 { 206 // Remove the base Float reg dependency. 207 reg_idx = reg_idx - numPhysicalIntRegs; 208 209 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 210 211 DPRINTF(IEW, "RegFile: Setting float register %i to %lli\n", 212 int(reg_idx), (uint64_t)val); 213 | 216 } 217 218 void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val) 219 { 220 // Remove the base Float reg dependency. 221 reg_idx = reg_idx - numPhysicalIntRegs; 222 223 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 224 225 DPRINTF(IEW, "RegFile: Setting float register %i to %lli\n", 226 int(reg_idx), (uint64_t)val); 227 |
214 floatRegFile.setRegBits(reg_idx, val); | 228 floatRegFile[reg_idx].q = val; |
215 } 216 | 229 } 230 |
217 uint64_t readPC() | 231 MiscReg readMiscReg(int misc_reg, unsigned thread_id) |
218 { | 232 { |
219 return pc; | 233 return miscRegs[thread_id].readReg(misc_reg); |
220 } 221 | 234 } 235 |
222 void setPC(uint64_t val) | 236 MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault, 237 unsigned thread_id) |
223 { | 238 { |
224 pc = val; | 239 return miscRegs[thread_id].readRegWithEffect(misc_reg, fault, 240 cpu->xcBase(thread_id)); |
225 } 226 | 241 } 242 |
227 void setNextPC(uint64_t val) | 243 Fault setMiscReg(int misc_reg, const MiscReg &val, unsigned thread_id) |
228 { | 244 { |
229 npc = val; | 245 return miscRegs[thread_id].setReg(misc_reg, val); |
230 } 231 | 246 } 247 |
232 //Consider leaving this stuff and below in some implementation specific 233 //file as opposed to the general register file. Or have a derived class. 234 MiscReg readMiscReg(int misc_reg) | 248 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val, 249 unsigned thread_id) |
235 { | 250 { |
236 // Dummy function for now. 237 // @todo: Fix this once proxy XC is used. 238 return 0; | 251 return miscRegs[thread_id].setRegWithEffect(misc_reg, val, 252 cpu->xcBase(thread_id)); |
239 } 240 | 253 } 254 |
241 Fault setMiscReg(int misc_reg, const MiscReg &val) 242 { 243 // Dummy function for now. 244 // @todo: Fix this once proxy XC is used. 245 return NoFault; 246 } 247 | |
248#if FULL_SYSTEM 249 int readIntrFlag() { return intrflag; } | 255#if FULL_SYSTEM 256 int readIntrFlag() { return intrflag; } |
257 /** Sets an interrupt flag. */ |
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250 void setIntrFlag(int val) { intrflag = val; } 251#endif 252 | 258 void setIntrFlag(int val) { intrflag = val; } 259#endif 260 |
253 // These should be private eventually, but will be public for now 254 // so that I can hack around the initregs issue. | |
255 public: 256 /** (signed) integer register file. */ | 261 public: 262 /** (signed) integer register file. */ |
257 IntReg *intRegFile; | 263 std::vector<IntReg> intRegFile; |
258 259 /** Floating point register file. */ | 264 265 /** Floating point register file. */ |
260 FloatReg *floatRegFile; | 266 std::vector<PhysFloatReg> floatRegFile; |
261 262 /** Miscellaneous register file. */ | 267 268 /** Miscellaneous register file. */ |
263 MiscRegFile miscRegs; | 269 MiscRegFile miscRegs[Impl::MaxThreads]; |
264 | 270 |
265 /** Program counter. */ 266 Addr pc; 267 268 /** Next-cycle program counter. */ 269 Addr npc; 270 | |
271#if FULL_SYSTEM 272 private: | 271#if FULL_SYSTEM 272 private: |
273 // This is ISA specifc stuff; remove it eventually once ISAImpl is used 274// IntReg palregs[NumIntRegs]; // PAL shadow registers | |
275 int intrflag; // interrupt flag | 273 int intrflag; // interrupt flag |
276 bool pal_shadow; // using pal_shadow registers | |
277#endif 278 279 private: | 274#endif 275 276 private: |
277 /** CPU pointer. */ |
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280 FullCPU *cpu; 281 282 public: | 278 FullCPU *cpu; 279 280 public: |
281 /** Sets the CPU pointer. */ |
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283 void setCPU(FullCPU *cpu_ptr) { cpu = cpu_ptr; } 284 | 282 void setCPU(FullCPU *cpu_ptr) { cpu = cpu_ptr; } 283 |
284 /** Number of physical integer registers. */ |
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285 unsigned numPhysicalIntRegs; | 285 unsigned numPhysicalIntRegs; |
286 /** Number of physical floating point registers. */ |
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286 unsigned numPhysicalFloatRegs; 287}; 288 289template <class Impl> 290PhysRegFile<Impl>::PhysRegFile(unsigned _numPhysicalIntRegs, 291 unsigned _numPhysicalFloatRegs) 292 : numPhysicalIntRegs(_numPhysicalIntRegs), 293 numPhysicalFloatRegs(_numPhysicalFloatRegs) 294{ | 287 unsigned numPhysicalFloatRegs; 288}; 289 290template <class Impl> 291PhysRegFile<Impl>::PhysRegFile(unsigned _numPhysicalIntRegs, 292 unsigned _numPhysicalFloatRegs) 293 : numPhysicalIntRegs(_numPhysicalIntRegs), 294 numPhysicalFloatRegs(_numPhysicalFloatRegs) 295{ |
295 intRegFile = new IntReg[numPhysicalIntRegs]; 296 floatRegFile = new FloatReg[numPhysicalFloatRegs]; | 296 intRegFile.resize(numPhysicalIntRegs); 297 floatRegFile.resize(numPhysicalFloatRegs); |
297 | 298 |
298 memset(intRegFile, 0, sizeof(*intRegFile)); 299 memset(floatRegFile, 0, sizeof(*floatRegFile)); | 299 //memset(intRegFile, 0, sizeof(*intRegFile)); 300 //memset(floatRegFile, 0, sizeof(*floatRegFile)); |
300} 301 | 301} 302 |
302#endif // __CPU_O3_CPU_REGFILE_HH__ | 303#endif |