1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Gabe Black
30 */
31
32#ifndef __CPU_O3_REGFILE_HH__
33#define __CPU_O3_REGFILE_HH__
34
35#include "arch/isa_traits.hh"
36#include "arch/types.hh"
37#include "base/trace.hh"
38#include "config/full_system.hh"
39#include "cpu/o3/comm.hh"
40
41#if FULL_SYSTEM
42#include "arch/kernel_stats.hh"
43#endif
44
45#include <vector>
46
47/**
48 * Simple physical register file class.
49 * Right now this is specific to Alpha until we decide if/how to make things
50 * generic enough to support other ISAs.
51 */
52template <class Impl>
53class PhysRegFile
54{
55 protected:
56 typedef TheISA::IntReg IntReg;
57 typedef TheISA::FloatReg FloatReg;
58 typedef TheISA::FloatRegBits FloatRegBits;
59 typedef TheISA::MiscRegFile MiscRegFile;
60 typedef TheISA::MiscReg MiscReg;
61
62 typedef union {
63 FloatReg d;
64 FloatRegBits q;
65 } PhysFloatReg;
66
67 // Note that most of the definitions of the IntReg, FloatReg, etc. exist
68 // within the Impl/ISA class and not within this PhysRegFile class.
69
70 // Will make these registers public for now, but they probably should
71 // be private eventually with some accessor functions.
72 public:
73 typedef typename Impl::O3CPU O3CPU;
74
75 /**
76 * Constructs a physical register file with the specified amount of
77 * integer and floating point registers.
78 */
79 PhysRegFile(unsigned _numPhysicalIntRegs,
80 unsigned _numPhysicalFloatRegs);
81
82 //Everything below should be pretty well identical to the normal
83 //register file that exists within AlphaISA class.
84 //The duplication is unfortunate but it's better than having
85 //different ways to access certain registers.
86
87 /** Reads an integer register. */
88 uint64_t readIntReg(PhysRegIndex reg_idx)
89 {
90 assert(reg_idx < numPhysicalIntRegs);
91
92 DPRINTF(IEW, "RegFile: Access to int register %i, has data "
93 "%#x\n", int(reg_idx), intRegFile[reg_idx]);
94 return intRegFile[reg_idx];
95 }
96
97 FloatReg readFloatReg(PhysRegIndex reg_idx, int width)
98 {
99 // Remove the base Float reg dependency.
100 reg_idx = reg_idx - numPhysicalIntRegs;
101
102 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
103
104 FloatReg floatReg = floatRegFile[reg_idx].d;
105
106 DPRINTF(IEW, "RegFile: Access to %d byte float register %i, has "
107 "data %#x\n", int(reg_idx), floatRegFile[reg_idx].q);
108
109 return floatReg;
110 }
111
112 /** Reads a floating point register (double precision). */
113 FloatReg readFloatReg(PhysRegIndex reg_idx)
114 {
115 // Remove the base Float reg dependency.
116 reg_idx = reg_idx - numPhysicalIntRegs;
117
118 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
119
120 FloatReg floatReg = floatRegFile[reg_idx].d;
121
122 DPRINTF(IEW, "RegFile: Access to float register %i, has "
123 "data %#x\n", int(reg_idx), floatRegFile[reg_idx].q);
124
125 return floatReg;
126 }
127
128 /** Reads a floating point register as an integer. */
129 FloatRegBits readFloatRegBits(PhysRegIndex reg_idx, int width)
130 {
131 // Remove the base Float reg dependency.
132 reg_idx = reg_idx - numPhysicalIntRegs;
133
134 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
135
136 FloatRegBits floatRegBits = floatRegFile[reg_idx].q;
137
138 DPRINTF(IEW, "RegFile: Access to float register %i as int, "
139 "has data %#x\n", int(reg_idx), (uint64_t)floatRegBits);
140
141 return floatRegBits;
142 }
143
144 FloatRegBits readFloatRegBits(PhysRegIndex reg_idx)
145 {
146 // Remove the base Float reg dependency.
147 reg_idx = reg_idx - numPhysicalIntRegs;
148
149 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
150
151 FloatRegBits floatRegBits = floatRegFile[reg_idx].q;
152
153 DPRINTF(IEW, "RegFile: Access to float register %i as int, "
154 "has data %#x\n", int(reg_idx), (uint64_t)floatRegBits);
155
156 return floatRegBits;
157 }
158
159 /** Sets an integer register to the given value. */
160 void setIntReg(PhysRegIndex reg_idx, uint64_t val)
161 {
162 assert(reg_idx < numPhysicalIntRegs);
163
164 DPRINTF(IEW, "RegFile: Setting int register %i to %#x\n",
165 int(reg_idx), val);
166
167 if (reg_idx != TheISA::ZeroReg)
168 intRegFile[reg_idx] = val;
169 }
170
171 /** Sets a single precision floating point register to the given value. */
172 void setFloatReg(PhysRegIndex reg_idx, FloatReg val, int width)
173 {
174 // Remove the base Float reg dependency.
175 reg_idx = reg_idx - numPhysicalIntRegs;
176
177 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
178
179 DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
180 int(reg_idx), (uint64_t)val);
181
182 if (reg_idx != TheISA::ZeroReg)
183 floatRegFile[reg_idx].d = val;
184 }
185
186 /** Sets a double precision floating point register to the given value. */
187 void setFloatReg(PhysRegIndex reg_idx, FloatReg val)
188 {
189 // Remove the base Float reg dependency.
190 reg_idx = reg_idx - numPhysicalIntRegs;
191
192 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
193
194 DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
195 int(reg_idx), (uint64_t)val);
196
197 if (reg_idx != TheISA::ZeroReg)
198 floatRegFile[reg_idx].d = val;
199 }
200
201 /** Sets a floating point register to the given integer value. */
202 void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val, int width)
203 {
204 // Remove the base Float reg dependency.
205 reg_idx = reg_idx - numPhysicalIntRegs;
206
207 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
208
209 DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
210 int(reg_idx), (uint64_t)val);
211
212 floatRegFile[reg_idx].q = val;
213 }
214
215 void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val)
216 {
217 // Remove the base Float reg dependency.
218 reg_idx = reg_idx - numPhysicalIntRegs;
219
220 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
221
222 DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
223 int(reg_idx), (uint64_t)val);
224
225 floatRegFile[reg_idx].q = val;
226 }
227
|
228 MiscReg readMiscReg(int misc_reg, unsigned thread_id)
|
| 228 MiscReg readMiscRegNoEffect(int misc_reg, unsigned thread_id) |
229 {
|
230 return miscRegs[thread_id].readReg(misc_reg);
|
| 230 return miscRegs[thread_id].readRegNoEffect(misc_reg); |
231 }
232
|
233 MiscReg readMiscRegWithEffect(int misc_reg, unsigned thread_id)
|
| 233 MiscReg readMiscReg(int misc_reg, unsigned thread_id) |
234 {
|
235 return miscRegs[thread_id].readRegWithEffect(misc_reg,
|
| 235 return miscRegs[thread_id].readReg(misc_reg, |
236 cpu->tcBase(thread_id));
237 }
238
|
239 void setMiscReg(int misc_reg, const MiscReg &val, unsigned thread_id)
|
| 239 void setMiscRegNoEffect(int misc_reg, const MiscReg &val, unsigned thread_id) |
240 {
|
241 miscRegs[thread_id].setReg(misc_reg, val);
|
| 241 miscRegs[thread_id].setRegNoEffect(misc_reg, val); |
242 }
243
|
244 void setMiscRegWithEffect(int misc_reg, const MiscReg &val,
|
| 244 void setMiscReg(int misc_reg, const MiscReg &val, |
245 unsigned thread_id)
246 {
|
247 miscRegs[thread_id].setRegWithEffect(misc_reg, val,
|
| 247 miscRegs[thread_id].setReg(misc_reg, val, |
248 cpu->tcBase(thread_id));
249 }
250
251 public:
252 /** (signed) integer register file. */
253 IntReg *intRegFile;
254
255 /** Floating point register file. */
256 PhysFloatReg *floatRegFile;
257
258 /** Miscellaneous register file. */
259 MiscRegFile miscRegs[Impl::MaxThreads];
260
261#if FULL_SYSTEM
262 private:
263 int intrflag; // interrupt flag
264#endif
265
266 private:
267 /** CPU pointer. */
268 O3CPU *cpu;
269
270 public:
271 /** Sets the CPU pointer. */
272 void setCPU(O3CPU *cpu_ptr) { cpu = cpu_ptr; }
273
274 /** Number of physical integer registers. */
275 unsigned numPhysicalIntRegs;
276 /** Number of physical floating point registers. */
277 unsigned numPhysicalFloatRegs;
278};
279
280template <class Impl>
281PhysRegFile<Impl>::PhysRegFile(unsigned _numPhysicalIntRegs,
282 unsigned _numPhysicalFloatRegs)
283 : numPhysicalIntRegs(_numPhysicalIntRegs),
284 numPhysicalFloatRegs(_numPhysicalFloatRegs)
285{
286 intRegFile = new IntReg[numPhysicalIntRegs];
287 floatRegFile = new PhysFloatReg[numPhysicalFloatRegs];
288
289 for (int i = 0; i < Impl::MaxThreads; ++i) {
290 miscRegs[i].clear();
291 }
292
293 memset(intRegFile, 0, sizeof(IntReg) * numPhysicalIntRegs);
294 memset(floatRegFile, 0, sizeof(PhysFloatReg) * numPhysicalFloatRegs);
295}
296
297#endif
|