1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 10 unchanged lines hidden (view full) --- 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 */ 28 |
29#ifndef __CPU_O3_REGFILE_HH__ 30#define __CPU_O3_REGFILE_HH__ |
31 |
32#include "arch/isa_traits.hh" 33#include "arch/faults.hh" |
34#include "arch/types.hh" |
35#include "base/trace.hh" 36#include "config/full_system.hh" 37#include "cpu/o3/comm.hh" 38 39#if FULL_SYSTEM 40#include "kern/kernel_stats.hh" 41 42#endif 43 |
44#include <vector> |
45 |
46/** 47 * Simple physical register file class. 48 * Right now this is specific to Alpha until we decide if/how to make things 49 * generic enough to support other ISAs. 50 */ |
51template <class Impl> 52class PhysRegFile 53{ 54 protected: 55 typedef TheISA::IntReg IntReg; 56 typedef TheISA::FloatReg FloatReg; |
57 typedef TheISA::FloatRegBits FloatRegBits; |
58 typedef TheISA::MiscRegFile MiscRegFile; 59 typedef TheISA::MiscReg MiscReg; 60 |
61 typedef union { 62 FloatReg d; 63 FloatRegBits q; 64 } PhysFloatReg; |
65 |
66 // Note that most of the definitions of the IntReg, FloatReg, etc. exist 67 // within the Impl/ISA class and not within this PhysRegFile class. |
68 |
69 // Will make these registers public for now, but they probably should 70 // be private eventually with some accessor functions. |
71 public: 72 typedef typename Impl::FullCPU FullCPU; 73 |
74 /** 75 * Constructs a physical register file with the specified amount of 76 * integer and floating point registers. 77 */ |
78 PhysRegFile(unsigned _numPhysicalIntRegs, 79 unsigned _numPhysicalFloatRegs); 80 81 //Everything below should be pretty well identical to the normal 82 //register file that exists within AlphaISA class. 83 //The duplication is unfortunate but it's better than having 84 //different ways to access certain registers. 85 86 //Add these in later when everything else is in place 87// void serialize(std::ostream &os); 88// void unserialize(Checkpoint *cp, const std::string §ion); 89 |
90 /** Reads an integer register. */ |
91 uint64_t readIntReg(PhysRegIndex reg_idx) 92 { 93 assert(reg_idx < numPhysicalIntRegs); 94 95 DPRINTF(IEW, "RegFile: Access to int register %i, has data " 96 "%i\n", int(reg_idx), intRegFile[reg_idx]); 97 return intRegFile[reg_idx]; 98 } 99 100 FloatReg readFloatReg(PhysRegIndex reg_idx, int width) 101 { 102 // Remove the base Float reg dependency. 103 reg_idx = reg_idx - numPhysicalIntRegs; 104 105 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 106 |
107 FloatReg floatReg = floatRegFile[reg_idx].d; |
108 109 DPRINTF(IEW, "RegFile: Access to %d byte float register %i, has " 110 "data %8.8d\n", int(reg_idx), (double)floatReg); 111 112 return floatReg; 113 } 114 |
115 /** Reads a floating point register (double precision). */ |
116 FloatReg readFloatReg(PhysRegIndex reg_idx) 117 { 118 // Remove the base Float reg dependency. 119 reg_idx = reg_idx - numPhysicalIntRegs; 120 121 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 122 |
123 FloatReg floatReg = floatRegFile[reg_idx].d; |
124 125 DPRINTF(IEW, "RegFile: Access to float register %i, has " 126 "data %8.8d\n", int(reg_idx), (double)floatReg); 127 128 return floatReg; 129 } 130 |
131 /** Reads a floating point register as an integer. */ |
132 FloatRegBits readFloatRegBits(PhysRegIndex reg_idx, int width) 133 { 134 // Remove the base Float reg dependency. 135 reg_idx = reg_idx - numPhysicalIntRegs; 136 137 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 138 |
139 FloatRegBits floatRegBits = floatRegFile[reg_idx].q; |
140 141 DPRINTF(IEW, "RegFile: Access to %d byte float register %i as int, " 142 "has data %lli\n", int(reg_idx), (uint64_t)floatRegBits); 143 144 return floatRegBits; 145 } 146 147 FloatRegBits readFloatRegBits(PhysRegIndex reg_idx) 148 { 149 // Remove the base Float reg dependency. 150 reg_idx = reg_idx - numPhysicalIntRegs; 151 152 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 153 |
154 FloatRegBits floatRegBits = floatRegFile[reg_idx].q; |
155 156 DPRINTF(IEW, "RegFile: Access to float register %i as int, " 157 "has data %lli\n", int(reg_idx), (uint64_t)floatRegBits); 158 159 return floatRegBits; 160 } 161 |
162 /** Sets an integer register to the given value. */ |
163 void setIntReg(PhysRegIndex reg_idx, uint64_t val) 164 { 165 assert(reg_idx < numPhysicalIntRegs); 166 167 DPRINTF(IEW, "RegFile: Setting int register %i to %lli\n", 168 int(reg_idx), val); 169 |
170 if (reg_idx != TheISA::ZeroReg) 171 intRegFile[reg_idx] = val; |
172 } 173 |
174 /** Sets a single precision floating point register to the given value. */ |
175 void setFloatReg(PhysRegIndex reg_idx, FloatReg val, int width) 176 { 177 // Remove the base Float reg dependency. 178 reg_idx = reg_idx - numPhysicalIntRegs; 179 180 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 181 182 DPRINTF(IEW, "RegFile: Setting float register %i to %8.8d\n", 183 int(reg_idx), (double)val); 184 |
185 if (reg_idx != TheISA::ZeroReg) 186 floatRegFile[reg_idx].d = width; |
187 } 188 |
189 /** Sets a double precision floating point register to the given value. */ |
190 void setFloatReg(PhysRegIndex reg_idx, FloatReg val) 191 { 192 // Remove the base Float reg dependency. 193 reg_idx = reg_idx - numPhysicalIntRegs; 194 195 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 196 197 DPRINTF(IEW, "RegFile: Setting float register %i to %8.8d\n", 198 int(reg_idx), (double)val); 199 |
200 if (reg_idx != TheISA::ZeroReg) 201 floatRegFile[reg_idx].d = val; |
202 } 203 |
204 /** Sets a floating point register to the given integer value. */ |
205 void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val, int width) 206 { 207 // Remove the base Float reg dependency. 208 reg_idx = reg_idx - numPhysicalIntRegs; 209 210 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 211 212 DPRINTF(IEW, "RegFile: Setting float register %i to %lli\n", 213 int(reg_idx), (uint64_t)val); 214 |
215 floatRegFile[reg_idx].q = val; |
216 } 217 218 void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val) 219 { 220 // Remove the base Float reg dependency. 221 reg_idx = reg_idx - numPhysicalIntRegs; 222 223 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 224 225 DPRINTF(IEW, "RegFile: Setting float register %i to %lli\n", 226 int(reg_idx), (uint64_t)val); 227 |
228 floatRegFile[reg_idx].q = val; |
229 } 230 |
231 MiscReg readMiscReg(int misc_reg, unsigned thread_id) |
232 { |
233 return miscRegs[thread_id].readReg(misc_reg); |
234 } 235 |
236 MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault, 237 unsigned thread_id) |
238 { |
239 return miscRegs[thread_id].readRegWithEffect(misc_reg, fault, 240 cpu->xcBase(thread_id)); |
241 } 242 |
243 Fault setMiscReg(int misc_reg, const MiscReg &val, unsigned thread_id) |
244 { |
245 return miscRegs[thread_id].setReg(misc_reg, val); |
246 } 247 |
248 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val, 249 unsigned thread_id) |
250 { |
251 return miscRegs[thread_id].setRegWithEffect(misc_reg, val, 252 cpu->xcBase(thread_id)); |
253 } 254 |
255#if FULL_SYSTEM 256 int readIntrFlag() { return intrflag; } |
257 /** Sets an interrupt flag. */ |
258 void setIntrFlag(int val) { intrflag = val; } 259#endif 260 |
261 public: 262 /** (signed) integer register file. */ |
263 std::vector<IntReg> intRegFile; |
264 265 /** Floating point register file. */ |
266 std::vector<PhysFloatReg> floatRegFile; |
267 268 /** Miscellaneous register file. */ |
269 MiscRegFile miscRegs[Impl::MaxThreads]; |
270 |
271#if FULL_SYSTEM 272 private: |
273 int intrflag; // interrupt flag |
274#endif 275 276 private: |
277 /** CPU pointer. */ |
278 FullCPU *cpu; 279 280 public: |
281 /** Sets the CPU pointer. */ |
282 void setCPU(FullCPU *cpu_ptr) { cpu = cpu_ptr; } 283 |
284 /** Number of physical integer registers. */ |
285 unsigned numPhysicalIntRegs; |
286 /** Number of physical floating point registers. */ |
287 unsigned numPhysicalFloatRegs; 288}; 289 290template <class Impl> 291PhysRegFile<Impl>::PhysRegFile(unsigned _numPhysicalIntRegs, 292 unsigned _numPhysicalFloatRegs) 293 : numPhysicalIntRegs(_numPhysicalIntRegs), 294 numPhysicalFloatRegs(_numPhysicalFloatRegs) 295{ |
296 intRegFile.resize(numPhysicalIntRegs); 297 floatRegFile.resize(numPhysicalFloatRegs); |
298 |
299 //memset(intRegFile, 0, sizeof(*intRegFile)); 300 //memset(floatRegFile, 0, sizeof(*floatRegFile)); |
301} 302 |
303#endif |