1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 121 unchanged lines hidden (view full) --- 130 } 131 132 /** Reads an integer register. */ 133 uint64_t readIntReg(PhysRegIdPtr phys_reg) const 134 { 135 assert(phys_reg->isIntPhysReg()); 136 137 DPRINTF(IEW, "RegFile: Access to int register %i, has data " |
138 "%#x\n", phys_reg->index(), intRegFile[phys_reg->index()]); 139 return intRegFile[phys_reg->index()]; |
140 } 141 142 /** Reads a floating point register (double precision). */ 143 FloatReg readFloatReg(PhysRegIdPtr phys_reg) const 144 { 145 assert(phys_reg->isFloatPhysReg()); 146 147 DPRINTF(IEW, "RegFile: Access to float register %i, has " |
148 "data %#x\n", phys_reg->index(), 149 floatRegFile[phys_reg->index()].q); |
150 |
151 return floatRegFile[phys_reg->index()].d; |
152 } 153 154 FloatRegBits readFloatRegBits(PhysRegIdPtr phys_reg) const 155 { 156 assert(phys_reg->isFloatPhysReg()); 157 |
158 FloatRegBits floatRegBits = floatRegFile[phys_reg->index()].q; |
159 160 DPRINTF(IEW, "RegFile: Access to float register %i as int, " |
161 "has data %#x\n", phys_reg->index(), |
162 (uint64_t)floatRegBits); 163 164 return floatRegBits; 165 } 166 167 /** Reads a condition-code register. */ 168 CCReg readCCReg(PhysRegIdPtr phys_reg) 169 { 170 assert(phys_reg->isCCPhysReg()); 171 172 DPRINTF(IEW, "RegFile: Access to cc register %i, has " |
173 "data %#x\n", phys_reg->index(), 174 ccRegFile[phys_reg->index()]); |
175 |
176 return ccRegFile[phys_reg->index()]; |
177 } 178 179 /** Sets an integer register to the given value. */ 180 void setIntReg(PhysRegIdPtr phys_reg, uint64_t val) 181 { 182 assert(phys_reg->isIntPhysReg()); 183 184 DPRINTF(IEW, "RegFile: Setting int register %i to %#x\n", |
185 phys_reg->index(), val); |
186 187 if (!phys_reg->isZeroReg()) |
188 intRegFile[phys_reg->index()] = val; |
189 } 190 191 /** Sets a double precision floating point register to the given value. */ 192 void setFloatReg(PhysRegIdPtr phys_reg, FloatReg val) 193 { 194 assert(phys_reg->isFloatPhysReg()); 195 196 DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n", |
197 phys_reg->index(), (uint64_t)val); |
198 199 if (!phys_reg->isZeroReg()) |
200 floatRegFile[phys_reg->index()].d = val; |
201 } 202 203 void setFloatRegBits(PhysRegIdPtr phys_reg, FloatRegBits val) 204 { 205 assert(phys_reg->isFloatPhysReg()); 206 207 DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n", |
208 phys_reg->index(), (uint64_t)val); |
209 |
210 floatRegFile[phys_reg->index()].q = val; |
211 } 212 213 /** Sets a condition-code register to the given value. */ 214 void setCCReg(PhysRegIdPtr phys_reg, CCReg val) 215 { 216 assert(phys_reg->isCCPhysReg()); 217 218 DPRINTF(IEW, "RegFile: Setting cc register %i to %#x\n", |
219 phys_reg->index(), (uint64_t)val); |
220 |
221 ccRegFile[phys_reg->index()] = val; |
222 } 223}; 224 225 226#endif //__CPU_O3_REGFILE_HH__ |