26a27,29
> *
> * Authors: Kevin Lim
> * Gabe Black
29,30c32,33
< #ifndef __CPU_O3_REGFILE_HH__
< #define __CPU_O3_REGFILE_HH__
---
> #ifndef __CPU_O3_CPU_REGFILE_HH__
> #define __CPU_O3_CPU_REGFILE_HH__
31a35,36
> // @todo: Destructor
>
43c48,51
< #include <vector>
---
> // This really only depends on the ISA, and not the Impl. It might be nicer
> // to see if I can make it depend on nothing...
> // Things that are in the ifdef FULL_SYSTEM are pretty dependent on the ISA,
> // and should go in the AlphaFullCPU.
45,50d52
< /**
< * Simple physical register file class.
< * This really only depends on the ISA, and not the Impl. Things that are
< * in the ifdef FULL_SYSTEM are pretty dependent on the ISA, and probably
< * should go in the AlphaFullCPU.
< */
59,60d60
< // Note that most of the definitions of the IntReg, FloatReg, etc. exist
< // within the Impl/ISA class and not within this PhysRegFile class.
62,63c62,70
< // Will make these registers public for now, but they probably should
< // be private eventually with some accessor functions.
---
> //Note that most of the definitions of the IntReg, FloatReg, etc. exist
> //within the Impl/ISA class and not within this PhysRegFile class.
>
> //Will need some way to allow stuff like swap_palshadow to access the
> //correct registers. Might require code changes to swap_palshadow and
> //other execution contexts.
>
> //Will make these registers public for now, but they probably should
> //be private eventually with some accessor functions.
67,70d73
< /**
< * Constructs a physical register file with the specified amount of
< * integer and floating point registers.
< */
83d85
< /** Reads an integer register. */
108d109
< /** Reads a floating point register (double precision). */
124d124
< /** Reads a floating point register as an integer. */
155d154
< /** Sets an integer register to the given value. */
163,164c162
< if (reg_idx != TheISA::ZeroReg)
< intRegFile[reg_idx] = val;
---
> intRegFile[reg_idx] = val;
167d164
< /** Sets a single precision floating point register to the given value. */
178,179c175
< if (reg_idx != TheISA::ZeroReg)
< floatRegFile.setReg(reg_idx, val, width);
---
> floatRegFile.setReg(reg_idx, val, width);
182d177
< /** Sets a double precision floating point register to the given value. */
193,194c188
< if (reg_idx != TheISA::ZeroReg)
< floatRegFile.setReg(reg_idx, val);
---
> floatRegFile.setReg(reg_idx, val);
197d190
< /** Sets a floating point register to the given integer value. */
219a213,214
>
> floatRegFile.setRegBits(reg_idx, val);
222,223c217
< MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault,
< unsigned thread_id)
---
> uint64_t readPC()
225,226c219
< return miscRegs[thread_id].readRegWithEffect(misc_reg, fault,
< cpu->xcBase(thread_id));
---
> return pc;
229c222
< Fault setMiscReg(int misc_reg, const MiscReg &val, unsigned thread_id)
---
> void setPC(uint64_t val)
231c224
< return miscRegs[thread_id].setReg(misc_reg, val);
---
> pc = val;
234,235c227
< Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val,
< unsigned thread_id)
---
> void setNextPC(uint64_t val)
237,238c229
< return miscRegs[thread_id].setRegWithEffect(misc_reg, val,
< cpu->xcBase(thread_id));
---
> npc = val;
240a232,247
> //Consider leaving this stuff and below in some implementation specific
> //file as opposed to the general register file. Or have a derived class.
> MiscReg readMiscReg(int misc_reg)
> {
> // Dummy function for now.
> // @todo: Fix this once proxy XC is used.
> return 0;
> }
>
> Fault setMiscReg(int misc_reg, const MiscReg &val)
> {
> // Dummy function for now.
> // @todo: Fix this once proxy XC is used.
> return NoFault;
> }
>
243d249
< /** Sets an interrupt flag. */
246a253,254
> // These should be private eventually, but will be public for now
> // so that I can hack around the initregs issue.
249c257
< std::vector<IntReg> intRegFile;
---
> IntReg *intRegFile;
252c260
< std::vector<FloatReg> floatRegFile;
---
> FloatReg *floatRegFile;
255c263
< MiscRegFile miscRegs[Impl::MaxThreads];
---
> MiscRegFile miscRegs;
256a265,270
> /** Program counter. */
> Addr pc;
>
> /** Next-cycle program counter. */
> Addr npc;
>
258a273,274
> // This is ISA specifc stuff; remove it eventually once ISAImpl is used
> // IntReg palregs[NumIntRegs]; // PAL shadow registers
259a276
> bool pal_shadow; // using pal_shadow registers
263d279
< /** CPU pointer. */
267d282
< /** Sets the CPU pointer. */
270d284
< /** Number of physical integer registers. */
272d285
< /** Number of physical floating point registers. */
282,283c295,296
< intRegFile.resize(numPhysicalIntRegs);
< floatRegFile.resize(numPhysicalFloatRegs);
---
> intRegFile = new IntReg[numPhysicalIntRegs];
> floatRegFile = new FloatReg[numPhysicalFloatRegs];
285,286c298,299
< //memset(intRegFile, 0, sizeof(*intRegFile));
< //memset(floatRegFile, 0, sizeof(*floatRegFile));
---
> memset(intRegFile, 0, sizeof(*intRegFile));
> memset(floatRegFile, 0, sizeof(*floatRegFile));
289c302
< #endif
---
> #endif // __CPU_O3_CPU_REGFILE_HH__
> *
> * Authors: Kevin Lim
> * Gabe Black
29,30c32,33
< #ifndef __CPU_O3_REGFILE_HH__
< #define __CPU_O3_REGFILE_HH__
---
> #ifndef __CPU_O3_CPU_REGFILE_HH__
> #define __CPU_O3_CPU_REGFILE_HH__
31a35,36
> // @todo: Destructor
>
43c48,51
< #include <vector>
---
> // This really only depends on the ISA, and not the Impl. It might be nicer
> // to see if I can make it depend on nothing...
> // Things that are in the ifdef FULL_SYSTEM are pretty dependent on the ISA,
> // and should go in the AlphaFullCPU.
45,50d52
< /**
< * Simple physical register file class.
< * This really only depends on the ISA, and not the Impl. Things that are
< * in the ifdef FULL_SYSTEM are pretty dependent on the ISA, and probably
< * should go in the AlphaFullCPU.
< */
59,60d60
< // Note that most of the definitions of the IntReg, FloatReg, etc. exist
< // within the Impl/ISA class and not within this PhysRegFile class.
62,63c62,70
< // Will make these registers public for now, but they probably should
< // be private eventually with some accessor functions.
---
> //Note that most of the definitions of the IntReg, FloatReg, etc. exist
> //within the Impl/ISA class and not within this PhysRegFile class.
>
> //Will need some way to allow stuff like swap_palshadow to access the
> //correct registers. Might require code changes to swap_palshadow and
> //other execution contexts.
>
> //Will make these registers public for now, but they probably should
> //be private eventually with some accessor functions.
67,70d73
< /**
< * Constructs a physical register file with the specified amount of
< * integer and floating point registers.
< */
83d85
< /** Reads an integer register. */
108d109
< /** Reads a floating point register (double precision). */
124d124
< /** Reads a floating point register as an integer. */
155d154
< /** Sets an integer register to the given value. */
163,164c162
< if (reg_idx != TheISA::ZeroReg)
< intRegFile[reg_idx] = val;
---
> intRegFile[reg_idx] = val;
167d164
< /** Sets a single precision floating point register to the given value. */
178,179c175
< if (reg_idx != TheISA::ZeroReg)
< floatRegFile.setReg(reg_idx, val, width);
---
> floatRegFile.setReg(reg_idx, val, width);
182d177
< /** Sets a double precision floating point register to the given value. */
193,194c188
< if (reg_idx != TheISA::ZeroReg)
< floatRegFile.setReg(reg_idx, val);
---
> floatRegFile.setReg(reg_idx, val);
197d190
< /** Sets a floating point register to the given integer value. */
219a213,214
>
> floatRegFile.setRegBits(reg_idx, val);
222,223c217
< MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault,
< unsigned thread_id)
---
> uint64_t readPC()
225,226c219
< return miscRegs[thread_id].readRegWithEffect(misc_reg, fault,
< cpu->xcBase(thread_id));
---
> return pc;
229c222
< Fault setMiscReg(int misc_reg, const MiscReg &val, unsigned thread_id)
---
> void setPC(uint64_t val)
231c224
< return miscRegs[thread_id].setReg(misc_reg, val);
---
> pc = val;
234,235c227
< Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val,
< unsigned thread_id)
---
> void setNextPC(uint64_t val)
237,238c229
< return miscRegs[thread_id].setRegWithEffect(misc_reg, val,
< cpu->xcBase(thread_id));
---
> npc = val;
240a232,247
> //Consider leaving this stuff and below in some implementation specific
> //file as opposed to the general register file. Or have a derived class.
> MiscReg readMiscReg(int misc_reg)
> {
> // Dummy function for now.
> // @todo: Fix this once proxy XC is used.
> return 0;
> }
>
> Fault setMiscReg(int misc_reg, const MiscReg &val)
> {
> // Dummy function for now.
> // @todo: Fix this once proxy XC is used.
> return NoFault;
> }
>
243d249
< /** Sets an interrupt flag. */
246a253,254
> // These should be private eventually, but will be public for now
> // so that I can hack around the initregs issue.
249c257
< std::vector<IntReg> intRegFile;
---
> IntReg *intRegFile;
252c260
< std::vector<FloatReg> floatRegFile;
---
> FloatReg *floatRegFile;
255c263
< MiscRegFile miscRegs[Impl::MaxThreads];
---
> MiscRegFile miscRegs;
256a265,270
> /** Program counter. */
> Addr pc;
>
> /** Next-cycle program counter. */
> Addr npc;
>
258a273,274
> // This is ISA specifc stuff; remove it eventually once ISAImpl is used
> // IntReg palregs[NumIntRegs]; // PAL shadow registers
259a276
> bool pal_shadow; // using pal_shadow registers
263d279
< /** CPU pointer. */
267d282
< /** Sets the CPU pointer. */
270d284
< /** Number of physical integer registers. */
272d285
< /** Number of physical floating point registers. */
282,283c295,296
< intRegFile.resize(numPhysicalIntRegs);
< floatRegFile.resize(numPhysicalFloatRegs);
---
> intRegFile = new IntReg[numPhysicalIntRegs];
> floatRegFile = new FloatReg[numPhysicalFloatRegs];
285,286c298,299
< //memset(intRegFile, 0, sizeof(*intRegFile));
< //memset(floatRegFile, 0, sizeof(*floatRegFile));
---
> memset(intRegFile, 0, sizeof(*intRegFile));
> memset(floatRegFile, 0, sizeof(*floatRegFile));
289c302
< #endif
---
> #endif // __CPU_O3_CPU_REGFILE_HH__