27,29d26
< *
< * Authors: Kevin Lim
< * Gabe Black
32,33c29,30
< #ifndef __CPU_O3_CPU_REGFILE_HH__
< #define __CPU_O3_CPU_REGFILE_HH__
---
> #ifndef __CPU_O3_REGFILE_HH__
> #define __CPU_O3_REGFILE_HH__
35,36d31
< // @todo: Destructor
<
38a34
> #include "arch/types.hh"
48,51c44
< // This really only depends on the ISA, and not the Impl. It might be nicer
< // to see if I can make it depend on nothing...
< // Things that are in the ifdef FULL_SYSTEM are pretty dependent on the ISA,
< // and should go in the AlphaFullCPU.
---
> #include <vector>
52a46,50
> /**
> * Simple physical register file class.
> * Right now this is specific to Alpha until we decide if/how to make things
> * generic enough to support other ISAs.
> */
58a57
> typedef TheISA::FloatRegBits FloatRegBits;
62,63c61,64
< //Note that most of the definitions of the IntReg, FloatReg, etc. exist
< //within the Impl/ISA class and not within this PhysRegFile class.
---
> typedef union {
> FloatReg d;
> FloatRegBits q;
> } PhysFloatReg;
65,67c66,67
< //Will need some way to allow stuff like swap_palshadow to access the
< //correct registers. Might require code changes to swap_palshadow and
< //other execution contexts.
---
> // Note that most of the definitions of the IntReg, FloatReg, etc. exist
> // within the Impl/ISA class and not within this PhysRegFile class.
69,70c69,70
< //Will make these registers public for now, but they probably should
< //be private eventually with some accessor functions.
---
> // Will make these registers public for now, but they probably should
> // be private eventually with some accessor functions.
73a74,77
> /**
> * Constructs a physical register file with the specified amount of
> * integer and floating point registers.
> */
85a90
> /** Reads an integer register. */
102c107
< FloatReg floatReg = floatRegFile.readReg(reg_idx, width);
---
> FloatReg floatReg = floatRegFile[reg_idx].d;
109a115
> /** Reads a floating point register (double precision). */
117c123
< FloatReg floatReg = floatRegFile.readReg(reg_idx);
---
> FloatReg floatReg = floatRegFile[reg_idx].d;
124a131
> /** Reads a floating point register as an integer. */
132c139
< FloatRegBits floatRegBits = floatRegFile.readRegBits(reg_idx, width);
---
> FloatRegBits floatRegBits = floatRegFile[reg_idx].q;
147c154
< FloatRegBits floatRegBits = floatRegFile.readRegBits(reg_idx);
---
> FloatRegBits floatRegBits = floatRegFile[reg_idx].q;
154a162
> /** Sets an integer register to the given value. */
162c170,171
< intRegFile[reg_idx] = val;
---
> if (reg_idx != TheISA::ZeroReg)
> intRegFile[reg_idx] = val;
164a174
> /** Sets a single precision floating point register to the given value. */
175c185,186
< floatRegFile.setReg(reg_idx, val, width);
---
> if (reg_idx != TheISA::ZeroReg)
> floatRegFile[reg_idx].d = width;
177a189
> /** Sets a double precision floating point register to the given value. */
188c200,201
< floatRegFile.setReg(reg_idx, val);
---
> if (reg_idx != TheISA::ZeroReg)
> floatRegFile[reg_idx].d = val;
190a204
> /** Sets a floating point register to the given integer value. */
201c215
< floatRegFile.setRegBits(reg_idx, val, width);
---
> floatRegFile[reg_idx].q = val;
214c228
< floatRegFile.setRegBits(reg_idx, val);
---
> floatRegFile[reg_idx].q = val;
217c231
< uint64_t readPC()
---
> MiscReg readMiscReg(int misc_reg, unsigned thread_id)
219c233
< return pc;
---
> return miscRegs[thread_id].readReg(misc_reg);
222c236,237
< void setPC(uint64_t val)
---
> MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault,
> unsigned thread_id)
224c239,240
< pc = val;
---
> return miscRegs[thread_id].readRegWithEffect(misc_reg, fault,
> cpu->xcBase(thread_id));
227c243
< void setNextPC(uint64_t val)
---
> Fault setMiscReg(int misc_reg, const MiscReg &val, unsigned thread_id)
229c245
< npc = val;
---
> return miscRegs[thread_id].setReg(misc_reg, val);
232,234c248,249
< //Consider leaving this stuff and below in some implementation specific
< //file as opposed to the general register file. Or have a derived class.
< MiscReg readMiscReg(int misc_reg)
---
> Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val,
> unsigned thread_id)
236,238c251,252
< // Dummy function for now.
< // @todo: Fix this once proxy XC is used.
< return 0;
---
> return miscRegs[thread_id].setRegWithEffect(misc_reg, val,
> cpu->xcBase(thread_id));
241,247d254
< Fault setMiscReg(int misc_reg, const MiscReg &val)
< {
< // Dummy function for now.
< // @todo: Fix this once proxy XC is used.
< return NoFault;
< }
<
249a257
> /** Sets an interrupt flag. */
253,254d260
< // These should be private eventually, but will be public for now
< // so that I can hack around the initregs issue.
257c263
< IntReg *intRegFile;
---
> std::vector<IntReg> intRegFile;
260c266
< FloatReg *floatRegFile;
---
> std::vector<PhysFloatReg> floatRegFile;
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< MiscRegFile miscRegs;
---
> MiscRegFile miscRegs[Impl::MaxThreads];
265,270d270
< /** Program counter. */
< Addr pc;
<
< /** Next-cycle program counter. */
< Addr npc;
<
273,274d272
< // This is ISA specifc stuff; remove it eventually once ISAImpl is used
< // IntReg palregs[NumIntRegs]; // PAL shadow registers
276d273
< bool pal_shadow; // using pal_shadow registers
279a277
> /** CPU pointer. */
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> /** Sets the CPU pointer. */
284a284
> /** Number of physical integer registers. */
285a286
> /** Number of physical floating point registers. */
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< intRegFile = new IntReg[numPhysicalIntRegs];
< floatRegFile = new FloatReg[numPhysicalFloatRegs];
---
> intRegFile.resize(numPhysicalIntRegs);
> floatRegFile.resize(numPhysicalFloatRegs);
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< memset(intRegFile, 0, sizeof(*intRegFile));
< memset(floatRegFile, 0, sizeof(*floatRegFile));
---
> //memset(intRegFile, 0, sizeof(*intRegFile));
> //memset(floatRegFile, 0, sizeof(*floatRegFile));
302c303
< #endif // __CPU_O3_CPU_REGFILE_HH__
---
> #endif
< *
< * Authors: Kevin Lim
< * Gabe Black
32,33c29,30
< #ifndef __CPU_O3_CPU_REGFILE_HH__
< #define __CPU_O3_CPU_REGFILE_HH__
---
> #ifndef __CPU_O3_REGFILE_HH__
> #define __CPU_O3_REGFILE_HH__
35,36d31
< // @todo: Destructor
<
38a34
> #include "arch/types.hh"
48,51c44
< // This really only depends on the ISA, and not the Impl. It might be nicer
< // to see if I can make it depend on nothing...
< // Things that are in the ifdef FULL_SYSTEM are pretty dependent on the ISA,
< // and should go in the AlphaFullCPU.
---
> #include <vector>
52a46,50
> /**
> * Simple physical register file class.
> * Right now this is specific to Alpha until we decide if/how to make things
> * generic enough to support other ISAs.
> */
58a57
> typedef TheISA::FloatRegBits FloatRegBits;
62,63c61,64
< //Note that most of the definitions of the IntReg, FloatReg, etc. exist
< //within the Impl/ISA class and not within this PhysRegFile class.
---
> typedef union {
> FloatReg d;
> FloatRegBits q;
> } PhysFloatReg;
65,67c66,67
< //Will need some way to allow stuff like swap_palshadow to access the
< //correct registers. Might require code changes to swap_palshadow and
< //other execution contexts.
---
> // Note that most of the definitions of the IntReg, FloatReg, etc. exist
> // within the Impl/ISA class and not within this PhysRegFile class.
69,70c69,70
< //Will make these registers public for now, but they probably should
< //be private eventually with some accessor functions.
---
> // Will make these registers public for now, but they probably should
> // be private eventually with some accessor functions.
73a74,77
> /**
> * Constructs a physical register file with the specified amount of
> * integer and floating point registers.
> */
85a90
> /** Reads an integer register. */
102c107
< FloatReg floatReg = floatRegFile.readReg(reg_idx, width);
---
> FloatReg floatReg = floatRegFile[reg_idx].d;
109a115
> /** Reads a floating point register (double precision). */
117c123
< FloatReg floatReg = floatRegFile.readReg(reg_idx);
---
> FloatReg floatReg = floatRegFile[reg_idx].d;
124a131
> /** Reads a floating point register as an integer. */
132c139
< FloatRegBits floatRegBits = floatRegFile.readRegBits(reg_idx, width);
---
> FloatRegBits floatRegBits = floatRegFile[reg_idx].q;
147c154
< FloatRegBits floatRegBits = floatRegFile.readRegBits(reg_idx);
---
> FloatRegBits floatRegBits = floatRegFile[reg_idx].q;
154a162
> /** Sets an integer register to the given value. */
162c170,171
< intRegFile[reg_idx] = val;
---
> if (reg_idx != TheISA::ZeroReg)
> intRegFile[reg_idx] = val;
164a174
> /** Sets a single precision floating point register to the given value. */
175c185,186
< floatRegFile.setReg(reg_idx, val, width);
---
> if (reg_idx != TheISA::ZeroReg)
> floatRegFile[reg_idx].d = width;
177a189
> /** Sets a double precision floating point register to the given value. */
188c200,201
< floatRegFile.setReg(reg_idx, val);
---
> if (reg_idx != TheISA::ZeroReg)
> floatRegFile[reg_idx].d = val;
190a204
> /** Sets a floating point register to the given integer value. */
201c215
< floatRegFile.setRegBits(reg_idx, val, width);
---
> floatRegFile[reg_idx].q = val;
214c228
< floatRegFile.setRegBits(reg_idx, val);
---
> floatRegFile[reg_idx].q = val;
217c231
< uint64_t readPC()
---
> MiscReg readMiscReg(int misc_reg, unsigned thread_id)
219c233
< return pc;
---
> return miscRegs[thread_id].readReg(misc_reg);
222c236,237
< void setPC(uint64_t val)
---
> MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault,
> unsigned thread_id)
224c239,240
< pc = val;
---
> return miscRegs[thread_id].readRegWithEffect(misc_reg, fault,
> cpu->xcBase(thread_id));
227c243
< void setNextPC(uint64_t val)
---
> Fault setMiscReg(int misc_reg, const MiscReg &val, unsigned thread_id)
229c245
< npc = val;
---
> return miscRegs[thread_id].setReg(misc_reg, val);
232,234c248,249
< //Consider leaving this stuff and below in some implementation specific
< //file as opposed to the general register file. Or have a derived class.
< MiscReg readMiscReg(int misc_reg)
---
> Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val,
> unsigned thread_id)
236,238c251,252
< // Dummy function for now.
< // @todo: Fix this once proxy XC is used.
< return 0;
---
> return miscRegs[thread_id].setRegWithEffect(misc_reg, val,
> cpu->xcBase(thread_id));
241,247d254
< Fault setMiscReg(int misc_reg, const MiscReg &val)
< {
< // Dummy function for now.
< // @todo: Fix this once proxy XC is used.
< return NoFault;
< }
<
249a257
> /** Sets an interrupt flag. */
253,254d260
< // These should be private eventually, but will be public for now
< // so that I can hack around the initregs issue.
257c263
< IntReg *intRegFile;
---
> std::vector<IntReg> intRegFile;
260c266
< FloatReg *floatRegFile;
---
> std::vector<PhysFloatReg> floatRegFile;
263c269
< MiscRegFile miscRegs;
---
> MiscRegFile miscRegs[Impl::MaxThreads];
265,270d270
< /** Program counter. */
< Addr pc;
<
< /** Next-cycle program counter. */
< Addr npc;
<
273,274d272
< // This is ISA specifc stuff; remove it eventually once ISAImpl is used
< // IntReg palregs[NumIntRegs]; // PAL shadow registers
276d273
< bool pal_shadow; // using pal_shadow registers
279a277
> /** CPU pointer. */
282a281
> /** Sets the CPU pointer. */
284a284
> /** Number of physical integer registers. */
285a286
> /** Number of physical floating point registers. */
295,296c296,297
< intRegFile = new IntReg[numPhysicalIntRegs];
< floatRegFile = new FloatReg[numPhysicalFloatRegs];
---
> intRegFile.resize(numPhysicalIntRegs);
> floatRegFile.resize(numPhysicalFloatRegs);
298,299c299,300
< memset(intRegFile, 0, sizeof(*intRegFile));
< memset(floatRegFile, 0, sizeof(*floatRegFile));
---
> //memset(intRegFile, 0, sizeof(*intRegFile));
> //memset(floatRegFile, 0, sizeof(*floatRegFile));
302c303
< #endif // __CPU_O3_CPU_REGFILE_HH__
---
> #endif